summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
* [DebugInfo] Fix printing of DW_LNS_set_isaJames Henderson2019-12-112-1/+53
| | | | | | | | | | | | | | | | | The Isa register is a uint8_t, but at least on Windows this is internally an unsigned char, which meant that prior to this patch it got formatted as an ASCII character, rather than a decimal number. This patch fixes this by casting it to a uint64_t before printing. I did it this way instead of using a uint8_t formatter because a) it is simpler, and b) it allows us to change the internal type of Isa in the future without this code breaking. I also took the opportunity to test the printing of the other standard opcodes. Reviewed by: probinson Differential Revision: https://reviews.llvm.org/D71274
* [lldb][NFC] Remove dead metadata code in ClangASTSourceProxyRaphael Isemann2019-12-111-12/+0
|
* Rollback assumeAligned in MemorySanitizerGuillaume Chatelet2019-12-111-18/+22
| | | | | | | | | | | | Summary: Rollback of parts of D71213. After digging more into the code I think we should leave 0 when creating the instructions (CreateMemcpy, CreateMaskedStore, CreateMaskedLoad). It's probably fine for MemorySanitizer because Alignement is resolved but I'm having a hard time convincing myself it has no impact at all (although tests are passing). Reviewers: courbet Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71332
* [Analyzer] Iterator Modeling: Print Container Data and Iterator Positions ↵Adam Balogh2019-12-112-0/+84
| | | | | | | | | | | | when printing the Program State Debugging the Iterator Modeling checker or any of the iterator checkers is difficult without being able to see the relations between the iterator variables and their abstract positions, as well as the abstract symbols denoting the begin and the end of the container. This patch adds the checker-specific part of the Program State printing to the Iterator Modeling checker.
* [lldb][NFC] Remove ClangExternalASTSourceCommon::g_TotalSizeOfMetadataRaphael Isemann2019-12-111-7/+0
| | | | Turns out this counter is doing literally nothing beside counting.
* [AArch64][SVE] Add DAG combine rules for gather loads and sext/zextAndrzej Warzynski2019-12-119-134/+609
| | | | | | | | | | | | | | | | Summary: These changes allow us to support sign-extending gather loads with the exisiting intrinsics (i.e. @llvm.aarch64.sve.ld1.gather.*). Reviewers: sdesmalen, huntergr, kmclaughlin, efriedma, rengolin, rovka, dancgr, mgudim Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits Tags: #llvm Differential revision: https://reviews.llvm.org/D70812
* [SYCL] Add support for auxiliary triple specification to FrontendAlexey Bader2019-12-113-3/+10
| | | | | | | | | | | | | | | | | Summary: Add host predefined macros to compilation for SYCL device, which is required for pre-processing host specific includes (e.g. system headers). Reviewers: ABataev, jdoerfert Subscribers: ebevhan, Anastasia, cfe-commits, keryell, Naghasan, Fznamznon Tags: #clang Differential Revision: https://reviews.llvm.org/D71286 Signed-off-by: Alexey Bader <alexey.bader@intel.com>
* CodeGen: Allow annotations on globals in non-zero address spaceNicolai Hähnle2019-12-112-5/+17
| | | | | | | | | | | | | | | | | | | | | | Summary: Attribute annotations are recorded in a special global composite variable that points to annotation strings and the annotated objects. As a restriction of the LLVM IR type system, those pointers are all pointers to address space 0, so let's insert an addrspacecast when the annotated global is in a non-0 address space. Since this addrspacecast is only reachable from the global annotations object, this should allow us to represent annotations on all globals regardless of which addrspacecasts are usually legal for the target. Reviewers: rjmccall Subscribers: cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D71208
* gn build: Merge afb13afcf22LLVM GN Syncbot2019-12-111-1/+6
|
* [ARM][MVE] Factor out an IntrinsicMX multiclass.Simon Tatham2019-12-112-27/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The ACLE intrinsics for MVE contain a lot of pairs of functions with `_m` and `_x` in the name, wrapping a predicated MVE instruction which only partially overwrites its output register. They have the common pattern that the `_m` variant takes an initial argument called 'inactive', of the same type as the return value, supplying the input value of the output register, so that lanes disabled by the predication will be taken from that parameter; the `_x` variant omits that initial argument, and simply sets it to undef. That common pattern is simple enough to wrap into a multiclass, which should save a lot of effort in setting up all the rest of the `_x` variants. In this commit I introduce `multiclass IntrinsicMX` in `arm_mve_defs.td`, and convert existing generation of m/x pairs to use it. This allows me to remove the `PredicatedImmediateVectorShift` multiclass (from D71065) completely, because the new multiclass makes it so much simpler that it's not worth bothering to define it at all. Reviewers: MarkMurrayARM, miyuki Reviewed By: MarkMurrayARM, miyuki Subscribers: kristof.beyls, dmgreen, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D71335
* [llvm-readobj][llvm-readelf] - Remove excessive empty lines when reporting ↵Georgii Rymar2019-12-119-129/+94
| | | | | | | | | | errors and warnings. After recent changes it is now seems possible to get rid of printing '\n' before each error and warning. This makes the output cleaner. Differential revision: https://reviews.llvm.org/D71246
* Revert "Reland [AArch64][MachineOutliner] Return address signing for ↵Oliver Stannard2019-12-1112-1275/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | outlined functions" This reverts commit cec2d5c17457722113580251c8a045fa9aca9b1b. Reverting because this is still creating outlined functions with return address signing instructions with mismatches SP values. For example: int *volatile v; void foo(int x) { int a[x]; v = &a[0]; v = &a[0]; v = &a[0]; v = &a[0]; v = &a[0]; v = &a[0]; } void bar(int x) { int a[x]; v = 0; v = &a[0]; v = &a[0]; v = &a[0]; v = &a[0]; v = &a[0]; } This generates these two outlined functions, both of which modify SP between the paciasp and retaa instructions: $ clang --target=aarch64-arm-none-eabi -march=armv8.3-a -c test2.c -o - -S -Oz -mbranch-protection=pac-ret+leaf ... OUTLINED_FUNCTION_0: // @OUTLINED_FUNCTION_0 .cfi_sections .debug_frame .cfi_startproc // %bb.0: paciasp .cfi_negate_ra_state mov w8, w0 lsl x8, x8, #2 add x8, x8, #15 // =15 mov x9, sp and x8, x8, #0x7fffffff0 sub x8, x9, x8 mov x29, sp mov sp, x8 adrp x9, v retaa ... OUTLINED_FUNCTION_1: // @OUTLINED_FUNCTION_1 .cfi_startproc // %bb.0: paciasp .cfi_negate_ra_state str x8, [x9, :lo12:v] str x8, [x9, :lo12:v] str x8, [x9, :lo12:v] str x8, [x9, :lo12:v] str x8, [x9, :lo12:v] mov sp, x29 retaa
* [TableGen] Add bang-operators !getop and !setop.Simon Tatham2019-12-118-10/+172
| | | | | | | | | | | | | | | | | | | | | | Summary: These allow you to get and set the operator of a dag node, without affecting its list of arguments. `!getop` is slightly fiddly because in many contexts you need its return value to have a static type more specific than 'any record'. It works to say `!cast<BaseClass>(!getop(...))`, but it's cumbersome, so I made `!getop` take an optional type suffix itself, so that can be written as the shorter `!getop<BaseClass>(...)`. Reviewers: hfinkel, nhaehnle Reviewed By: nhaehnle Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71191
* [Analyzer][NFC] Iterator Checkers - Separate iterator modeling and the ↵Adam Balogh2019-12-118-1131/+1429
| | | | | | | | | | actual checkers A monolithic checker class is hard to maintain. This patch splits it up into a modeling part, the three checkers and a debug checker. The common functions are moved into a library. Differential Revision: https://reviews.llvm.org/D70320
* [clang-tidy] Link shared library clangTidyOpenMPModule to library ↵Adam Balogh2019-12-111-0/+1
| | | | | | LLVMFrontendOpenMP Building shared libs was broken, it is fixed now.
* [AArch64][SVE] Implement intrinsics for non-temporal loads & storesKerry McLaughlin2019-12-117-3/+311
| | | | | | | | | | | | | | | | | | | | Summary: Adds the following intrinsics: - llvm.aarch64.sve.ldnt1 - llvm.aarch64.sve.stnt1 This patch creates masked loads and stores with the MONonTemporal flag set when used with the intrinsics above. Reviewers: sdesmalen, paulwalker-arm, dancgr, mgudim, efriedma, rengolin Reviewed By: efriedma Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71000
* [PowerPC][NFC] add test case for lwa - loop ds form prepczhengsz2019-12-111-0/+73
|
* [Clang] Pragma vectorize_width() implies vectorize(enable)Sjoerd Meijer2019-12-113-17/+70
| | | | | | | | | | | | | | | | | | | | | | Let's try this again; this has been reverted/recommited a few times. Last time this got reverted because for this loop: void a() { #pragma clang loop vectorize(disable) for (;;) ; } vectorisation was incorrectly enabled and the vectorize.enable metadata was set due to a logic error. But with this fixed, we now imply vectorisation when: 1) vectorisation is enabled, which means: VectorizeWidth > 1, 2) and don't want to add it when it is disabled or enabled, otherwise we would be incorrectly setting it or duplicating the metadata, respectively. This should fix PR27643. Differential Revision: https://reviews.llvm.org/D69628
* [lldb][NFC] Cleanup includes in FormatManagerTests.cppRaphael Isemann2019-12-111-13/+0
|
* [ARM][LowOverheadLoops] Remove dead loop update instructions.Sjoerd Meijer2019-12-1111-9/+638
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After creating a low-overhead loop, the loop update instruction was still lingering around hurting performance. This removes dead loop update instructions, which in our case are mostly SUBS instructions. To support this, some helper functions were added to MachineLoopUtils and ReachingDefAnalysis to analyse live-ins of loop exit blocks and find uses before a particular loop instruction, respectively. This is a first version that removes a SUBS instruction when there are no other uses inside and outside the loop block, but there are some more interesting cases in test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll which shows that there is room for improvement. For example, we can't handle this case yet: .. dlstp.32 lr, r2 .LBB0_1: mov r3, r2 subs r2, #4 vldrh.u32 q2, [r1], #8 vmov q1, q0 vmla.u32 q0, q2, r0 letp lr, .LBB0_1 @ %bb.2: vctp.32 r3 .. which is a lot more tricky because r2 is not only used by the subs, but also by the mov to r3, which is used outside the low-overhead loop by the vctp instruction, and that requires a bit of a different approach, and I will follow up on this. Differential Revision: https://reviews.llvm.org/D71007
* [ARM][MVE] Add intrinsics for immediate shifts. (reland)Simon Tatham2019-12-118-54/+1274
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the family of `vshlq_n` and `vshrq_n` ACLE intrinsics, which shift every lane of a vector left or right by a compile-time immediate. They mostly work by expanding to the IR `shl`, `lshr` and `ashr` operations, with their second operand being a vector splat of the immediate. There's a fiddly special case, though. ACLE specifies that the immediate in `vshrq_n` can take values up to //and including// the bit size of the vector lane. But LLVM IR thinks that shifting right by the full size of the lane is UB, and feels free to replace the `lshr` with an `undef` half way through the optimization pipeline. Hence, to keep this legal in source code, I have to detect it at codegen time. Logical (unsigned) right shifts by the element size are handled by simply emitting the zero vector; arithmetic ones are converted into a shift of one bit less, which will always give the same output. In order to do that check, I also had to enhance the tablegen MveEmitter so that it can cope with converting a builtin function's operand into a bare integer to pass to a code-generating subfunction. Previously the only bare integers it knew how to handle were flags generated from within `arm_mve.td`. Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard Reviewed By: dmgreen, MarkMurrayARM Subscribers: echristo, hokein, rdhindsa, kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D71065
* [lldb/DWARF] Add support for DW_AT_loclists_base&DW_FORM_loclistxPavel Labath2019-12-116-3/+174
| | | | | | | | | | | | | | | | | | | | | | Summary: This adds support for DWARF5 location lists which are specified indirectly, via an index into the debug_loclists offset table. This includes parsing the DW_AT_loclists_base attribute which determines the location of this offset table, and support for new form DW_FORM_loclistx which is used in conjuction with DW_AT_location to refer to the location lists in this way. The code uses the llvm class to parse the offset information, and I've also tried to structure it similarly to how the relevant llvm functionality works. Reviewers: JDevlieghere, aprantl, clayborg Subscribers: lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D71268
* [NFC] Correct the example in the comments of JSON.h to avoid misleadQingShan Zhang2019-12-111-1/+1
| | | | user
* [ARM][TypePromotion] Enable by defaultSam Parker2019-12-1111-13/+31
| | | | | | | | | Enable the TypePromotion pass my default (again). This patch was originally committed in 393dacacf7e7. This patch was reverted in a38396939c54. Differential Revision: https://reviews.llvm.org/D70998
* [NFC][PowerPC] Remove the dead conditions in the if(cond)QingShan Zhang2019-12-111-5/+1
|
* [MCRegInfo] Add sub_and_superregs_inclusive iterator range.Florian Hahn2019-12-111-0/+8
| | | | | | | | Reviewers: evandro, qcolombet, paquette, MatzeB, arsenm Reviewed By: paquette Differential Revision: https://reviews.llvm.org/D70566
* [clangd] Deduplicate refs from index for cross-file rename.Haojian Wu2019-12-113-14/+77
| | | | | | | | | | | | | | | | | | | | | | Summary: If the index returns duplicated refs, it will trigger the assertion in BuildRenameEdit (we expect the processing position is always larger the the previous one, but it is not true if we have duplication), and also breaks our heuristics. This patch make the code robost enough to handle duplications, also save some cost of redundnat llvm::sort. Though clangd's index doesn't return duplications, our internal index kythe will. Reviewers: ilya-biryukov Subscribers: MaskRay, jkorous, mgrang, arphaman, kadircet, usaxena95, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D71300
* [AArch64][SVE] Move TableGen class definitions for gather loads (NFC)Andrzej Warzynski2019-12-111-17/+17
| | | | | | | Move 2 intrinsic class definitions so that they're all clustered in one place. Patch submitted to test commit access.
* [PowerPC] [CodeGen] Use MachineBranchProbabilityInfo in EarlyIfPredicator to ↵shkzhang2019-12-111-3/+7
| | | | | | | | | | | | | | | | | | | avoid the potential bug Summary: In the function `EarlyIfPredicator::shouldConvertIf()`, we call `TII->isProfitableToIfCvt()` with `BranchProbability::getUnknown()`, it may cause the potential assertion error for those hook which use `BranchProbability` in `isProfitableToIfCvt()`, for example `SystemZ`. `SystemZ` use `Probability < BranchProbability(1, 8))` in the function `SystemZInstrInfo::isProfitableToIfCvt()`, if we call this function with `BranchProbability::getUnknown()`, it will cause assertion error. This patch is to fix the potential bug. Reviewed By: ThomasRaoux Differential Revision: https://reviews.llvm.org/D71273
* [LiveRegUnits] Add phys_regs_and_masks iterator range (NFC).Florian Hahn2019-12-113-42/+44
| | | | | | | | | | | This iterator range just includes physical registers and register masks, which are interesting when dealing with register liveness. Reviewers: evandro, t.p.northover, paquette, MatzeB, arsenm Reviewed By: paquette Differential Revision: https://reviews.llvm.org/D70562
* [llvm-readelf] - Do no print an empty symbol version as "<corrupt>"Georgii Rymar2019-12-112-2/+2
| | | | | | | | | | | | | It is discussed here https://reviews.llvm.org/D71118#inline-643172 Currently when a version is empty, llvm-readelf prints: "000: 0 (*local*) 2 (<corrupt>)" But GNU readelf does not treat empty section as corrupt. There is no sense in having empty versions anyways it seems, but this change is for consistency with GNU. Differential revision: https://reviews.llvm.org/D71243
* [DWARF5][SplitDwarf] Set default state for -fsplit-dwarf-inlining to be false.Alexey Lapshin2019-12-112-2/+5
| | | | | | | | | The -fsplit-dwarf-inlining option does not conform to DWARF5 standard. It creates children for Skeleton compilation unit. We need default behavior to be DWARF5 compatible. Thus set default state for -fsplit-dwarf-inlining into "false". Differential Revision: https://reviews.llvm.org/D71304
* [CodeComplete] Fix a crash in preferred type and signature helpIlya Biryukov2019-12-112-3/+14
| | | | | | | | | | | | | | Summary: Null type pointers could be dereferenced in some cases. Reviewers: kadircet, sammccall Reviewed By: sammccall Subscribers: cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D71329
* [Alignment][NFC] Introduce Align in SROAGuillaume Chatelet2019-12-111-26/+26
| | | | | | | | | | | | | | | Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71277
* [llvm-readobj] Fix/improve printing WinEH unwind info for linked PE imagesMartin Storsjö2019-12-115-6/+405
| | | | | | | | | | | | | | | | | | | | ARMWinEHPrinter was already designed to handle linked PE images (since d2941b43f40d), but resolving symbols didn't consistently take the image base into account (as linked images seldom have a symbol table, except for in MinGW setups). Win64EHDumper wasn't really designed to handle linked images (it would crash if executed on such a file), but a few concepts (getSymbol, taking a virtual address instead of a relocation, and getSectionContaining for finding the section containing a certain virtual address) can be borrowed from ARMWinEHPrinter. Adjust ARMWinEHPrinter to print the address of the exception handler routine as a VA instead of an RVA, consistently with other addresses in the same printout, and make Win64EHDumper print addresses similarly for image cases. Differential Revision: https://reviews.llvm.org/D71303
* [PowerPC] Exploitate the Vector Integer Average InstructionsQingShan Zhang2019-12-112-72/+142
| | | | | | | | | | | PowerPC has instruction to do the semantics of this piece of code: vector int foo(vector int m, vector int n) { return (m + n + 1) >> 1; } This patch is adding the match rule to select it. Differential Revision: https://reviews.llvm.org/D71002
* [LegalizeTypes] Remove manual worklist management from SoftenFloatRes_FP_EXTEND.Craig Topper2019-12-103-9/+2
| | | | | | I think this is no longer needed. The system should take care of legalizing any new nodes that are added. I think this might have been needed prior to r371709 or r307053.
* [ELF] Move a computeIsPreemptible() pass into ICF. NFCFangrui Song2019-12-102-5/+6
| | | | | | | | Address post-commit review for D71163. Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D71326
* [SanitizerCommon] Reduce wasting memory in LowLevelAllocator.Igor Kudrin2019-12-112-1/+12
| | | | | | | | | MmapOrDie allocates memory multiple to page size. LowLevelAllocator should use all that memory for the internal buffer because there are chances that subsequent requests may be small enough to fit in that space. Differential Revision: https://reviews.llvm.org/D71275
* [cxx_status] Re-add missing cell.Richard Smith2019-12-101-0/+1
|
* [c++20] Implement P1946R0: allow defaulted comparisons to take theirRichard Smith2019-12-105-13/+58
| | | | arguments by value.
* [c++20] Delete defaulted comparison functions if they would invoke anRichard Smith2019-12-108-17/+154
| | | | inaccessible comparison function.
* Change the mtc Makefile to check $SDKROOT value insteadJason Molenda2019-12-101-3/+8
| | | | | | | | | | of depending on it being set in the environment. Fred's change from October assumed that SDKROOT was set in the environment so that 'xcrun --show-sdk-path' would print the path. If it was passed in as a Makefile variable, it wouldn't be set in the environment and xcrun --show-sdk-path would always show the macOS SDK path. When running the lldb testsuite against an ios device via lit, this seems to be the case.
* Revert "[DebugInfo] Refactored macro related generation, added a test case ↵Nico Weber2019-12-103-89/+19
| | | | | | | | | | | | | | | | for macinfo.dwo emission." This reverts commit 307f60a1a3ff04313a75e2fc11bc14df4fc2ffb8. DebugInfo/X86/debug-macinfo-split-dwarf.ll fails on Windows: Command Output (stdout): -- $ ":" "RUN: at line 1" $ "c:\src\llvm-project\out\gn\bin\llc.exe" "-mtriple=x86_64-pc-windows-gnu" "-O0" "-split-dwarf-file=foo.dwo" "-filetype=obj" Assertion failed: Section && "Cannot switch to a null section!", file ../../llvm/lib/MC/MCStreamer.cpp, line 1103 Stack dump: 0. Program arguments: c:\src\llvm-project\out\gn\bin\llc.exe -mtriple=x86_64-pc-windows-gnu -O0 -split-dwarf-file=foo.dwo -filetype=obj
* Fix mishandling of invalid-but-non-empty nested name specifiers in nameRichard Smith2019-12-102-5/+16
| | | | | | | | classification. We were accidentally treating invalid scope specs as being empty, resulting in our trying to form an ADL-only call with a qualified callee, which tripped up an assert later on.
* [llvm-ar] Improve tool selection heuristicFangrui Song2019-12-105-7/+72
| | | | | | | | | | | | | | | | If llvm-ar is installed at arm-pokymllib32-linux-gnueabi-llvm-ar, it may think it is llvm-lib due to the "lib" substring. Improve the heuristic to make all the following work as intended: llvm-ar-9 (llvm-9 package on Debian) llvm-ranlib.exe Lib.exe (reported by D44808) arm-pokymllib32-linux-gnueabi-llvm-ar (reported by D71030) Reviewed By: raj.khem, rupprecht Differential Revision: https://reviews.llvm.org/D71302
* [X86] Split v64i1 arguments into 2 v32i1s that will be promoted to v32i8 ↵Craig Topper2019-12-102-445/+17
| | | | | | under min-legal-vector-width=256 This is an improvement to 88dacbd43625cf7aad8a01c0c3b92142c4dc0970
* Reland "Enable `-funwind-tables` flag when building libunwind"Sergej Jaskiewicz2019-12-116-2/+47
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Relands https://reviews.llvm.org/D70815. The original commit set `CMAKE_TRY_COMPILE_TARGET_TYPE` to `STATIC_LIBRARY` globally in libunwind/CMakeLists.txt, which effectively disabled the linking step in CMake checks. This broke some builds (see 938c70b86c7d2165f8c28d5700e9c1ac1263307e). Here we set CMAKE_TRY_COMPILE_TARGET_TYPE to STATIC_LIBRARY only when checking for presence of the `-funwind-tables` flag, and then set it back to the original value so it doesn't affect other checks. Reviewers: mstorsjo, jfb Subscribers: mgorny, christof, libcxx-commits Tags: #libc Differential Revision: https://reviews.llvm.org/D71117
* [c++20] Implement P1185R2 (as modified by P2002R0).Richard Smith2019-12-1010-52/+424
| | | | | | For each defaulted operator<=> in a class that doesn't explicitly declare any operator==, also inject a matching implicit defaulted operator==.
* [llvm][MIRVRegNamerUtil] Adding hashing against MachineInstr flags.Puyan Lotfi2019-12-102-1/+38
| | | | | | | | Now, flags will result in differing hashes for a given MI. In effect, if you have two instructions with everything identical except for their flags then you should get two different hashes and fewer collisions. Differential Revision: https://reviews.llvm.org/D70479
OpenPOWER on IntegriCloud