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* [Docs] Clarify what the object-size sanitizer does.George Burgess IV2016-04-251-5/+8
| | | | | | | | | | Currently, the UBSan docs make it sound like the object-size sanitizer will only detect out-of-bounds reads/writes. It also catches some operations that don't necessarily access memory (invalid downcasts, calls of methods on invalid pointers, ...). This patch adds a note about this behavior in the docs. llvm-svn: 267447
* ARM Limited license agreement from the copyright/patent holderJonathan Peyton2016-04-251-0/+50
| | | | | | | | | | | | | | | | | I have prepared some patches for LLVM OpenMP runtime, mostly addressing ARMv8 support. Before I upstream them, I must address legal issues that arose around my planned contribution. I was advised that before I send any substantial commit, I need to make sure that LICENSE.txt file in the projects repository contains a statement submitted by ARM, similar to the one provided by Intel (see "a license agreement from the copyright/patent holders"). This is the same situation as with top-level LLVM project: ARM has provided the same statement in http://llvm.org/svn/llvm-project/llvm/trunk/lib/Target/ARM/LICENSE.TXT file. Patch by Paul Osmialowski Differential Revision: http://reviews.llvm.org/D19319 llvm-svn: 267446
* Extract some constant factors from "SCEVAddExprs"Johannes Doerfert2016-04-252-0/+78
| | | | | | | | | Additive expressions can have constant factors too that we can extract and thereby simplify the internal representation. For now we do compute the gcd of all constant factors but only extract the same (possibly negated) factor if there is one. llvm-svn: 267445
* When deducing template parameters from base classes of an argument type, don'tRichard Smith2016-04-252-76/+97
| | | | | | | preserve any deduced types from a failed deduction to a subsequent attempt at deduction. Patch by Erik Pilkington! llvm-svn: 267444
* test commitFrancis Ricci2016-04-251-1/+1
| | | | llvm-svn: 267443
* Do not check all GEPs for assumptionsJohannes Doerfert2016-04-253-12/+81
| | | | | | | | | | Before, we checked all GEPs in a statement in order to derive out-of-bound assumptions. However, this can not only introduce new parameters but it is also not clear what we can learn from GEPs that are not immediately used in a memory accesses inside the SCoP. As this case is very rare, no actual change in the behaviour is expected. llvm-svn: 267442
* Only add user assumptions on known parameters [NFC]Johannes Doerfert2016-04-253-1/+131
| | | | | | | | | | | | Before, assumptions derived from llvm.assume could reference new parameters that were not known to the SCoP before. These were neither beneficial to the representation nor to the user that reads the emitted remark. Now we project them out and keep only user assumptions on known parameters. Nevertheless, the new parameters are still part of the SCoPs parameter space as the SCEVAffinator currently adds them on demand. llvm-svn: 267441
* [LVI] Clarify comments describing the lattice valuesPhilip Reames2016-04-251-5/+10
| | | | | | There has been much recent confusion about the partition in the lattice between constant and non-constant values. Hopefully, documenting this will prevent confusion going forward. llvm-svn: 267440
* [LVI] Split solveBlockValueConstantRange into two [NFC]Philip Reames2016-04-251-31/+63
| | | | | | This function handled both unary and binary operators. Cloning and specializing leads to much easier to follow code with minimal duplicatation. llvm-svn: 267438
* [gold] Fix linkInModule and extend common.ll test.Evgeniy Stepanov2016-04-255-12/+32
| | | | | | | | | | Fix early exit from linkInModule. IRMover::move returns false on success and true on error. Add a few more cases of merged common linkage variables with different sizes and alignments. llvm-svn: 267437
* Fix typo from r267432.Chad Rosier2016-04-251-2/+2
| | | | llvm-svn: 267436
* [Hexagon] Use llvm-mc instead of llc in an MC testcaseKrzysztof Parzyszek2016-04-251-0/+9
| | | | | | Remember to svn add the new file. llvm-svn: 267435
* [Hexagon] Use llvm-mc instead of llc in an MC testcaseKrzysztof Parzyszek2016-04-251-9/+0
| | | | llvm-svn: 267434
* [Hexagon] Register save/restore functions do not follow regular conventionsKrzysztof Parzyszek2016-04-255-45/+123
| | | | | | Do not mark them as modifying any of the volatile registers by default. llvm-svn: 267433
* [ValueTracking] Add an additional test case for r266767 where one operand is ↵Chad Rosier2016-04-251-0/+24
| | | | | | a const. llvm-svn: 267432
* Resubmit "Refactor raw pdb dumper into library"Zachary Turner2016-04-2513-348/+737
| | | | | | | This fixes a number of endianness issues as well as an ODR violation that hopefully causes everything to be happy. llvm-svn: 267431
* [ValueTracking] Improve isImpliedCondition when the dominating cond is false.Chad Rosier2016-04-256-13/+409
| | | | llvm-svn: 267430
* [gold-plugin] Remove dead assignment. NFC.Davide Italiano2016-04-251-1/+0
| | | | llvm-svn: 267429
* [ELFRelocs] Other architectures do not have *_NUM reloc.Davide Italiano2016-04-251-1/+0
| | | | | | | It also seems to be unused. Get rid of it. Thanks to Rafael for pointing out. llvm-svn: 267428
* dsymutil: Only warn about clang module DWO id mismatches in verbose mode.Adrian Prantl2016-04-252-2/+5
| | | | | | | | | | Until PR27449 (https://llvm.org/bugs/show_bug.cgi?id=27449) is fixed in clang this warning is pointless, since ASTFileSignatures will change randomly when a module is rebuilt. rdar://problem/25610919 llvm-svn: 267427
* add tests for potential CGP transform (PR27344)Sanjay Patel2016-04-251-0/+32
| | | | llvm-svn: 267426
* [Clang][Builtin][AVX512]Adding k-register logic intrinsics KAND, KANDN, KOR, ↵Michael Zuckerman2016-04-253-0/+104
| | | | | | | | KORTEST, KXNOR, KXOR, KUNPACK instruction set. Differential Revision: http://reviews.llvm.org/D19466 llvm-svn: 267425
* [lanai] Expand findClosestSuitableAluInstr check to consider offset register.Jacques Pienaar2016-04-251-3/+6
| | | | | | Previously findClosestSuitableAluInstr was only considering the base register when checking the current instruction for suitability. Expand check to consider the offset if the offset is a register. llvm-svn: 267424
* Refactor Scop parameter handlingJohannes Doerfert2016-04-252-57/+45
| | | | | | | | | The new handling is consistent with the remaining code, e.g., we do not create a new parameter id for each lookup call but copy an existing one. Additionally, we now use the implicit order defined by the Parameters set instead of an explicit one defined in a map. llvm-svn: 267423
* Fix ARM attribute parsing for Android after rL267291Tamas Berghammer2016-04-252-14/+26
| | | | | | Differential revision: http://reviews.llvm.org/D19480 llvm-svn: 267422
* skip TestBitfields.py on OS XTodd Fiala2016-04-251-0/+1
| | | | | | | tracked by: https://llvm.org/bugs/show_bug.cgi?id=27515 llvm-svn: 267421
* [PR27390] [CodeGen] Reject indexed loads in CombinerDAG.Marcin Koscielnicki2016-04-253-3/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | visitAND, when folding and (load) forgets to check which output of an indexed load is involved, happily folding the updated address output on the following testcase: target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" %typ = type { i32, i32 } define signext i32 @_Z8access_pP1Tc(%typ* %p, i8 zeroext %type) { %b = getelementptr inbounds %typ, %typ* %p, i64 0, i32 1 %1 = load i32, i32* %b, align 4 %2 = ptrtoint i32* %b to i64 %3 = and i64 %2, -35184372088833 %4 = inttoptr i64 %3 to i32* %_msld = load i32, i32* %4, align 4 %zzz = add i32 %1, %_msld ret i32 %zzz } Fix this by checking ResNo. I've found a few more places that currently neglect to check for indexed load, and tightened them up as well, but I don't have test cases for them. In fact, they might not be triggerable at all, at least with current targets. Still, better safe than sorry. Differential Revision: http://reviews.llvm.org/D19202 llvm-svn: 267420
* [mips][microMIPS] Revert commit r267137Hrvoje Varga2016-04-2510-32/+5
| | | | | | Commit r267137 was the reason for failing tests in LLVM test suite. llvm-svn: 267419
* [mips][microMIPS] Revert commit r266977Zlatko Buljan2016-04-2516-137/+9
| | | | | | Commit r266977 was reason for failing LLVM test suite with error message: fatal error: error in backend: Cannot select: t17: i32 = rotr t2, t11 ... llvm-svn: 267418
* [x86] auto-generate checks for cmov testsSanjay Patel2016-04-251-14/+32
| | | | llvm-svn: 267417
* Added Fixer implementation and fix() interface in clang-format for removing ↵Eric Liu2016-04-259-258/+835
| | | | | | | | | | | | | | | | | redundant code. Summary: After applying replacements, redundant code like extra commas or empty namespaces might be introduced. Fixer can detect and remove any redundant code introduced by replacements. The current implementation only handles redundant commas. Reviewers: djasper, klimek Subscribers: ioeric, mprobst, klimek, cfe-commits Differential Revision: http://reviews.llvm.org/D18551 llvm-svn: 267416
* Fix incorrect redundant expression in target AMDGPU.Etienne Bergeron2016-04-251-1/+1
| | | | | | | | | | | | | | | | | | | Summary: The expression is detected as a redundant expression. Turn out, this is probably a bug. ``` /home/etienneb/llvm/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:306:26: warning: both side of operator are equivalent [misc-redundant-expression] if (isSMRD(*FirstLdSt) && isSMRD(*FirstLdSt)) { ``` Reviewers: rnk, tstellarAMD Subscribers: arsenm, cfe-commits Differential Revision: http://reviews.llvm.org/D19460 llvm-svn: 267415
* [Clang][Builtin][AVX512]Adding intrinsics for vfpclass{sd|ss} ↵Michael Zuckerman2016-04-255-0/+187
| | | | | | | | vfpclass{pd|ps} instruction set Differential Revision: http://reviews.llvm.org/D19476 llvm-svn: 267414
* [analyzer] Let TK_PreserveContents span across the whole base region.Artem Dergachev2016-04-254-2/+68
| | | | | | | | | | | | If an address of a field is passed through a const pointer, the whole structure's base region should receive the TK_PreserveContents trait and avoid invalidation. Additionally, include a few FIXME tests shown up during testing. Differential Revision: http://reviews.llvm.org/D19057 llvm-svn: 267413
* [WinEH] Update SplitAnalysis::computeLastSplitPoint to cope with multiple EH ↵David Majnemer2016-04-255-18/+87
| | | | | | | | | | | | | | | | | | | successors We didn't have logic to correctly handle CFGs where there was more than one EH-pad successor (these are novel with WinEH). There were situations where a register was live in one exceptional successor but not another but the code as written would only consider the first exceptional successor it found. This resulted in split points which were insufficiently early if an invoke was present. This fixes PR27501. N.B. This removes getLandingPadSuccessor. llvm-svn: 267412
* [ARM] Add support for the X asm constraintSilviu Baranga2016-04-254-0/+200
| | | | | | | | | | | | | | | | | | Summary: This patch adds support for the X asm constraint. To do this, we lower the constraint to either a "w" or "r" constraint depending on the operand type (both constraints are supported on ARM). Fixes PR26493 Reviewers: t.p.northover, echristo, rengolin Subscribers: joker.eph, jgreenhalgh, aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D19061 llvm-svn: 267411
* [AMDGPU][llvm-mc] s_getreg/setreg* - Add hwreg(...) syntax.Artem Tamazov2016-04-259-15/+183
| | | | | | | | | | | | | Added hwreg(reg[,offset,width]) syntax. Default offset = 0, default width = 32. Possibility to specify 16-bit immediate kept. Added out-of-range checks. Disassembling is always to hwreg(...) format. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19329 llvm-svn: 267410
* Add support for R_X86_64_PC64.Rafael Espindola2016-04-252-0/+37
| | | | llvm-svn: 267409
* Model zext-extend instructionsJohannes Doerfert2016-04-2517-54/+424
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A zero-extended value can be interpreted as a piecewise defined signed value. If the value was non-negative it stays the same, otherwise it is the sum of the original value and 2^n where n is the bit-width of the original (or operand) type. Examples: zext i8 127 to i32 -> { [127] } zext i8 -1 to i32 -> { [256 + (-1)] } = { [255] } zext i8 %v to i32 -> [v] -> { [v] | v >= 0; [256 + v] | v < 0 } However, LLVM/Scalar Evolution uses zero-extend (potentially lead by a truncate) to represent some forms of modulo computation. The left-hand side of the condition in the code below would result in the SCEV "zext i1 <false, +, true>for.body" which is just another description of the C expression "i & 1 != 0" or, equivalently, "i % 2 != 0". for (i = 0; i < N; i++) if (i & 1 != 0 /* == i % 2 */) /* do something */ If we do not make the modulo explicit but only use the mechanism described above we will get the very restrictive assumption "N < 3", because for all values of N >= 3 the SCEVAddRecExpr operand of the zero-extend would wrap. Alternatively, we can make the modulo in the operand explicit in the resulting piecewise function and thereby avoid the assumption on N. For the example this would result in the following piecewise affine function: { [i0] -> [(1)] : 2*floor((-1 + i0)/2) = -1 + i0; [i0] -> [(0)] : 2*floor((i0)/2) = i0 } To this end we can first determine if the (immediate) operand of the zero-extend can wrap and, in case it might, we will use explicit modulo semantic to compute the result instead of emitting non-wrapping assumptions. Note that operands with large bit-widths are less likely to be negative because it would result in a very large access offset or loop bound after the zero-extend. To this end one can optimistically assume the operand to be positive and avoid the piecewise definition if the bit-width is bigger than some threshold (here MaxZextSmallBitWidth). We choose to go with a hybrid solution of all modeling techniques described above. For small bit-widths (up to MaxZextSmallBitWidth) we will model the wrapping explicitly and use a piecewise defined function. However, if the bit-width is bigger than MaxZextSmallBitWidth we will employ overflow assumptions and assume the "former negative" piece will not exist. llvm-svn: 267408
* Skip TestBitfileds on linuxPavel Labath2016-04-251-0/+1
| | | | | | | Test added in r267248 exposed a bug in handling of dwarf produced by clang>=3.9, which causes a crash during expression evaluation. Skip the test until this is sorted out. llvm-svn: 267407
* Test commit: modified comment. NFCAnna Thomas2016-04-251-1/+1
| | | | llvm-svn: 267406
* Handle invalid values of PLT entry size generated by linkerOmair Javaid2016-04-251-1/+4
| | | | | | | | Make sure we figure out correct plt entry field in case linker has generated a small value below realistic entry size like 4 bytes or below. Differential revision: http://reviews.llvm.org/D19252 llvm-svn: 267405
* Check only loop control of loops that are part of the regionJohannes Doerfert2016-04-253-4/+35
| | | | | | | This also removes a duplicated line of code in the region generator that caused a SPEC benchmark to fail with the new SCoPs. llvm-svn: 267404
* Initialize the invalid domain of an access with an empty setJohannes Doerfert2016-04-251-1/+3
| | | | llvm-svn: 267403
* Do not propagate invalid domains over back edgesJohannes Doerfert2016-04-251-0/+4
| | | | llvm-svn: 267402
* Introduce a parameter set type [NFC]Johannes Doerfert2016-04-255-26/+23
| | | | llvm-svn: 267401
* Remove unnecessary argument of the SCEVValidator [NFC]Johannes Doerfert2016-04-255-35/+20
| | | | llvm-svn: 267400
* Typo. NFC.Chad Rosier2016-04-251-1/+1
| | | | llvm-svn: 267399
* [Clang][AVX512][BUILTIN] Adding intrinsics for ↵Michael Zuckerman2016-04-254-0/+263
| | | | | | | | VSCATTERPF{1|0}{DPS|QPS|DPD|QPD} instruction set Differential Revision: http://reviews.llvm.org/D19313 llvm-svn: 267398
* [Hexagon] Correctly set "Flags" in ELF headerKrzysztof Parzyszek2016-04-252-3/+16
| | | | llvm-svn: 267397
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