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* Fix indentation.Rui Ueyama2016-07-071-1/+1
| | | | llvm-svn: 274719
* Add support to debugserver for some new ways to interact with dyldJason Molenda2016-07-077-193/+658
| | | | | | | | | | | | to find the solibs loaded in a process. Support two new ways of sending the jGetLoadedDynamicLibrariesInfos packet to debugserver and add a new jGetSharedCacheInfo packet. Update the documentation for these packets as well. The changes to lldb to use these will be a separate commit. <rdar://problem/25251243> llvm-svn: 274718
* Rename argument for consistency.Eric Christopher2016-07-072-22/+22
| | | | llvm-svn: 274717
* Remove the plumbing for isDarwinABI from EmitTailCallLoadFPAndRetAddr.Eric Christopher2016-07-072-9/+6
| | | | llvm-svn: 274716
* Use the MachineFunction that we've already queried for in the function.Eric Christopher2016-07-071-4/+2
| | | | llvm-svn: 274715
* Remove the plumbing for isDarwinABI from the PrepareTailCall hierarchy.Eric Christopher2016-07-071-10/+8
| | | | llvm-svn: 274714
* [CUDA] Fix "control reaches end of non-void function" warnings in Cuda.cpp.Justin Lebar2016-07-071-0/+6
| | | | | | | | | | Some compilers are too dumb to realize that the switch statement covers all cases. (Don't use a "default" label, because we explicitly want to get a warning if our switch doesn't cover all the cases.) llvm-svn: 274713
* [PM] Avoid getResult on a higher level in LoopAccessAnalysisSean Silva2016-07-0722-28/+36
| | | | | | | Note that require<domtree> and require<loops> aren't needed because they come in implicitly via the loop pass manager. llvm-svn: 274712
* Remove the plumbing of 64-bitness from PrepareTailCall and functionsEric Christopher2016-07-071-13/+13
| | | | | | called by it. llvm-svn: 274711
* Sink call to get the MachineFunction into EmitTailCallStoreFPAndRetAddrEric Christopher2016-07-071-10/+7
| | | | | | and remove the argument. llvm-svn: 274710
* Remove unnecessary subtarget parameters in PPCTargetLowering.Eric Christopher2016-07-072-31/+26
| | | | llvm-svn: 274709
* [PM] Port TailCallElimSean Silva2016-07-065-2/+88
| | | | llvm-svn: 274708
* Fix missing member initializersMatt Arsenault2016-07-061-1/+1
| | | | | | | This fixes the -Werror build with some combination of warning flags. llvm-svn: 274707
* Revert "Retry "Include debug info for nested structs and classes""Adrian McCarthy2016-07-065-24/+12
| | | | | | | | | | Reverting because it causes a test failure on build bots (Modules/ModuleDebugInfo.cpp). Failure does not reproduce locally. svn revision: rL274698 This reverts commit 3c5ed6599b086720aab5b8bd6941149d066806a6. llvm-svn: 274706
* [PM] Port CorrelatedValuePropagationSean Silva2016-07-065-7/+54
| | | | llvm-svn: 274705
* fix documentation comment. NFC.Junmo Park2016-07-061-2/+1
| | | | llvm-svn: 274704
* "frame variable" and "target variable" shouldn't allow us to get the address ↵Greg Clayton2016-07-061-14/+18
| | | | | | | | | | | | | | of bitfields. "frame variable" and "target variable" are trying to emulate the expression parser when doing things like: (lldb) frame variable &my_struct.my_bitfield And since the expression parser doesn't allow this, we shouldn't allow "frame variable" or "target variable" to succeed. <rdar://problem/27208607> llvm-svn: 274703
* Minor code cleanup. NFC.Junmo Park2016-07-061-1/+1
| | | | llvm-svn: 274702
* LLDB reads incorrect memory ranges when displaying bitfields when reading ↵Greg Clayton2016-07-061-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bits from file memory. Bitfields were not correctly describing their offsets within the integer that they are contained within. If we had a bitfield like: struct MyStruct { uint32_t a:8; uint32_t b:8; }; ClangASTContext::GetChildCompilerTypeAtIndex would say that child a and b had the following values in their respective ValueObjectChild objects: name byte-size bit-size bit-offset byte-offset-from-parent ==== ========= ======== ========== ======================= "a" 4 8 0 0 "b" 4 8 0 1 So if we had a "MyStruct" at address 0x1000, we would end up reading 4 bytes from 0x1000 for "a", and 4 bytes from 0x1001 for "b". The fix for this is to fix the "child_byte_offset" and "child_bitfield_bit_offset" values returned by ClangASTContext::GetChildCompilerTypeAtIndex() so that now the table looks like: name byte-size bit-size bit-offset byte-offset-from-parent ==== ========= ======== ========== ======================= "a" 4 8 0 0 "b" 4 8 8 0 Then we don't run into a problem when reading data from a file's section info using "target variable" before running. It will also stop us from not being able to display a bitfield values if the bitfield is in the last bit of memory before an unmapped region. (Like if address 0x1004 was unmapped and unreadable in the example above, if we tried to read 4 bytes from 0x1001, the memory read would fail and we wouldn't be able to display "b"). <rdar://problem/27208225> llvm-svn: 274701
* Enhance FuncUnwinders::GetUnwindPlanAtNonCallSite to detect when weJason Molenda2016-07-062-4/+78
| | | | | | | | | | | | | | | | | | may be in a function that is non-ABI conformant, and the eh_frame instructions correctly describe how to unwind out of this function, but the assembly parsing / arch default unwind plans would be incorrect. This is to address a problem that Ravitheja Addepally reported in http://reviews.llvm.org/D21221 - I wanted to try handling the problem with this approach which I think may be more generally helpful, Ravitheja tested it and said it solves the problem on Linux/FreeBSD. Ravi has a test case in http://reviews.llvm.org/D21221 that will be committed separately. Thanks for all the help on this one, Ravi. llvm-svn: 274700
* ThinLTO: Add test cases for promote+internalize.Peter Collingbourne2016-07-062-1/+43
| | | | | | | | | This tests the effect of both promotion and internalization on a module, and helps show that D21883 is NFC wrt promotion+internalization. Differential Revision: http://reviews.llvm.org/D21915 llvm-svn: 274699
* Retry "Include debug info for nested structs and classes"Adrian McCarthy2016-07-065-12/+24
| | | | | | | | | | This should work now that the LLVM-side of the change has landed successfully. Original Differential Revision: http://reviews.llvm.org/D21705 This reverts commit a30322e861c387e1088f47065d0438c6bb019879. llvm-svn: 274698
* Fix the installation of the vector<bool> data formatters in order to restore ↵Enrico Granata2016-07-061-4/+2
| | | | | | functionality llvm-svn: 274697
* [InstCombine] enhance (select X, C1, C2 --> ext X) to handle vectorsSanjay Patel2016-07-062-27/+46
| | | | | | | | | By replacing dyn_cast of ConstantInt with m_Zero/m_One/m_AllOnes, we allow these transforms for splat vectors. Differential Revision: http://reviews.llvm.org/D21899 llvm-svn: 274696
* Ensuring the bit-fields have the same type; MSVC will place the fields in ↵Aaron Ballman2016-07-061-1/+1
| | | | | | different allocation units otherwise. llvm-svn: 274695
* Minor formatting change, NFCVedant Kumar2016-07-061-7/+3
| | | | | | | The rest of llvm-cov does not use LLVM_ATTRIBUTE_UNUSED. Leave unused params unnamed to be consistent. llvm-svn: 274694
* Add testing coverage for r274582.Manman Ren2016-07-061-0/+21
| | | | llvm-svn: 274693
* [X86] Transform setcc + movzbl into xorl + setccMichael Kuperstein2016-07-0632-288/+523
| | | | | | | | | | | xorl + setcc is generally the preferred sequence due to the partial register stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller. This fixes PR28146. Differential Revision: http://reviews.llvm.org/D21774 llvm-svn: 274692
* [analyzer] Suppress false positives in std::shared_ptrDevin Coughlin2016-07-065-131/+197
| | | | | | | | | | | | | | | | | | | | | The analyzer does not model C++ temporary destructors completely and so reports false alarms about leaks of memory allocated by the internals of shared_ptr: std::shared_ptr<int> p(new int(1)); p = nullptr; // 'Potential leak of memory pointed to by field __cntrl_' This patch suppresses all diagnostics where the end of the path is inside a method in std::shared_ptr. It also reorganizes the tests for suppressions in the C++ standard library to use a separate simulated header for library functions with bugs that were deliberately inserted to test suppression. This will prevent other tests from using these as models. rdar://problem/23652766 llvm-svn: 274691
* Read the implicit addend of R_386_GOT32X.Rafael Espindola2016-07-062-0/+8
| | | | llvm-svn: 274690
* [CUDA] Add missing namespace qualification on CudaArch in Action.cpp.Justin Lebar2016-07-061-1/+1
| | | | | | Fix build breakage with MSVC. llvm-svn: 274689
* [llvm-cov] Add support for creating html reportsVedant Kumar2016-07-069-2/+615
| | | | | | | | Based on a patch by Harlan Haskins! Differential Revision: http://reviews.llvm.org/D18278 llvm-svn: 274688
* Recognize R_386_GOT32X.Rafael Espindola2016-07-062-0/+6
| | | | | | We don't relax it, but we at least recognize it. llvm-svn: 274687
* AArch64: Change modeling of zero cycle zeroing.Matthias Braun2016-07-064-26/+76
| | | | | | | | | | | | | | | | | On CPUs with the zero cycle zeroing feature enabled "movi v.2d" should be used to zero a vector register. This was previously done at instruction selection time, however the register coalescer sometimes widened multiple vregs to the Q width because of that leading to extra spills. This patch leaves the decision on how to zero a register to the AsmPrinter phase where it doesn't affect register allocation anymore. This patch also sets isAsCheapAsAMove=1 on FMOVS0, FMOVD0. This fixes http://llvm.org/PR27454, rdar://25866262 Differential Revision: http://reviews.llvm.org/D21826 llvm-svn: 274686
* AArch64: Replace a RegScavenger instance with LivePhysRegsMatthias Braun2016-07-063-16/+35
| | | | | | | | | | | | | | findScratchNonCalleeSaveRegister() just needs a simple liveness analysis, use LivePhysRegs for that as it is simpler and does not depend on the kill flags. This commit adds a convenience function available() to LivePhysRegs: This function returns true if the given register is not reserved and neither the register nor any of its aliases are alive. Differential Revision: http://reviews.llvm.org/D21865 llvm-svn: 274685
* [ELF] Introduce a flag to parse response files according to windows rules.Davide Italiano2016-07-063-5/+39
| | | | | | Differential Revision: http://reviews.llvm/org/D22015 llvm-svn: 274684
* Because of our lifetime rules w.r.t. ValueObjects and ClusterManagers, ↵Enrico Granata2016-07-0616-82/+199
| | | | | | | | | | | | | | | | synthetic children caching is a tricky area: - if a synthetic child comes from the same hierarchy as its parent object, then it can't be cached by SharedPointer inside the synthetic provider, or it will cause a reference loop; - but, if a synthetic child is made from whole cloth (e.g. from an expression, a memory region, ...), then it better be cached by SharedPointer, or it will be cleared out and cause an assert() to fail if used at a later point For most cases of self-rooted synthetic children, we have a flag we set "IsSyntheticChildrenGenerated", but we were not using it to track caching. So, what ended up happening is each provider would set up its own cache, and if it got it wrong, a hard to diagnose crash would ensue This patch fixes that by centralizing caching in ValueObjectSynthetic - if a provider returns a self-rooted child (as per the flag), then it gets cached centrally by the ValueObject itself This cache is used only for lifetime management and not later retrieval of child values - a different cache handles that (because we might have a mix of self-rooted and properly nested child values for the same parent, we can't trivially use this lifetime cache for retrieval) Fixes rdar://26480007 llvm-svn: 274683
* [CUDA] Rename member variables in CudaInstallationDetector.Justin Lebar2016-07-062-40/+39
| | | | | | | | | | | | | | Summary: Remove the "Cuda" prefix from these variables -- it's clear that they related to CUDA given their containing type. Reviewers: tra Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D21868 llvm-svn: 274682
* [CUDA] Add utility functions for dealing with CUDA versions / architectures.Justin Lebar2016-07-068-110/+292
| | | | | | | | | | | | | | | | | | Summary: Currently our handling of CUDA architectures is scattered all around clang. This patch centralizes it. A key advantage of this centralization is that you can now write a C++ switch on e.g. CudaArch and get a compile error if you don't handle one of the enum values. Reviewers: tra Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D21867 llvm-svn: 274681
* [CUDA] Add support for CUDA 8 and sm_60-62.Justin Lebar2016-07-063-29/+47
| | | | | | | | | | | | Summary: Also add sm_32, which was missing. Reviewers: tra Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D21778 llvm-svn: 274680
* [MemorySSA] Reinstate the legacy printer and verifier.Chad Rosier2016-07-0619-15/+58
| | | | | | Differential Revision: http://reviews.llvm.org/D22058 llvm-svn: 274679
* Add initial support for R_386_GOT32X.Rafael Espindola2016-07-068-11/+53
| | | | | | This adds it only for movl mov@GOT(%reg), %reg. llvm-svn: 274678
* [CodeGen, DebugInfo] Use hasLocalLinkage instead of hasInternalLinkageDavid Majnemer2016-07-061-3/+3
| | | | | | | | For the purpose of emitting debug info, entities with private linkage should be treated the same as internal linkage. While this doesn't change anything in practice, it makes the code a little less confusing. llvm-svn: 274677
* [CodeView] Emit an appropriate symbol kind for globalsDavid Majnemer2016-07-066-9/+32
| | | | | | | We emitted debug info for globals/functions as if they all had external linkage. Instead, emit local symbol records when appropriate. llvm-svn: 274676
* [CodeView] Unions are always sealedDavid Majnemer2016-07-062-2/+3
| | | | | | | It is impossible to inherit from a union. We are missing a way to represent this in IR for classes/structs... llvm-svn: 274675
* [NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.Justin Lebar2016-07-064-1/+28
| | | | | | | | | | Reviewers: tra Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D22068 llvm-svn: 274674
* [LIR] Fix mis-compilation with unwinding.Haicheng Wu2016-07-062-0/+41
| | | | | | | | To fix PR27859, bail out if there is an instruction may throw. Differential Revision: http://reviews.llvm.org/D20638 llvm-svn: 274673
* [esan|wset] Ensure SIGSEGV is not blockedDerek Bruening2016-07-068-6/+105
| | | | | | | | | | | | | | | | | | | | Summary: Adds interception of sigprocmask and pthread_sigmask to esan so that the working set tool can prevent SIGSEGV from being blocked. A blocked SIGSEGV results in crashes due to our lazy shadow page allocation scheme. Adds new sanitizer helper functions internal_sigemptyset and internal_sigismember. Adds a test to workingset-signal-posix.cpp. Reviewers: aizatsky Subscribers: vitalybuka, zhaoqin, kcc, eugenis, llvm-commits, kubabrecka Differential Revision: http://reviews.llvm.org/D22063 llvm-svn: 274672
* Fix cmake generation on Apple for interception unittestsEtienne Bergeron2016-07-061-2/+0
| | | | llvm-svn: 274671
* [InstCombine] use more specific pattern matchers; NFCISanjay Patel2016-07-061-12/+10
| | | | | | | | Follow-up from r274465: we don't need to capture the value in these cases, so just match the constant that we're looking for. m_One/m_Zero work with vector splats as well as scalars. llvm-svn: 274670
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