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* [WebAssembly] Narrow the scope of WebAssemblyFixFunctionBitcastsJacob Gravelle2017-10-102-38/+120
| | | | | | | | | | | | | | | | | Summary: The pass to fix function bitcasts generates thunks for functions that are called directly with a mismatching signature. It was also generating thunks in cases where the function was address-taken, causing aliasing problems in otherwise valid cases. This patch tightens the restrictions for when the pass runs. Reviewers: sunfish, dschuff Subscribers: jfb, sbc100, llvm-commits, aheejin Differential Revision: https://reviews.llvm.org/D38640 llvm-svn: 315326
* [clangd] Use UniqueFunction for deferred computations.Ilya Biryukov2017-10-103-23/+24
| | | | | | | Previsouly, `std::future` that were results of `std::async(std::launch::deferred, ...` were used. llvm-svn: 315325
* [clangd] Added missing #includes to Function.hIlya Biryukov2017-10-101-0/+3
| | | | llvm-svn: 315324
* [clangd] Added forgotten return in UniqueFunction.Ilya Biryukov2017-10-101-1/+1
| | | | | | | This hasn't bitten us because we only used functions returning 'void'. llvm-svn: 315323
* [X86][AVX512] Regenerate element insertion/extraction testsSimon Pilgrim2017-10-101-352/+171
| | | | llvm-svn: 315322
* [TableGen] Convert VarDef to range_loop. NFC.Javed Absar2017-10-101-2/+2
| | | | llvm-svn: 315321
* [sanitizer] Revert D38706Kostya Kortchinsky2017-10-103-31/+2
| | | | | | | | | | | | | | Summary: D38706 breaks tsan and the nolibc build. Reverting while working on a fix. Reviewers: alekseyshl Subscribers: kubamracek, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D38739 llvm-svn: 315320
* [sanitizer] Move the errno/ENOMEM allocator checks logic to separate .ccKostya Kortchinsky2017-10-103-2/+31
| | | | | | | | | | | | | | | | | | | | | | | Summary: The fact that `sanitizer_allocator_checks.h` is including `sanitizer_errno.h` creates complications for future changes, where it would conflict with `errno.h` definitions on Android and Fuchsia (macro redefinition). By moving the portion that sets errno in the checks to a separate compilation unit, we avoid the inclusion of the header there, which solves the issue. Not that it is not vital to have that function in a header as it is called as a result of an unlikely event, and doesn't need to be inlined. Reviewers: alekseyshl Reviewed By: alekseyshl Subscribers: kubamracek, llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D38706 llvm-svn: 315319
* [mips] Duplicate the reciprocal instruction definitions for FP32Simon Dardis2017-10-105-13/+37
| | | | | | | | | | | | | Add instruction definitions for FP32 mode for recip.d and rsqrt.d. Previously these instructions were only defined when targeting the full 64-bit FPU model but were not guarded properly. Reviewers: nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D38400 llvm-svn: 315318
* [clangd] clang-format the source code. NFC.Ilya Biryukov2017-10-103-7/+11
| | | | llvm-svn: 315317
* Re-land "[llvm-dwarfdump] Print type names in DW_AT_type DIEs"Jonas Devlieghere2017-10-1023-82/+142
| | | | | | | | | | | | This patch adds printing for DW_AT_type DIEs like it is already the case for DW_AT_specification DIEs. This is a rather naive approach and only a start. We should have pretty printers for different languages. Recommit after being reverted in r315299. Differential revision: https://reviews.llvm.org/D36993 llvm-svn: 315316
* [OPENMP] Add default codegen|tests for 'target parallel for[ simd]'Alexey Bataev2017-10-103-1/+472
| | | | | | | | | constructs. Added default codegen for 'target parallel for' construct + tests for default codegen of 'target parallel for[ simd]' constructs. llvm-svn: 315315
* Fix a (slightly weird) 'comma operator within array index expression' ↵Simon Pilgrim2017-10-101-1/+2
| | | | | | warning on VS builds. NFCI. llvm-svn: 315314
* [PowerPC] Add missing record form instructions to the P9 Scheduling ModelStefan Pintilie2017-10-102-1/+32
| | | | | | | | | A number of record form instructions were missing from the P9 scheduling model. Added those instructions and marked the P9 model as complete. Differential Revision: https://reviews.llvm.org/D38560 llvm-svn: 315313
* [x86] add tests for insertelement; NFCSanjay Patel2017-10-101-0/+1178
| | | | llvm-svn: 315312
* after fixing the i386 caseUriel Korach2017-10-101-2/+2
| | | | | Change-Id: If6fe0b6ec01f111115fb734fe31c0e152dbc165f llvm-svn: 315311
* [mips] Partially fix PR34391Simon Dardis2017-10-103-4/+84
| | | | | | | | | | | | | | | | | | | | | | | | Previously, the parsing of the 'subu $reg, ($reg,) imm' relied on a parser which also rendered the operand to the instruction. In some cases the general parser could construct an MCExpr which was not a MCConstantExpr which MipsAsmParser was expecting. Address this by altering the special handling to cope with unexpected inputs and fine-tune the handling of cases where an register name that is not available in the current ABI is regarded as not a match for the custom parser but also not as an outright error. Also enforces the binutils restriction that only constants are accepted. This partially resolves PR34391. Thanks to Ed Maste for reporting the issue! Reviewers: nitesh.jain, arichardson Differential Revision: https://reviews.llvm.org/D37476 llvm-svn: 315310
* Revert "[Modules TS] Module ownership semantics for redeclarations."Eric Liu2017-10-1020-353/+79
| | | | | | This reverts commit r315251. See the original commit thread for reason. llvm-svn: 315309
* Revert "[Modules TS] Avoid computing the linkage of the enclosing ↵Eric Liu2017-10-104-24/+4
| | | | | | | | DeclContext for a declaration in the global module." This reverts commit r315256. See the original commit thread for reason. llvm-svn: 315308
* [DAGCombine] Fix for shuffle to vector extend for non power 2 vectorsDavid Stuttard2017-10-102-0/+35
| | | | | | | | | | | | | | | | | | | | | Summary: See https://llvm.org/PR33743 for more details It seems that for non-power of 2 vector sizes, the algorithm can produce non-matching sizes for input and result causing an assert. This usually isn't a problem as the isAnyExtend check will weed these out, but in some cases (most often with lots of undefined values for the mask indices) it can pass this check for non power of 2 vectors. Adding in an extra check that ensures that bit size will match for the result and input (as required) Subscribers: nhaehnle Differential Revision: https://reviews.llvm.org/D35241 llvm-svn: 315307
* [XRay][compiler-rt] Fix rdtscp support check for x86_64Dean Michael Berris2017-10-101-2/+2
| | | | | | Follow-up to D29438. llvm-svn: 315306
* [ARM, Asm] Harden GNU LDRD/STRD aliases against invalid inputsOliver Stannard2017-10-106-28/+136
| | | | | | | | | | | | | | | | | | | Previously, the code that implemented the GNU assembler aliases for the LDRD and STRD instructions (where the second register is omitted) assumed that the input was a valid instruction. This caused assertion failures for every example in ldrd-strd-gnu-bad-inst.s. This improves this code so that it bails out if the instruction is not in the expected format, the check bails out, and the asm parser is run on the unmodified instruction. It also relaxes the alias on thumb targets, so that unaligned pairs of registers can be used. The restriction that Rt must be even-numbered only applies to the ARM versions of these instructions. Differential revision: https://reviews.llvm.org/D36732 llvm-svn: 315305
* [ARM, Asm] Add diagnostics for floating-point register operandsOliver Stannard2017-10-108-55/+106
| | | | | | | | | | | | | | | This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
* [ARM, Asm] Add diagnostics for general-purpose register operandsOliver Stannard2017-10-1016-86/+177
| | | | | | | | | | | | | | | This adds diagnostic strings for the ARM general-purpose register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, rGPR, requires C++ code to select the correct error message, as that class contains different registers in pre-v8 and v8 targets. The rest can all have their diagnostic strings stored in the tablegen description of them. Differential revision: https://reviews.llvm.org/D36692 llvm-svn: 315303
* AMDGPU: Split MUBUF offset into aligned componentsNicolai Haehnle2017-10-104-35/+41
| | | | | | | | | | | | | | | | | | | | Summary: Atomic buffer operations do not work (and trap on gfx9) when the components are unaligned, even if their sum is aligned. Previously, we generated an offset of 4156 without an SGPR by splitting it as 4095 + 61 (immediate + inline constant). The highest offset for which we can do this correctly is 4156 = 4092 + 64. Fixes dEQP-GLES31.functional.ssbo.atomic.* Reviewers: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D37850 llvm-svn: 315302
* [analyzer] MisusedMovedObject: Fix state-resetting a base-class sub-object.Artem Dergachev2017-10-102-1/+16
| | | | | | | | | | | If a method is resetting the state of an object that was moved from, it should be safe to use this object again. However if the method was defined in a parent class, but used in a child class, the reset didn't happen from the checker's perspective. Differential Revision: https://reviews.llvm.org/D31538 llvm-svn: 315301
* [analyzer] MisusedMovedObject: Add printState() method for self-debugging.Artem Dergachev2017-10-101-0/+21
| | | | | | | | | This method injects additional information into program state dumps, describing which objects have been moved from. Differential Revision: https://reviews.llvm.org/D31541 llvm-svn: 315300
* Revert "[llvm-dwarfdump] Print type names in DW_AT_type DIEs"Jonas Devlieghere2017-10-1022-138/+76
| | | | | | This reverts commit r315297. llvm-svn: 315299
* [analyzer] PthreadLockChecker: Add printState() method for self-debugging.Artem Dergachev2017-10-101-0/+35
| | | | | | | | | This method injects additional information into program state dumps, describing states of mutexes tracked by the checker. Differential Revision: https://reviews.llvm.org/D37805 llvm-svn: 315298
* [llvm-dwarfdump] Print type names in DW_AT_type DIEsJonas Devlieghere2017-10-1022-76/+138
| | | | | | | | | | This patch adds printing for DW_AT_type DIEs like it is already the case for DW_AT_specification DIEs. This is a rather naive approach and only a start. We should have pretty printers for different languages. Differential revision: https://reviews.llvm.org/D36993 llvm-svn: 315297
* [analyzer] Implement pointer arithmetic on constantsGabor Horvath2017-10-102-0/+36
| | | | | | | | Patch by: Rafael Stahl! Differential Revision: https://reviews.llvm.org/D37478 llvm-svn: 315296
* [AsmParser] Add DiagnosticString to register classes in tablegenOliver Stannard2017-10-104-23/+97
| | | | | | | | | | | | | | | | | | | | | | | | | This allows a DiagnosticType and/or DiagnosticString to be associated with a RegisterClass in tablegen, so that we can emit diagnostics in the assembler when a register operand is incorrect. DiagnosticType creates a predictable enum value, which gets returned as the error code when an operand does not match, and can be used by the assembly parser to map to a user-facing diagnostic. DiagnosticString creates an anonymous enum value (currently based on the tablegen class name), and a function to map from enum values to strings will be generated. Both of these work the same was as they do for AsmOperand. This isn't used by any targets yet, but has one (positive) side-effect. It improves the diagnostic codes returned by validateOperandClass - we always want to emit the diagnostic that relates to the expected operand class, but this wasn't always being done when the expected and actual classes were completely different (token/register/custom). This causes a few AArch64 diagnostics to be improved, as Match_InvalidOperand was being returned instead of a specific diagnostic type. Differential revision: https://reviews.llvm.org/D36691 llvm-svn: 315295
* [SCCP] Fix mem-sanitizer failure introduced by r315288.Florian Hahn2017-10-101-2/+4
| | | | llvm-svn: 315294
* [ELF] Set Dot initially to --image-base value when using linker scriptsJames Henderson2017-10-107-16/+44
| | | | | | | | | | | | | | | | | | | | | When parsing linker scripts, LLD previously started with a '.' value of 0, regardless of the internal default image base for the target, and regardless of switches such as --image-base. It seems reasonable to use a different image base value when using linker scripts and --image-base is specified, since otherwise the switch has no effect. This change does this, as well as removing unnecessary initialisation of Dot where it is not used. The default image base should not be used when processing linker scripts, because this will change the behaviour for existing linker script users, and potentially result in invalid output being produced, as a subsequent assignment to Dot could move the location counter backwards. Instead, we maintain the existing behaviour of starting from 0 if --image-base is not specified. Reviewers: ruiu Differential Revision: https://reviews.llvm.org/D38360 llvm-svn: 315293
* [LLD] Fix findOrphanPos to consistently ignore "dead" OutputSection'sAndrew Ng2017-10-102-3/+39
| | | | | | | | | | | | | | When findOrphanPos does the reverse search to find the OutputSection preceding the orphan's insertion point, look for a live OutputSection and ignore "dead" OutputSection's. This matches the behaviour of the forward search performed earlier in this function. Added test which without the above fix fails as a result of an orphan executable section being incorrectly placed in a non-executable segment. Differential Review: https://reviews.llvm.org/D38690 llvm-svn: 315292
* [X86][SKYLAKE] Update regression test to differentiate between HASWELL and ↵Gadi Haber2017-10-106-6/+314
| | | | | | | | | | | | | | | SKYLAKE scheduling.<NFC> NFC. Updated 6 regression tests to differentiate between HASWELL and SKYLAKE scheduling information. The fix is in preparation of a patch to update the information of the Skylake Client scheduling to include the appropriate load and store latencies. Reviewers: zvi, RKSimon Differential Revision: https://reviews.llvm.org/D38685 Change-Id: Ifc6b98d9eaf266913698f24c766fd994fc977555 llvm-svn: 315291
* [clang-refactor] Fix clang-tidy misc-move-const-arg warning.Haojian Wu2017-10-101-2/+2
| | | | | | NFC llvm-svn: 315290
* [CodeGen] Do not construct complete LValue base info in trivial casesIvan A. Kosarev2017-10-106-71/+74
| | | | | | | | | | | | | Besides obvious code simplification, avoiding explicit creation of LValueBaseInfo objects makes it easier to make TBAA information to be part of such objects. This is part of D38126 reworked to be a separate patch to simplify review. Differential Revision: https://reviews.llvm.org/D38695 llvm-svn: 315289
* [SCCP] Propagate integer range info for parameters in IPSCCP.Florian Hahn2017-10-102-8/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This updates the SCCP solver to use of the ValueElement lattice for parameters, which provides integer range information. The range information is used to remove unneeded icmp instructions. For the following function, f() can be optimized to `ret i32 2` with this change source_filename = "sccp.c" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" ; Function Attrs: norecurse nounwind readnone uwtable define i32 @main() local_unnamed_addr #0 { entry: %call = tail call fastcc i32 @f(i32 1) %call1 = tail call fastcc i32 @f(i32 47) %add3 = add nsw i32 %call, %call1 ret i32 %add3 } ; Function Attrs: noinline norecurse nounwind readnone uwtable define internal fastcc i32 @f(i32 %x) unnamed_addr #1 { entry: %c1 = icmp sle i32 %x, 100 %cmp = icmp sgt i32 %x, 300 %. = select i1 %cmp, i32 1, i32 2 ret i32 %. } attributes #1 = { noinline } Reviewers: davide, sanjoy, efriedma, dberlin Reviewed By: davide, dberlin Subscribers: mcrosier, gberry, mssimpso, dberlin, llvm-commits Differential Revision: https://reviews.llvm.org/D36656 llvm-svn: 315288
* Revert "Revert r315214 since diff -Z isn't portable, this is breaking:"Ilya Biryukov2017-10-104-14/+208
| | | | | | | | | This reverts commit r315242 and restores r315214. To fix original failure, replaced non-portable `diff -Z` with portable alternative: `diff -b`. llvm-svn: 315287
* Fix small nits in clang-refactor doc.Haojian Wu2017-10-101-2/+2
| | | | llvm-svn: 315286
* Fix for PR34888.Nemanja Ivanovic2017-10-102-3/+125
| | | | | | | | | | The issue is that we assume operand zero of the input to the add instruction is a register. In this case, the input comes from inline assembly and operand zero is not a register thereby causing a crash. The code will bail anyway if the input instruction doesn't have the right opcode. So do that check first and let short-circuiting prevent the crash. llvm-svn: 315285
* [clangd] Fix compilation on gcc.Ilya Biryukov2017-10-101-2/+2
| | | | llvm-svn: 315284
* SILoadStoreOptimizer.cpp: Fix build; Clang doesn't like "using anonymous ↵NAKAMURA Takumi2017-10-101-1/+1
| | | | | | struct" since rL315256. llvm-svn: 315283
* MCWinCOFFObjectWriter.h: Fix modules build in rL315257.NAKAMURA Takumi2017-10-101-0/+2
| | | | llvm-svn: 315282
* Re-land "[MergeICmps] Disable mergeicmps if the target does not want to ↵Clement Courbet2017-10-107-97/+251
| | | | | | | | | | handle memcmp expansion." (fixed stability issues) This reverts commit d6492333d3b478a1d88163315002022f8d5e58dc. llvm-svn: 315281
* [ELF] - Improve "has non-ABS reloc" error.George Rimar2017-10-102-2/+3
| | | | | | | | It did not contain information about relocation type and symbol. Differential revision: https://reviews.llvm.org/D38623 llvm-svn: 315280
* Ignore all duplicate frame index expressionBjorn Steinbrink2017-10-102-24/+26
| | | | | | | | | | | | | | | | | Some passes might duplicate calls to llvm.dbg.declare creating duplicate frame index expression which currently trigger an assertion which is meant to catch erroneous, overlapping fragment declarations. But identical frame index expressions are just redundant and don't actually conflict with each other, so we can be more lenient and just ignore the duplicates. Reviewers: aprantl, rnk Subscribers: llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D38540 llvm-svn: 315279
* Remove unneeded typename from testRoger Ferrer Ibanez2017-10-102-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D38628 llvm-svn: 315278
* [clang-tidy] Use a more efficient map for the virtual near miss check.Benjamin Kramer2017-10-101-3/+3
| | | | | | DenseMap performs better here. No functionality change intended. llvm-svn: 315277
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