diff options
| author | Uriel Korach <uriel.korach@intel.com> | 2017-10-10 13:43:09 +0000 |
|---|---|---|
| committer | Uriel Korach <uriel.korach@intel.com> | 2017-10-10 13:43:09 +0000 |
| commit | 059e211aa12742ea367f84e37409f1ccf08d0576 (patch) | |
| tree | b1b456a6f03dc029a46735881ea84de72531b61c | |
| parent | a17a7b619ab336e72c16ced3372a4cbc67709351 (diff) | |
| download | bcm5719-llvm-059e211aa12742ea367f84e37409f1ccf08d0576.tar.gz bcm5719-llvm-059e211aa12742ea367f84e37409f1ccf08d0576.zip | |
after fixing the i386 case
Change-Id: If6fe0b6ec01f111115fb734fe31c0e152dbc165f
llvm-svn: 315311
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 0f6a27ed9e7..d35c188e310 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -8028,8 +8028,8 @@ static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op, // output register, mark it as legal and catch the pattern in instruction // selection to avoid emitting extra insturctions (for zeroing upper bits). if (SDValue Promoted = isTypePromotionOfi1ZeroUpBits(Op)) { - SDValue ZeroC = DAG.getConstant(0, dl, MVT::i64); - SDValue AllZeros = DAG.getSplatBuildVector(ResVT, dl, ZeroC); + SDValue ZeroC = DAG.getIntPtrConstant(0, dl); + SDValue AllZeros = getZeroVector(ResVT, Subtarget, DAG, dl); return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, AllZeros, Promoted, ZeroC); } |
