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* [Alignment] Introduce llvm::Align to MCSectionGuillaume Chatelet2019-09-1310-24/+28
| | | | | | | | | | | | | | | | | Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet, JDevlieghere Subscribers: arsenm, sdardis, jvesely, nhaehnle, sbc100, hiraditya, aheejin, jrtc27, atanasyan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67486 llvm-svn: 371831
* [lib/ObjectYAML] - Change interface to return `bool` instead of `int`. NFCIGeorge Rimar2019-09-137-36/+34
| | | | | | | | It was suggested in comments for D67445 to split this part. Differential revision: https://reviews.llvm.org/D67488 llvm-svn: 371828
* [ARM] Add support for MVE vmaxv and vminvSam Tebbs2019-09-135-2/+174
| | | | | | | | This patch adds vecreduce_smax, vecredude_umax, vecreduce_smin, vecreduce_umin and selection for vmaxv and minv. Differential Revision: https://reviews.llvm.org/D66413 llvm-svn: 371827
* [llvm-objdump] Fix llvm-objdump --all-headers output orderGeorge Rimar2019-09-132-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Justice Adams! Made llvm-objdump --all-headers output match the order of GNU objdump for compatibility reasons. Old order of the headers output: * file header * section header table * symbol table * program header table * dynamic section New order of the headers output (GNU compatible): * file header information * program header table * dynamic section * section header table * symbol table (Relevant BugZilla Bug: https://bugs.llvm.org/show_bug.cgi?id=41830) Differential revision: https://reviews.llvm.org/D67357 llvm-svn: 371826
* [Polly] Fix lib/Transform/ScheduleOptimizer.cpp compilation on SolarisRainer Orth2019-09-131-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | lib/Transform/ScheduleOptimizer.cpp fails to compile on Solaris, both on the 9.x branch (first noticed when running test-release.sh without -no-polly) and on trunk: /var/llvm/llvm-9.0.0-rc4/rc4/llvm.src/tools/polly/lib/Transform/ScheduleOptimizer.cpp: In function ‘MicroKernelParamsTy getMicroKernelParams(const llvm::TargetTransformInfo*, polly::MatMulInfoTy)’: /var/llvm/llvm-9.0.0-rc4/rc4/llvm.src/tools/polly/lib/Transform/ScheduleOptimizer.cpp:914:62: error: call of overloaded ‘sqrt(long unsigned int)’ is ambiguous 914 | ceil(sqrt(Nvec * LatencyVectorFma * ThroughputVectorFma) / Nvec) * Nvec; | ^ In file included from /usr/gcc/9/lib/gcc/x86_64-pc-solaris2.11/9.1.0/include-fixed/math.h:24, from /usr/gcc/9/include/c++/9.1.0/cmath:45, from /var/llvm/llvm-9.0.0-rc4/rc4/llvm.src/include/llvm-c/DataTypes.h:28, from /var/llvm/llvm-9.0.0-rc4/rc4/llvm.src/include/llvm/Support/DataTypes.h:16, from /var/llvm/llvm-9.0.0-rc4/rc4/llvm.src/include/llvm/ADT/Hashing.h:47, from /var/llvm/llvm-9.0.0-rc4/rc4/llvm.src/include/llvm/ADT/ArrayRef.h:12, from /var/llvm/llvm-9.0.0-rc4/rc4/llvm.src/tools/polly/include/polly/ScheduleOptimizer.h:12, from /var/llvm/llvm-9.0.0-rc4/rc4/llvm.src/tools/polly/lib/Transform/ScheduleOptimizer.cpp:48: /usr/gcc/9/lib/gcc/x86_64-pc-solaris2.11/9.1.0/include-fixed/iso/math_iso.h:220:21: note: candidate: ‘long double std::sqrt(long double)’ 220 | inline long double sqrt(long double __X) { return __sqrtl(__X); } | ^~~~ /usr/gcc/9/lib/gcc/x86_64-pc-solaris2.11/9.1.0/include-fixed/iso/math_iso.h:186:15: note: candidate: ‘float std::sqrt(float)’ 186 | inline float sqrt(float __X) { return __sqrtf(__X); } | ^~~~ /usr/gcc/9/lib/gcc/x86_64-pc-solaris2.11/9.1.0/include-fixed/iso/math_iso.h:74:15: note: candidate: ‘double std::sqrt(double)’ 74 | extern double sqrt __P((double)); | ^~~~ /var/llvm/llvm-9.0.0-rc4/rc4/llvm.src/tools/polly/lib/Transform/ScheduleOptimizer.cpp:915:67: error: call of overloaded ‘ceil(long unsigned int)’ is ambiguous 915 | int Mr = ceil(Nvec * LatencyVectorFma * ThroughputVectorFma / Nr); | ^ In file included from /usr/gcc/9/lib/gcc/x86_64-pc-solaris2.11/9.1.0/include-fixed/math.h:24, from /usr/gcc/9/include/c++/9.1.0/cmath:45, from /var/llvm/llvm-9.0.0-rc4/rc4/llvm.src/include/llvm-c/DataTypes.h:28, from /var/llvm/llvm-9.0.0-rc4/rc4/llvm.src/include/llvm/Support/DataTypes.h:16, from /var/llvm/llvm-9.0.0-rc4/rc4/llvm.src/include/llvm/ADT/Hashing.h:47, from /var/llvm/llvm-9.0.0-rc4/rc4/llvm.src/include/llvm/ADT/ArrayRef.h:12, from /var/llvm/llvm-9.0.0-rc4/rc4/llvm.src/tools/polly/include/polly/ScheduleOptimizer.h:12, from /var/llvm/llvm-9.0.0-rc4/rc4/llvm.src/tools/polly/lib/Transform/ScheduleOptimizer.cpp:48: /usr/gcc/9/lib/gcc/x86_64-pc-solaris2.11/9.1.0/include-fixed/iso/math_iso.h:196:21: note: candidate: ‘long double std::ceil(long double)’ 196 | inline long double ceil(long double __X) { return __ceill(__X); } | ^~~~ /usr/gcc/9/lib/gcc/x86_64-pc-solaris2.11/9.1.0/include-fixed/iso/math_iso.h:160:15: note: candidate: ‘float std::ceil(float)’ 160 | inline float ceil(float __X) { return __ceilf(__X); } | ^~~~ /usr/gcc/9/lib/gcc/x86_64-pc-solaris2.11/9.1.0/include-fixed/iso/math_iso.h:76:15: note: candidate: ‘double std::ceil(double)’ 76 | extern double ceil __P((double)); | ^~~~ Fixed by adding casts to disambiguate, checked that it now compiles on both amd64-pc-solaris2.11 and sparcv9-sun-solaris2.11 and on x86_64-pc-linux-gnu. Differential Revision: https://reviews.llvm.org/D67442 llvm-svn: 371825
* Revert "Fix test failures after r371640"Dmitri Gribenko2019-09-132-6/+7
| | | | | | This reverts commit r371645, because r371640 was reverted. llvm-svn: 371824
* [lldb][NFC] Make ArgEntry::quote private and provide a getterRaphael Isemann2019-09-134-4/+5
| | | | llvm-svn: 371823
* [compiler-rt] Add ubsan interface header.Pierre Gousseau2019-09-132-0/+33
| | | | | | | | | | This is to document __ubsan_default_options(). Reviewed By: vitalybuka Differential Revision: https://reviews.llvm.org/D67503 llvm-svn: 371822
* [Clang][ASTImporter] Added visibility check for FunctionTemplateDecl.Balazs Keri2019-09-132-11/+54
| | | | | | | | | | | | | | | | | | Summary: ASTImporter makes now difference between function templates with same name in different translation units if these are not visible outside. Reviewers: martong, a.sidorin, shafik, a_sidorin Reviewed By: a_sidorin Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D67490 llvm-svn: 371820
* [BasicBlockUtils] Add optional BBName argument, in line with BB:splitBasicBlockFlorian Hahn2019-09-133-5/+8
| | | | | | | | | | Reviewers: spatel, asbirlea, craig.topper Reviewed By: asbirlea Differential Revision: https://reviews.llvm.org/D67521 llvm-svn: 371819
* [AArch64] MachineCombiner FMA matching. NFC.Sjoerd Meijer2019-09-131-325/+112
| | | | | | | | | Follow-up of rL371321 that added some more FP16 FMA patterns, and an attempt to reduce the copy-pasting and make this more readable. Differential Revision: https://reviews.llvm.org/D67403 llvm-svn: 371818
* For PR17164: split -fno-lax-vector-conversion into three differentRichard Smith2019-09-1332-64/+146
| | | | | | | | | | | | | | | | | | | | | levels: -- none: no lax vector conversions [new GCC default] -- integer: only conversions between integer vectors [old GCC default] -- all: all conversions between same-size vectors [Clang default] For now, Clang still defaults to "all" mode, but per my proposal on cfe-dev (2019-04-10) the default will be changed to "integer" as soon as that doesn't break lots of testcases. (Eventually I'd like to change the default to "none" to match GCC and general sanity.) Following GCC's behavior, the driver flag -flax-vector-conversions is translated to -flax-vector-conversions=integer. This reinstates r371805, reverted in r371813, with an additional fix for lldb. llvm-svn: 371817
* Fix interaction between r371813 and r371814.Richard Smith2019-09-131-3/+3
| | | | llvm-svn: 371816
* [TargetRegisterInfo] Remove SVT argument from getCommonSubClass.Craig Topper2019-09-133-19/+7
| | | | | | | | This was added to support fp128 on x86-64, but appears to be unneeded now. This may be because the FR128 register class added back then was merged with the VR128 register class later. llvm-svn: 371815
* Remove reliance on lax vector conversions from altivec.h and its test.Richard Smith2019-09-133-32/+38
| | | | llvm-svn: 371814
* Revert "For PR17164: split -fno-lax-vector-conversion into three different"Jonas Devlieghere2019-09-1330-142/+60
| | | | | | | This breaks the LLDB build. I tried reaching out to Richard, but haven't gotten a reply yet. llvm-svn: 371813
* AMDGPU/GlobalISel: Fix assert on multi-return side effect intrinsicsMatt Arsenault2019-09-131-1/+1
| | | | | | llvm.amdgcn.else hits this. llvm-svn: 371812
* AMDGPU/GlobalISel: Legalize s32->s16 G_SITOFP/G_UITOFPMatt Arsenault2019-09-133-1/+35
| | | | llvm-svn: 371811
* [RISCV] Support stack offset exceed 32-bit for RV64Shiva Chen2019-09-136-60/+104
| | | | | | Differential Revision: https://reviews.llvm.org/D61884 llvm-svn: 371810
* Revert "[RISCV] Support stack offset exceed 32-bit for RV64"Shiva Chen2019-09-136-103/+60
| | | | | | This reverts commit 1c340c62058d4115d21e5fa1ce3a0d094d28c792. llvm-svn: 371809
* AMDGPU/GlobalISel: Fix RegBankSelect for amdgcn.elseMatt Arsenault2019-09-133-0/+42
| | | | llvm-svn: 371808
* AMDGPU/GlobalISel: Select 16-bit VALU bit opsMatt Arsenault2019-09-134-21/+18
| | | | llvm-svn: 371807
* [RISCV] Support stack offset exceed 32-bit for RV64Shiva Chen2019-09-136-60/+103
| | | | | | Differential Revision: https://reviews.llvm.org/D61884 llvm-svn: 371806
* For PR17164: split -fno-lax-vector-conversion into three differentRichard Smith2019-09-1330-60/+142
| | | | | | | | | | | | | | | | | | levels: -- none: no lax vector conversions [new GCC default] -- integer: only conversions between integer vectors [old GCC default] -- all: all conversions between same-size vectors [Clang default] For now, Clang still defaults to "all" mode, but per my proposal on cfe-dev (2019-04-10) the default will be changed to "integer" as soon as that doesn't break lots of testcases. (Eventually I'd like to change the default to "none" to match GCC and general sanity.) Following GCC's behavior, the driver flag -flax-vector-conversions is translated to -flax-vector-conversions=integer. llvm-svn: 371805
* [ELF] Delete a redundant assignment to SectionBase::assigned. NFCFangrui Song2019-09-131-1/+0
| | | | | | | LinkerScript::discard marks a section dead. It is unnecessary to set the `assigned` bit. llvm-svn: 371804
* AMDGPU/GlobalISel: Legalize G_FFLOORMatt Arsenault2019-09-135-2/+642
| | | | llvm-svn: 371803
* Temporarily revert r371640 "LiveIntervals: Split live intervals on multiple ↵Tim Shen2019-09-132-29/+1
| | | | | | | | dead defs". It reveals a miscompile on Hexagon. See PR43302 for details. llvm-svn: 371802
* [ScopBuilder] Skip getting leader when merging statements to close holes.Michael Kruse2019-09-132-4/+90
| | | | | | | | | | | | | | | | | | | | | | | | | Function joinOrderedInstructions merges instructions when a leader is encountered twice. It also notices that leaders in SeenLeaders may lose their leadership in previous merging, and tries to handle the case using following code: Instruction *PrevLeader = UnionFind.getLeaderValue(SeenLeaders.back()); However, this is wrong because it always gets leader for the last element of SeenLeaders, and I believe it's wrong even we get leader for Prev here. As a result, Statements in cases like the one in patch aren't merged as expected. After investigation, I believe it's unnecessary to get leader instruction at all. This is based on fact: Although leaders in SeenLeaders could lose leadership, they only lose to others in SeenLeaders, in other words, one existing leader will be chosen as new leader of merged equivalent statements. We can take advantage of this and simply check if current leader equals to Prev and break merging if it does. The patch also adds a new test. Patch by bin.narwal <bin.narwal@gmail.com> Differential Revision: https://reviews.llvm.org/D67007 llvm-svn: 371801
* AMDGPU/GlobalISel: Legalize G_FMADMatt Arsenault2019-09-138-2/+872
| | | | | | | | | | | | | | | Unlike SelectionDAG, treat this as a normally legalizable operation. In SelectionDAG this is supposed to only ever formed if it's legal, but I've found that to be restricting. For AMDGPU this is contextually legal depending on whether denormal flushing is allowed in the use function. Technically we currently treat the denormal mode as a subtarget feature, so custom lowering could be avoided. However I consider this to be a defect, and this should be contextually dependent on the controllable rounding mode of the parent function. llvm-svn: 371800
* Revert r371785.Manoj Gupta2019-09-138-39/+0
| | | | | | r371785 is causing fails on clang-hexagon-elf buildbots. llvm-svn: 371799
* AMDGPU/GlobalISel: Select G_CTPOPMatt Arsenault2019-09-135-2/+219
| | | | llvm-svn: 371798
* DAG/GlobalISel: Correct type profile of bitcount opsMatt Arsenault2019-09-138-27/+30
| | | | | | | | The result integer does not need to be the same width as the input. AMDGPU, NVPTX, and Hexagon all have patterns working around the types matching. GlobalISel defines these as being different type indexes. llvm-svn: 371797
* [Target] Move InferiorCall to ProcessAlex Langford2019-09-134-66/+62
| | | | | | | | | | | | | | | | | | | Summary: InferiorCall is only ever used in Process, and it is not specific to POSIX. By moving it to Process, we can remove all dependencies on plugins from Process. Moving InferiorCall to Process seems to achieve this quite well. Additionally, the name InferiorCall is a little vague now, so we rename it something a bit more specific. Reviewers: JDevlieghere, clayborg, compnerd, labath Subscribers: lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D67472 llvm-svn: 371796
* The setUp/tearDown methods I added mssed up the test function; reorder.Jason Molenda2019-09-131-6/+7
| | | | | | Thanks to Ted Woodward for catching this one. llvm-svn: 371795
* [libclang] Fix UninstallAbortingLLVMFatalErrorHandler testJan Korous2019-09-121-2/+3
| | | | llvm-svn: 371794
* AMDGPU: Add immarg to llvm.amdgcn.init.exec.from.inputMatt Arsenault2019-09-121-1/+1
| | | | | | As far as I can tell this has to be a constant. llvm-svn: 371793
* LiveIntervals: Remove assertionMatt Arsenault2019-09-122-1/+30
| | | | | | | | | | | | | This testcase is invalid, and caught by the verifier. For the verifier to catch it, the live interval computation needs to complete. Remove the assert so the verifier catches this, which is less confusing. In this testcase there is an undefined use of a subregister, and lanes which aren't used or defined. An equivalent testcase with the super-register shrunk to have no untouched lanes already hit this verifier error. llvm-svn: 371792
* AMDGPU: Inline constant when materalizing FI with add on gfx9Matt Arsenault2019-09-124-7/+53
| | | | | | | | | This was relying on the SGPR usable for the carry out clobber to also be used for the input. There was no carry out on gfx9. With no carry out clobber to worry about, so the literal can just be directly used with a VOP2 add. llvm-svn: 371791
* [Test] Restructure check lines to show differences between modes more clearlyPhilip Reames2019-09-121-960/+494
| | | | | | | | With the landing of the previous patch (in particular D66318) there are a lot fewer diffs now. I added an experimental O0 line, and updated all the tests to group experimental and non-experimental O0/O3 together. Skimming the remaining diffs, there's only a few which are obviously incorrect. There's a large number which are questionable, so more todo. llvm-svn: 371790
* Rename nonvolatile_load/store to simple_load/store [NFC]Philip Reames2019-09-127-38/+37
| | | | | | Implement the TODO from D66318. llvm-svn: 371789
* [AArch64][GlobalISel] Support tail calling with swiftself parametersJessica Paquette2019-09-122-5/+53
| | | | | | | | | | | | | | | | Swiftself uses a callee-saved register. We can tail call when the register used in the caller and callee is the same. This behaviour is equivalent to that in `TargetLowering::parametersInCSRMatch`. Update call-translator-tail-call.ll to verify that we can do this. When we support inline assembly, we can write a check similar to the one in the general swiftself.ll. For now, we need to verify that we get the correct COPY instruction after call lowering. Differential Revision: https://reviews.llvm.org/D67511 llvm-svn: 371788
* [libclang] Expose abort()-ing LLVM fatal error handlerJan Korous2019-09-128-9/+113
| | | | | | Differential Revision: https://reviews.llvm.org/D66775 llvm-svn: 371787
* [SDAG] Update generic code to conservatively check for isAtomic in addition ↵Philip Reames2019-09-126-111/+122
| | | | | | | | | | to isVolatile This is the first sweep of generic code to add isAtomic bailouts where appropriate. The intention here is to have the switch from AtomicSDNode to LoadSDNode/StoreSDNode be close to NFC; that is, I'm not looking to allow additional optimizations at this time. That will come later. See D66309 for context. Differential Revision: https://reviews.llvm.org/D66318 llvm-svn: 371786
* Add -Wpoison-system-directories warningManoj Gupta2019-09-128-0/+39
| | | | | | | | | | | | | | | | | | When using clang as a cross-compiler, we should not use system headers to do the compilation. This CL adds support of a new warning flag -Wpoison-system-directories which emits warnings if --sysroot is set and headers from common host system location are used. By default the warning is disabled. The intention of the warning is to catch bad includes which are usually generated by third party build system not targeting cross-compilation. Such cases happen in Chrome OS when someone imports a new package or upgrade one to a newer version from upstream. Patch by: denik (Denis Nikitin) llvm-svn: 371785
* [NFC] Sort source files in Utility/CMakeLists.txtJonas Devlieghere2019-09-121-3/+3
| | | | llvm-svn: 371784
* [NFC] Fix file header filename to be Range.hGreg Clayton2019-09-121-1/+1
| | | | llvm-svn: 371783
* [Docs] Adds page for reference docsDeForest Richards2019-09-123-9/+33
| | | | | | Adds a Reference Documentation page for LLVM and API reference documentation. llvm-svn: 371782
* [analyzer] Fix the 'analyzer-enabled-checkers.c' test on non-linux machines.Artem Dergachev2019-09-121-2/+1
| | | | | | | | '-Xclang -triple' doesn't seem to override the default target triple as reliably as '--target'. This leads to test failing due to platform-specific checks getting unexpectedly enabled. llvm-svn: 371781
* [AArch64][GlobalISel] Support sibling calls with outgoing argumentsJessica Paquette2019-09-129-77/+183
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for lowering sibling calls with outgoing arguments. e.g ``` define void @foo(i32 %a) ``` Support is ported from AArch64ISelLowering's `isEligibleForTailCallOptimization`. The only thing that is missing is a full port of `TargetLowering::parametersInCSRMatch`. So, if we're using swiftself, we'll never tail call. - Rename `analyzeCallResult` to `analyzeArgInfo`, since the function is now used for both outgoing and incoming arguments - Teach `OutgoingArgHandler` about tail calls. Tail calls use frame indices for stack arguments. - Teach `lowerFormalArguments` to set the bytes in the caller's stack argument area. This is used later to check if the tail call's parameters will fit on the caller's stack. - Add `areCalleeOutgoingArgsTailCallable` to perform the eligibility check on the callee's outgoing arguments. For testing: - Update call-translator-tail-call to verify that we can now tail call with outgoing arguments, use G_FRAME_INDEX for stack arguments, and respect the size of the caller's stack - Remove GISel-specific check lines from speculation-hardening.ll, since GISel now tail calls like the other selectors - Add a GISel test line to tailcall-string-rvo.ll since we can tail call in that test now - Add a GISel test line to tailcall_misched_graph.ll since we tail call there now. Add specific check lines for GISel, since the debug output from the machine-scheduler differs with GlobalISel. The dependency still holds, but the output comes out in a different order. Differential Revision: https://reviews.llvm.org/D67471 llvm-svn: 371780
* [PowerPC] Remove the SPE4RC register class and instead add f32 to the GPRC ↵Craig Topper2019-09-1210-63/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register class. Summary: Since the SPE4RC register class contains an identical set of registers and an identical spill size to the GPRC class its slightly confusing the tablegen emitter. It's preventing the GPRC_and_GPRC_NOR0 synthesized register class from inheriting VTs and AltOrders from GPRC or GPRC_NOR0. This is because SPE4C is found first in the super register class list when inheriting these properties and it doesn't set the VTs or AltOrders the same way as GPRC or GPRC_NOR0. This patch replaces all uses of GPE4RC with GPRC and allows GPRC and GPRC_NOR0 to contain f32. The test changes here are because the AltOrders are being inherited to GPRC_NOR0 now. Found while trying to determine if getCommonSubClass needs to take a VT argument. It was originally added to support fp128 on x86-64, I've changed some things about that so that it might be needed anymore. But a PowerPC test crashed without it and I think its due to this subclass issue. Reviewers: jhibbits, nemanjai, kbarton, hfinkel Subscribers: wuzish, nemanjai, mehdi_amini, hiraditya, kbarton, MaskRay, dexonsmith, jsji, shchenz, steven.zhang, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67513 llvm-svn: 371779
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