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* [docs][statepoint] Expand a bit on problems with mixing references and raw ↵Philip Reames2018-11-091-1/+9
| | | | | | pointers since it keeps coming up in discussions llvm-svn: 346513
* [Power9] Allow gpr callee saved spills in prologue to vectors registersZaara Syeda2018-11-096-41/+250
| | | | | | | | | | | | | | Currently in llvm, CalleeSavedInfo can only assign a callee saved register to stack frame index to be spilled in the prologue. We would like to enable spilling gprs to vector registers. This patch adds the capability to spill to other registers aside from just the stack. It also adds the changes for power9 to spill gprs to volatile vector registers when they are available. This happens only for leaf functions when using the option -ppc-enable-pe-vector-spills. Differential Revision: https://reviews.llvm.org/D39386 llvm-svn: 346512
* [NativePDB] Add support for bitfield records.Zachary Turner2018-11-093-4/+86
| | | | | | | | | Bitfields are represented as LF_MEMBER records whose TypeIndex points to an LF_BITFIELD record that describes the bit width, bit offset, and underlying type of the bitfield. All we need to do is resolve these when resolving record types. llvm-svn: 346511
* [CostModel] Add SK_ExtractSubvector handling to getInstructionThroughput ↵Simon Pilgrim2018-11-094-38/+92
| | | | | | | | (PR39368) Add ShuffleVectorInst::isExtractSubvectorMask helper to match shuffle masks. llvm-svn: 346510
* [docs][statepoint] tweak a titlePhilip Reames2018-11-091-2/+2
| | | | llvm-svn: 346509
* Revert "[DEBUGINFO, NVPTX]DO not emit ',debug' option if no debug info or ↵Alexey Bataev2018-11-094-78/+4
| | | | | | | | | only debug directives are requested." This reverts commit r345972. Need to update the description + possibly to update the patch itself after discussion with Eric Christofer. llvm-svn: 346508
* [OPENMP][NVPTX]Allow to use shared memory for theAlexey Bataev2018-11-099-98/+143
| | | | | | | | | | target|teams|distribute variables. If the total size of the variables, declared in target|teams|distribute regions, is less than the maximal size of shared memory available, the buffer is allocated in the shared memory. llvm-svn: 346507
* [llvm-cov] Add lcov tracefile export format.Max Moroz2018-11-099-13/+270
| | | | | | | | | | | | | | | | | | | | | | | | Summary: lcov tracefiles are used by various coverage reporting tools and build systems (e.g., Bazel). It is a simple text-based format to parse and more convenient to use than the JSON export format, which needs additional processing to map regions/segments back to line numbers. It's a little unfortunate that "text" format is now overloaded to refer specifically to JSON for export, but I wanted to avoid making any breaking changes to the UI of the llvm-cov tool at this time. Patch by Tony Allevato (@allevato). Reviewers: Dor1s, vsk Reviewed By: Dor1s, vsk Subscribers: mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D54266 llvm-svn: 346506
* Resubmit "Fix bug in PE/COFF plugin."Zachary Turner2018-11-094-7/+49
| | | | | | | | | | The original commit was actually 2 unrelated bug fixes, but it turns out the second bug fix wasn't quite correct, so the entire patch was reverted. Resubmitting this half of the patch by itself, then will follow up with a new patch which fixes the rest of the issue in a more appropriate way. llvm-svn: 346505
* [SystemZ] Avoid inserting same value after replicationJonas Paulsson2018-11-092-1/+23
| | | | | | | | | | | A minor improvement of buildVector() that skips creating an INSERT_VECTOR_ELT for a Value which has already been used for the REPLICATE. Review: Ulrich Weigand https://reviews.llvm.org/D54315 llvm-svn: 346504
* [clangd] Don't treat top-level decls as "local" if they are from the preamble.Sam McCall2018-11-092-0/+25
| | | | | | | | | | | | | | | Summary: These get passed to HandleTopLevelDecl() if they happen to have been deserialized for any reason. We don't want to treat them as part of the main file. Reviewers: ilya-biryukov Subscribers: ioeric, MaskRay, jkorous, arphaman, kadircet, cfe-commits Differential Revision: https://reviews.llvm.org/D54303 llvm-svn: 346503
* revert rL346478Kadir Cetinkaya2018-11-091-2/+2
| | | | | | | | | | Summary: Reviewers: Subscribers: llvm-svn: 346502
* AMDGPU: Add testcase to demonstrate a condition with pre-existing waitcntNicolai Haehnle2018-11-091-0/+36
| | | | | | Relevant for https://reviews.llvm.org/D54226. llvm-svn: 346501
* Revert "[VFS] Add "expand tilde" argument to getRealPath."Sam McCall2018-11-093-25/+23
| | | | | | | This reverts commit r346453. This is a complex change to a widely-used interface, and was not reviewed. llvm-svn: 346500
* [ARM] Don't promote i1 types in ARM CGPSam Parker2018-11-093-1/+47
| | | | | | | | | Now that we have mixed type sizes, i1 values need to be explicitly handled as we want to avoid promoting these values. Differential Revision: https://reviews.llvm.org/D54308 llvm-svn: 346499
* [x86] try to form broadcast before widening shuffle elementsSanjay Patel2018-11-096-33/+23
| | | | | | | | | | | | | | I noticed that we weren't generating broadcasts as much I thought we would with D54271, and this is part of the problem. Widening the shuffle elements means adding bitcasts and hiding the relationship between a splatted scalar and the vector. If we can form a broadcast, do that before going through the rest of the shuffle lowering because broadcasts should be cheap and can often be load-folded. Differential Revision: https://reviews.llvm.org/D54280 llvm-svn: 346498
* [RISCV] Avoid unnecessary XOR for seteq/setne 0Alex Bradbury2018-11-096-115/+116
| | | | | | | | Differential Revision: https://reviews.llvm.org/D53492 Patch by James Clarke. llvm-svn: 346497
* [RISCV] Update test/CodeGen/RISCV/calling-conv.ll after rL346432Alex Bradbury2018-11-091-8/+8
| | | | | | The DAGCombiner changes led to a different schedule. llvm-svn: 346496
* [MIPS GlobalISel] narrowScalar G_CONSTANTPetar Avramovic2018-11-091-23/+1
| | | | | | | | Legalize s64 G_CONSTANT using narrowScalar on MIPS 32. Differential Revision: https://reviews.llvm.org/D54255 llvm-svn: 346495
* [Hexagon] Handle Hexagon's SHF_HEX_GPREL section flagKrzysztof Parzyszek2018-11-093-0/+16
| | | | llvm-svn: 346494
* [llvm-exegesis] Fix unit tests on PowerPC/AArch64.Clement Courbet2018-11-092-4/+6
| | | | | | We were comparing char*s and not contents. Introduced in rL346489. llvm-svn: 346493
* Revert r346483: [CallSiteSplitting] Only record conditions up to the ↵Florian Hahn2018-11-094-74/+25
| | | | | | | | IDom(call site). This cause a failure with EXPENSIVE_CHECKS llvm-svn: 346492
* [clang-cl] Add warning for /Zc:dllexportInlines- when the flag is used with ↵Takuto Ikuta2018-11-093-0/+12
| | | | | | | | | | | | | | | | | | /fallback Summary: This is followup of https://reviews.llvm.org/D51340 Reviewers: hans, thakis Reviewed By: hans Subscribers: cfe-commits, llvm-commits Differential Revision: https://reviews.llvm.org/D54298 llvm-svn: 346491
* [X86] Add Subtarget to more lowerVectorShuffle functions. NFCI.Simon Pilgrim2018-11-091-22/+26
| | | | | | This will be necessary for an update to D54267 llvm-svn: 346490
* [llvm-exegesis][NFC] Add a way to declare the default counter binding for ↵Clement Courbet2018-11-0916-74/+113
| | | | | | | | | | | | | | | | unbound CPUs for a target. Summary: This simplifies the code and moves everything to tablegen for consistency. This also prepares the ground for adding issue counters. Reviewers: gchatelet, john.brawn, jsji Subscribers: nemanjai, mgorny, javed.absar, kbarton, tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D54297 llvm-svn: 346489
* [clangd] Make TestTU build with preamble, and fix the fallout.Sam McCall2018-11-095-67/+44
| | | | | | | | | | | | | | | | | | | | Our testing didn't reflect reality: live clangd almost always uses a preamble, and sometimes the preamble behaves differently. This patch fixes a common test helper to be more realistic. Preamble doesn't preserve information about which tokens come from the command-line (this gets inlined into a source file). So remove logic that attempts to treat symbols with such names differently. A SymbolCollectorTest tries to verify that locals in headers are not indexed, with preamble enabled this is only meaningful for locals of auto-typed functions (otherwise the bodies aren't parsed). Tests were relying on the fact that the findAnyDecl helper actually did expose symbols from headers. Resolve by making all these functions consistently able to find symbols in headers/preambles. llvm-svn: 346488
* [llvm-mca] Use a small vector for instructions in the EntryStage.Andrea Di Biagio2018-11-093-11/+15
| | | | | | | | | | | | | | | | | | | | | Use a simple SmallVector to track the lifetime of simulated instructions. An ordered map was not needed because instructions are already picked in program order. It is also much faster if we avoid searching for already retired instructions at the end of every cycle. The new policy only triggers a "garbage collection" when the number of retired instructions becomes significantly big when compared with the total size of the vector. While working on this, I noticed that instructions were correctly retired, but their internal state was not updated (i.e. there was no transition from the EXECUTED state, to the RETIRED state). While this was not a problem for the views, it prevented the EntryStage from correctly garbage collecting already retired instructions. That was a bad oversight, and this patch fixes it. The observed speedup on a debug build of llvm-mca after this patch is ~6%. On a release build of llvm-mca, the observed speedup is ~%15%. llvm-svn: 346487
* [IPSCCP,PM] Preserve DT in the new pass manager.Florian Hahn2018-11-094-43/+131
| | | | | | | | | | | | | | After D45330, Dominators are required for IPSCCP and can be preserved. This patch preserves DominatorTreeAnalysis in the new pass manager. AFAIK the legacy pass manager cannot preserve function analysis required by a module analysis. Reviewers: davide, dberlin, chandlerc, efriedma, kuhar, NutshellySima Reviewed By: chandlerc, kuhar, NutshellySima Differential Revision: https://reviews.llvm.org/D47259 llvm-svn: 346486
* [Tooling] Avoid diagnosing missing input files in an edge-case where it's ↵Sam McCall2018-11-091-0/+6
| | | | | | incorrect. llvm-svn: 346485
* [SelectionDAG] swap select_cc operands to enable foldingAlexandros Lamprineas2018-11-093-43/+93
| | | | | | | | | | | | | | | | | | The DAGCombiner tries to SimplifySelectCC as follows: select_cc(x, y, 16, 0, cc) -> shl(zext(set_cc(x, y, cc)), 4) It can't cope with the situation of reordered operands: select_cc(x, y, 0, 16, cc) In that case we just need to swap the operands and invert the Condition Code: select_cc(x, y, 16, 0, ~cc) Differential Revision: https://reviews.llvm.org/D53236 llvm-svn: 346484
* [CallSiteSplitting] Only record conditions up to the IDom(call site).Florian Hahn2018-11-094-25/+74
| | | | | | | | | | | | | | | | | | | | | | | We can stop recording conditions once we reached the immediate dominator for the block containing the call site. Conditions in predecessors of the that node will be the same for all paths to the call site and splitting is not beneficial. This patch makes CallSiteSplitting dependent on the DT anlysis. because the immediate dominators seem to be the easiest way of finding the node to stop at. I had to update some exiting tests, because they were checking for conditions that were true/false on all paths to the call site. Those should now be handled by instcombine/ipsccp. Reviewers: davide, junbuml Reviewed By: junbuml Differential Revision: https://reviews.llvm.org/D44627 llvm-svn: 346483
* [X86] Fix VZEROUPPER scheduling info on SNB,HSW,BDW,SXL,SKX.Clement Courbet2018-11-0919-248/+255
| | | | | | | | | | | | | | | | | | | | | | | Summary: Starting from SNB, VZEROUPPER is handled by the renamer and uses no proc resources. After HSW, it also has zero latency. This fixes PR35606. To reproduce: Uops: llvm-exegesis -mode=uops -opcode-name=VZEROUPPER Latency: echo -e '#LLVM-EXEGESIS-DEFREG XMM0 1\n#LLVM-EXEGESIS-DEFREG XMM1 1\nvzeroupper' | /tmp/llvm-exegesis -mode=latency -snippets-file=- echo -e '#LLVM-EXEGESIS-DEFREG XMM0 1\n#LLVM-EXEGESIS-DEFREG XMM1 1\nvzeroupper\naddps %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=latency -snippets-file=- Reviewers: RKSimon, craig.topper, andreadb Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D54107 llvm-svn: 346482
* [DebugInfo][Dexter] Unreachable line stepped onto after SimplifyCFG.Carlos Alberto Enciso2018-11-094-0/+152
| | | | | | | | In SimplifyCFG when given a conditional branch that goes to BB1 and BB2, the hoisted common terminator instruction in the two blocks, caused debug line records associated with subsequent select instructions to become ambiguous. It causes the debugger to display unreachable source lines. Differential Revision: https://reviews.llvm.org/D53390 llvm-svn: 346481
* [ARM] Enable mixed types in ARM CGPSam Parker2018-11-094-70/+298
| | | | | | | | | | | | | | | | | | | | | | Previously, during the search, all values had to have the same 'TypeSize', which is equal to number of bits of the integer type of the icmp operand. All values in the tree had to match this size; meaning that, if we searched from i16, we wouldn't accept i8s. A change in type size requires zext and truncs to perform the casts so, to allow mixed narrow types, the handling of these instructions is now slightly different: - we allow casts if their result or operand is <= TypeSize. - zexts are sinks if their result > TypeSize. - truncs are still sinks if their operand == TypeSize. - truncs are still sources if their result == TypeSize. The transformation bails on finding an icmp that operates on data smaller than the current TypeSize. Differential Revision: https://reviews.llvm.org/D54108 llvm-svn: 346480
* [ARM] Small reorganisation in ARMParallelDSPSam Parker2018-11-091-114/+161
| | | | | | | | | | | | | | | | | A few code movement things: - AreSymmetrical is now a method of BinOpChain. - Created a lambda in CreateParallelMACPairs to reduce loop nesting. - A Reduction object now gets pasted in a couple of places instead, including CreateParallelMACPairs so it doesn't need to return a value. I've also added RecordSequentialLoads, which is run before the transformation begins, and caches the interesting loads. This can then be queried later instead of cross checking many load values. Differential Revision: https://reviews.llvm.org/D54254 llvm-svn: 346479
* [lldb] Fix signature in test to match rL346453Kadir Cetinkaya2018-11-091-2/+2
| | | | llvm-svn: 346478
* [XRay] Add a test for function id encoding/decoding (NFC)Dean Michael Berris2018-11-091-0/+26
| | | | | | Increase test coverage for function enter/exit encoding/decoding. llvm-svn: 346477
* [XRay] Add a static assertion on size of metadata payload (NFC)Dean Michael Berris2018-11-091-0/+19
| | | | | | | This change adds a static check to ensure that all data metadata record payloads don't go past the available buffers in Metadata records. llvm-svn: 346476
* [XRay] Fix enter function tracing for record unwritingDean Michael Berris2018-11-092-3/+51
| | | | | | | | | | | | | | | | Summary: Before this change, we could run into a situation where we may try to undo tail exit records after writing metadata records before a function enter event. This change rectifies that by resetting the tail exit counter after writing the metadata records. Reviewers: mboerger Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54292 llvm-svn: 346475
* [XRay] Add atomic fences around non-atomic reads and writesDean Michael Berris2018-11-092-0/+29
| | | | | | | | | | | | | | | | | | Summary: We need these fences to ensure that other threads attempting to read bytes in the buffer will see thw writes committed before the extents are updated. Without these, the writes can be un-committed by the time the buffer extents counter is updated -- the fences should ensure that the records written into the log have completed by the time we observe the buffer extents from different threads. Reviewers: mboerger Subscribers: jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D54291 llvm-svn: 346474
* [XRay] Improve FDR trace handling and error messagingDean Michael Berris2018-11-0910-104/+492
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change covers a number of things spanning LLVM and compiler-rt, which are related in a non-trivial way. In LLVM, we have a library that handles the FDR mode even log loading, which uses C++'s runtime polymorphism feature to better faithfully represent the events that are written down by the FDR mode runtime. We do this by interpreting a trace that's serliased in a common format agreed upon by both the trace loading library and the FDR mode runtime. This library is under active development, which consists of features allowing us to reconstitute a higher-level event log. This event log is used by the conversion and visualisation tools we have for interpreting XRay traces. One of the tools we have is a diagnostic tool in llvm-xray called `fdr-dump` which we've been using to debug our expectations of what the FDR runtime should be writing and what the logical FDR event log structures are. We use this fairly extensively to reason about why some non-trivial traces we're generating with FDR mode runtimes fail to convert or fail to parse correctly. One of these failures we've found in manual debugging of some of the traces we've seen involve an inconsistency between the buffer extents (a record indicating how many bytes to follow are part of a logical thread's event log) and the record of the bytes written into the log -- sometimes it turns out the data could be garbage, due to buffers being recycled, but sometimes we're seeing the buffer extent indicating a log is "shorter" than the actual records associated with the buffer. This case happens particularly with function entry records with a call argument. This change for now updates the FDR mode runtime to write the bytes for the function call and arg record before updating the buffer extents atomically, allowing multiple threads to see a consistent view of the data in the buffer using the atomic counter associated with a buffer. What we're trying to prevent here is partial updates where we see the intermediary updates to the buffer extents (function record size then call argument record size) becoming observable from another thread, for instance, one doing the serialization/flushing. To do both diagnose this issue properly, we need to be able to honour the extents being set in the `BufferExtents` records marking the beginning of the logical buffers when reading an FDR trace. Since LLVM doesn't use C++'s RTTI mechanism, we instead follow the advice in the documentation for LLVM Style RTTI (https://llvm.org/docs/HowToSetUpLLVMStyleRTTI.html). We then rely on this RTTI feature to ensure that our file-based record producer (our streaming "deserializer") can honour the extents of individual buffers as we interpret traces. This also sets us up to be able to eventually do smart skipping/continuation of FDR logs, seeking instead to find BufferExtents records in cases where we find potentially recoverable errors. In the meantime, we make this change to operate in a strict mode when reading logical buffers with extent records. Reviewers: mboerger Subscribers: hiraditya, llvm-commits, jfb Differential Revision: https://reviews.llvm.org/D54201 llvm-svn: 346473
* [NFC] Add utility function for SafetyInfo updates for moveBeforeMax Kazantsev2018-11-091-3/+11
| | | | llvm-svn: 346472
* [PowerPC] [Clang] [AltiVec] The second parameter of vec_sr function should ↵Zi Xuan Wu2018-11-093-57/+87
| | | | | | | | | | | | | | | | be modulo the number of bits in the element The second parameter of vec_sr function is representing shift bits and it should be modulo the number of bits in the element like what vec_sl does now. This is actually required by the ABI: Each element of the result vector is the result of logically right shifting the corresponding element of ARG1 by the number of bits specified by the value of the corresponding element of ARG2, modulo the number of bits in the element. The bits that are shifted out are replaced by zeros. Differential Revision: https://reviews.llvm.org/D54087 llvm-svn: 346471
* [llvm-rc] Support joined or separate spelling for /fo flagPetr Hosek2018-11-093-1/+5
| | | | | | | | | CMake invokes rc using the joined spelling which appears to be supported by Microsoft's rc implementation, so we should support it as well. Differential Revision: https://reviews.llvm.org/D54191 llvm-svn: 346470
* [COFF, ARM64] Add support for MSVC buffer security checkMandeep Singh Grang2018-11-093-0/+45
| | | | | | | | | | | | Reviewers: rnk, mstorsjo, compnerd, efriedma, TomTan Reviewed By: rnk Subscribers: javed.absar, kristof.beyls, chrib, llvm-commits Differential Revision: https://reviews.llvm.org/D54248 llvm-svn: 346469
* Fix test from r346439 to also work on Windows due to path separator differences.Douglas Yung2018-11-091-1/+1
| | | | llvm-svn: 346468
* Remove unused c'tor.Bill Wendling2018-11-091-2/+0
| | | | llvm-svn: 346467
* Revert "[FileSystem] Make use of FS in TildeExpressionResolver"Jonas Devlieghere2018-11-0911-43/+21
| | | | | | | | The whole point of this change was making it possible to resolve paths without depending on the FileSystem, which is not what I did here. Not sure what I was thinking... llvm-svn: 346466
* [WebAssembly] Read prefixed opcodes as ULEB128sThomas Lively2018-11-093-12/+35
| | | | | | | | | | | | Summary: Depends on D54126. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D54138 llvm-svn: 346465
* [WebAssembly][NFC] Reorder SIMD sectionThomas Lively2018-11-091-283/+270
| | | | | | | | | | | | | | Summary: Reorders the sections in the SIMD tablegen file to roughly match the new opcode ordering. Depends on D54126. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D54134 llvm-svn: 346464
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