diff options
| author | Alex Bradbury <asb@lowrisc.org> | 2018-11-09 14:35:44 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2018-11-09 14:35:44 +0000 |
| commit | a9da1de5f46691284d2bb7973e44c6b34b8c2bc5 (patch) | |
| tree | 523b3118791206bb9f004ba61a0a1727f4b7f90d | |
| parent | 2cefaa2747403eccd691ba74986f32c242db9640 (diff) | |
| download | bcm5719-llvm-a9da1de5f46691284d2bb7973e44c6b34b8c2bc5.tar.gz bcm5719-llvm-a9da1de5f46691284d2bb7973e44c6b34b8c2bc5.zip | |
[RISCV] Update test/CodeGen/RISCV/calling-conv.ll after rL346432
The DAGCombiner changes led to a different schedule.
llvm-svn: 346496
| -rw-r--r-- | llvm/test/CodeGen/RISCV/calling-conv.ll | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/RISCV/calling-conv.ll b/llvm/test/CodeGen/RISCV/calling-conv.ll index 8440045fd91..7d93499ab1d 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv.ll @@ -997,14 +997,14 @@ define void @caller_large_scalar_ret() nounwind { define void @callee_large_struct_ret(%struct.large* noalias sret %agg.result) nounwind { ; RV32I-FPELIM-LABEL: callee_large_struct_ret: ; RV32I-FPELIM: # %bb.0: +; RV32I-FPELIM-NEXT: addi a1, zero, 4 +; RV32I-FPELIM-NEXT: sw a1, 12(a0) +; RV32I-FPELIM-NEXT: addi a1, zero, 3 +; RV32I-FPELIM-NEXT: sw a1, 8(a0) ; RV32I-FPELIM-NEXT: addi a1, zero, 2 ; RV32I-FPELIM-NEXT: sw a1, 4(a0) ; RV32I-FPELIM-NEXT: addi a1, zero, 1 ; RV32I-FPELIM-NEXT: sw a1, 0(a0) -; RV32I-FPELIM-NEXT: addi a1, zero, 3 -; RV32I-FPELIM-NEXT: sw a1, 8(a0) -; RV32I-FPELIM-NEXT: addi a1, zero, 4 -; RV32I-FPELIM-NEXT: sw a1, 12(a0) ; RV32I-FPELIM-NEXT: ret ; ; RV32I-WITHFP-LABEL: callee_large_struct_ret: @@ -1013,14 +1013,14 @@ define void @callee_large_struct_ret(%struct.large* noalias sret %agg.result) no ; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 +; RV32I-WITHFP-NEXT: addi a1, zero, 4 +; RV32I-WITHFP-NEXT: sw a1, 12(a0) +; RV32I-WITHFP-NEXT: addi a1, zero, 3 +; RV32I-WITHFP-NEXT: sw a1, 8(a0) ; RV32I-WITHFP-NEXT: addi a1, zero, 2 ; RV32I-WITHFP-NEXT: sw a1, 4(a0) ; RV32I-WITHFP-NEXT: addi a1, zero, 1 ; RV32I-WITHFP-NEXT: sw a1, 0(a0) -; RV32I-WITHFP-NEXT: addi a1, zero, 3 -; RV32I-WITHFP-NEXT: sw a1, 8(a0) -; RV32I-WITHFP-NEXT: addi a1, zero, 4 -; RV32I-WITHFP-NEXT: sw a1, 12(a0) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 16 |
