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* [AVR] Implement some missing code pathsDylan McKay2017-12-114-15/+54
| | | | | | This has been broken since r320009. llvm-svn: 320348
* [AVR] Fix incorrectly-calculated AVRMCExpr evaluationsDylan McKay2017-12-111-12/+9
| | | | | | This has been broken since r320009. llvm-svn: 320347
* Move PseudoTerminal to the lldb_private namespacePavel Labath2017-12-1113-26/+23
| | | | | | | lldb_utility doesn't make sense, as it is no longer even living in the "utility" module. llvm-svn: 320346
* MainLoop: avoid infinite loop when pty slave gets closedPavel Labath2017-12-112-1/+21
| | | | | | | | | | | | | | | | | | | | | Summary: For ptys (at least on Linux), the end-of-file (closing of the slave FD) is signalled by the POLLHUP flag. We were ignoring this flag, which meant that when this happened, we would spin in a loop, continuously calling poll(2) and not making any progress. This makes sure we treat POLLHUP as a read event (reading will return 0), and we call the registered callback when it happens. This is the behavior our clients expect (and is consistent with how select(2) works). Reviewers: eugene, beanz Subscribers: lldb-commits Differential Revision: https://reviews.llvm.org/D41008 llvm-svn: 320345
* [DAGCombiner] Support folding (mulhs/u X, 0)->0 for vectors.Craig Topper2017-12-112-8/+19
| | | | | | We should probably also fold (mulhs/u X, 1) for vectors, but that's harder. llvm-svn: 320344
* [DAGCombiner] Reuse existing SDLoc variable instead of creating a new one. NFCCraig Topper2017-12-111-4/+3
| | | | llvm-svn: 320343
* [X86] Regenerate test with update_llc_test_checks.pyCraig Topper2017-12-111-76/+340
| | | | llvm-svn: 320342
* Revert "[DataEncoder] Replace buggy versions of write functions."Davide Italiano2017-12-111-8/+36
| | | | | | | The commit exposes a bunch of failures in the LLDB testsuite that I need to analyze more carefully. Reverting for now. llvm-svn: 320341
* [X86] Add a test case for masked scatter where the index needs to be ↵Craig Topper2017-12-111-0/+52
| | | | | | legalized from v2i32 while other types are legal. llvm-svn: 320340
* Fix test to test what it intended to test.Rafael Espindola2017-12-111-4/+7
| | | | | | | The test was added to test that we don't merge read only data sections, but the sections in the test were rw. llvm-svn: 320339
* [DarwinLog] Remove other dead code. Found while reading this file.Davide Italiano2017-12-101-54/+0
| | | | llvm-svn: 320338
* [MachException] Garbage collect unused and dead code.Davide Italiano2017-12-101-27/+0
| | | | llvm-svn: 320337
* [ScopBuilder] Fix typo. NFC.Michael Kruse2017-12-101-4/+4
| | | | | | | | Contributed-by: Nandini Singhal <cs15mtech01004@iith.ac.in> Differential Revision: https://reviews.llvm.org/D41047 llvm-svn: 320336
* [DataEncoder] Replace buggy versions of write functions.Davide Italiano2017-12-101-36/+8
| | | | | | | | | | They cause an ubsan error when ran through the testsuite (store to misaligned address is UB). This commit kills two birds with one stone, as we also remove some code while fixing it. <rdar://problem/35941757> llvm-svn: 320335
* [X86] Add ROL/ROR schedule testsSimon Pilgrim2017-12-101-2/+732
| | | | llvm-svn: 320334
* [X86] Add DIV/MUL/NEG/NOP/NOT/PAUSE schedule testsSimon Pilgrim2017-12-101-6/+862
| | | | llvm-svn: 320333
* [X86] Add DEC/INC schedule testsSimon Pilgrim2017-12-102-2/+1079
| | | | | | Include i686 (non-REX) variant tests as well llvm-svn: 320332
* [X86] Add INS/OUTS schedule testsSimon Pilgrim2017-12-101-8/+186
| | | | llvm-svn: 320331
* [X86] Add CMPS/MOVS/SCAS/STOS schedule testsSimon Pilgrim2017-12-101-20/+412
| | | | llvm-svn: 320330
* [X86] Add CMOV schedule testsSimon Pilgrim2017-12-102-1/+2004
| | | | llvm-svn: 320329
* [X86] Add BT/BTC/BTR/BTS schedule testsSimon Pilgrim2017-12-101-4/+669
| | | | llvm-svn: 320328
* Move RelaPlt and RelaIplt to InX. NFC.Rafael Espindola2017-12-104-28/+29
| | | | llvm-svn: 320327
* [X86] Add VCOMISDZrr, VCOMISSZrr, VUCOMISDZrr, and VUCOMISSZrr to the ↵Craig Topper2017-12-101-4/+4
| | | | | | skylake server sheduler model llvm-svn: 320326
* [X86] Rename some instructions that start with Int_ to have the _Int at the end.Craig Topper2017-12-1013-267/+267
| | | | | | | | This matches AVX512 version and is more consistent overall. And improves our scheduler models. In some cases this adds _Int to instructions that didn't have any Int_ before. It's a side effect of the adjustments made to some of the multiclasses. llvm-svn: 320325
* Move RelaDyn to InX. NFC.Rafael Espindola2017-12-104-40/+38
| | | | llvm-svn: 320324
* Remove this->. NFC.Rafael Espindola2017-12-101-2/+2
| | | | llvm-svn: 320323
* [X86][X87] Fix typo in znver1 FIST/FISTT schedule patternsSimon Pilgrim2017-12-102-5/+5
| | | | llvm-svn: 320322
* [X86][X87] Add missing x87 scheduler testsSimon Pilgrim2017-12-101-62/+1322
| | | | | | Split off some 'n' instruction versions to make it clearer when WAIT is being inserted llvm-svn: 320321
* [X86] Rename some instructions from 'rb' to 'rrb' to make 'b' a proper ↵Craig Topper2017-12-103-18/+18
| | | | | | | | suffix. Fix the scheduling information for some of them. Some of the scheduling information was only present for the 'rb' version' and not the 'rr' version. Now we match 'rr(b?)' llvm-svn: 320320
* [X86] Add VCVTQQ2PS to the skylake server scheduler models.Craig Topper2017-12-102-1/+7
| | | | llvm-svn: 320319
* [X86] Add VPMULLWZ256 to the skylake server scheduler modelCraig Topper2017-12-101-0/+2
| | | | llvm-svn: 320318
* [X86] Add 256/512-bit EVEX VPSADBW instructions to skylake server scheduler ↵Craig Topper2017-12-101-2/+4
| | | | | | model. llvm-svn: 320317
* [X86] Fix a few instructions that were named Z512 instead of just Z.Craig Topper2017-12-104-15/+15
| | | | | | This makes things consistent with our normal instruction naming. llvm-svn: 320316
* [X86] Add VPSRLWZrr to skylake server scheduler model.Craig Topper2017-12-101-0/+1
| | | | llvm-svn: 320315
* [X86] Add VPUNPCKLWDZrr to skylake server scheduler model.Craig Topper2017-12-101-0/+1
| | | | llvm-svn: 320314
* [X86] Adjust tablegen includes so we can use Instructions in scheduler ↵Craig Topper2017-12-102-26/+25
| | | | | | | | models instead of just instregexs. This separates the CPU specific scheduler model includes to occur after the instructions. Moves the instruction includes between the basic scheduler information and the CPU specific scheduler models. llvm-svn: 320313
* [SimplifyLibCalls] propagate FMF when folding pow(x, -1.0) callSanjay Patel2017-12-102-15/+12
| | | | | | | Follow-up for a bug that's similar to: https://bugs.llvm.org/show_bug.cgi?id=35601 llvm-svn: 320312
* [InstCombine] add test for pow(x, -1.0) with FMF; NFCSanjay Patel2017-12-101-20/+23
| | | | llvm-svn: 320311
* [SimplifyLibCalls] propagate FMF when folding pow(x, 2.0) call (PR35601)Sanjay Patel2017-12-102-3/+8
| | | | | | | This should fix the larger problem with sqrt shown in: https://bugs.llvm.org/show_bug.cgi?id=35601 llvm-svn: 320310
* [InstCombine] add test for pow(x, 2.0) with FMF; NFCSanjay Patel2017-12-101-6/+18
| | | | llvm-svn: 320309
* [X86] Flag BroadWell scheduler model as completeSimon Pilgrim2017-12-108-44/+43
| | | | | | Locally tag COPY as WriteMove, which has caused some reg-reg + reg-mem instruction tests to reorder. llvm-svn: 320308
* Regenerate some AVX2+ scheduling tests that got missedSimon Pilgrim2017-12-102-39/+39
| | | | llvm-svn: 320307
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-12-101-3/+3
| | | | llvm-svn: 320306
* Regenerate some scheduling tests that got missedSimon Pilgrim2017-12-102-20/+20
| | | | llvm-svn: 320305
* [X86] Flag ZNVER1 scheduler model as completeSimon Pilgrim2017-12-101-6/+3
| | | | | | We just have to locally tag COPY as WriteMove llvm-svn: 320304
* [X86] Flag SLM scheduler model as completeSimon Pilgrim2017-12-101-5/+3
| | | | | | We just have to locally tag COPY as WriteMove llvm-svn: 320303
* [X86][AVX[ Tag VZEROALL/VZEROUPPER instructions scheduler classesSimon Pilgrim2017-12-102-3/+9
| | | | llvm-svn: 320302
* [X86] Tag SSE4A instructions as SSE INTALU scheduler classesSimon Pilgrim2017-12-101-4/+8
| | | | llvm-svn: 320301
* [X86] Flag BTVER2 scheduler model as completeSimon Pilgrim2017-12-101-4/+3
| | | | | | We just have to locally tag COPY as WriteMove llvm-svn: 320300
* [X86] Tag ADJSTACK instructions as INTALU scheduler classSimon Pilgrim2017-12-101-11/+9
| | | | llvm-svn: 320299
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