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| author | Craig Topper <craig.topper@intel.com> | 2017-12-11 08:33:20 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-11 08:33:20 +0000 |
| commit | ad45bf5895182563b2d107e4ecb76d0e340ebd17 (patch) | |
| tree | 72a939dc51278ff2055ab7cff68a9eeaf66240c6 | |
| parent | 65ed4d4492321f3f6f0417dc9be4c5e5cc910b1e (diff) | |
| download | bcm5719-llvm-ad45bf5895182563b2d107e4ecb76d0e340ebd17.tar.gz bcm5719-llvm-ad45bf5895182563b2d107e4ecb76d0e340ebd17.zip | |
[DAGCombiner] Support folding (mulhs/u X, 0)->0 for vectors.
We should probably also fold (mulhs/u X, 1) for vectors, but that's harder.
llvm-svn: 320344
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 16 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/pr34855.ll | 11 |
2 files changed, 19 insertions, 8 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 2170670a0b6..4cc86ed2d36 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3099,6 +3099,14 @@ SDValue DAGCombiner::visitMULHS(SDNode *N) { EVT VT = N->getValueType(0); SDLoc DL(N); + if (VT.isVector()) { + // fold (mulhs x, 0) -> 0 + if (ISD::isBuildVectorAllZeros(N1.getNode())) + return N1; + if (ISD::isBuildVectorAllZeros(N0.getNode())) + return N0; + } + // fold (mulhs x, 0) -> 0 if (isNullConstant(N1)) return N1; @@ -3138,6 +3146,14 @@ SDValue DAGCombiner::visitMULHU(SDNode *N) { EVT VT = N->getValueType(0); SDLoc DL(N); + if (VT.isVector()) { + // fold (mulhu x, 0) -> 0 + if (ISD::isBuildVectorAllZeros(N1.getNode())) + return N1; + if (ISD::isBuildVectorAllZeros(N0.getNode())) + return N0; + } + // fold (mulhu x, 0) -> 0 if (isNullConstant(N1)) return N1; diff --git a/llvm/test/CodeGen/X86/pr34855.ll b/llvm/test/CodeGen/X86/pr34855.ll index ee4428908a2..746d1ff56cc 100644 --- a/llvm/test/CodeGen/X86/pr34855.ll +++ b/llvm/test/CodeGen/X86/pr34855.ll @@ -8,18 +8,13 @@ define void @PR34855(<2 x i32> *%p0, <2 x i32> *%p1, <2 x i32> *%p2) { ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero -; X86-NEXT: movlps %xmm0, (%eax) +; X86-NEXT: movsd %xmm0, (%eax) ; X86-NEXT: retl ; ; X64-LABEL: PR34855: ; X64: # %bb.0: -; X64-NEXT: movslq 4(%rdi), %rax -; X64-NEXT: movq %rax, %xmm0 -; X64-NEXT: movslq (%rdi), %rax -; X64-NEXT: movq %rax, %xmm1 -; X64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] -; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3] -; X64-NEXT: movq %xmm0, (%rdx) +; X64-NEXT: movq (%rdi), %rax +; X64-NEXT: movq %rax, (%rdx) ; X64-NEXT: retq %tmp = load <2 x i32>, <2 x i32>* %p0, align 8 %tmp1 = load <2 x i32>, <2 x i32>* %p1, align 8 |
