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* [sanitizer] Suppress unused function warningVitaly Buka2018-06-181-1/+2
| | | | llvm-svn: 334923
* [X86] Add '.s' aliases to the assembler for the various redundant move ↵Craig Topper2018-06-186-54/+197
| | | | | | | | | | encodings to match gas and our EVEX instructions. We already have these aliases for EVEX enocded instructions, but not for the GPR, MMX, SSE, and VEX versions. Also remove the vpextrw.s EVEX alias. That's not something gas implements. llvm-svn: 334922
* Fix the 'tb' alias commandFrederic Riss2018-06-182-1/+26
| | | | | | | No idea when this broke or if it ever worked. Added a small test for one-shot breakpoints while I was there. llvm-svn: 334921
* [X86] Move the 'vmovq.s' and similar assembly strings for EVEX vector moves ↵Craig Topper2018-06-187-487/+522
| | | | | | | | | | with reversed operands to InstAliases. The .s assembly strings allow the reversed forms to be targeted from assembly which matches gas behavior. But when printing the instructions we should print them without the .s to match other tooling like objdump. By using InstAliases we can use the normal string in the instruction and just hide it from the assembly parser. Ideally we'd add the .s versions to the legacy SSE and VEX versions as well for full compatibility with gas. Not sure how we got to state where only EVEX was supported. llvm-svn: 334920
* [TableGen] Prevent double flattening of InstAlias asm strings in the asm ↵Craig Topper2018-06-185-14/+21
| | | | | | | | | | | | matcher emitter. Unlike CodeGenInstruction, CodeGenInstAlias was flatting asm strings in its constructor. For instructions it was the users responsibility to flatten the string. AsmMatcherEmitter didn't know this and treated them the same. This caused double flattening of InstAliases. This is mostly harmless unless the desired assembly string contains curly braces. The second flattening wouldn't know to ignore these and would remove the curly braces. And for variant 1 it would remove the contents of them as well. To mitigate this, this patch makes removes the flattening from the CodeGenIntAlias constructor and modifies AsmWriterEmitter to account for the flattening not having been done. llvm-svn: 334919
* [ORC] Remove redundant conditionLang Hames2018-06-171-1/+1
| | | | llvm-svn: 334918
* Fix libcxx tests after clang r334677.Richard Smith2018-06-171-3/+7
| | | | | | Feature test macro versions may have a trailing L. llvm-svn: 334917
* [ORC] Only notify queries that they are resolved/ready when the query stateLang Hames2018-06-173-11/+96
| | | | | | | | changes. This guards against redundant notifications. llvm-svn: 334916
* [X86] Add all the FMA instructions direclty to the load folding table ↵Craig Topper2018-06-172-100/+544
| | | | | | | | instead of proxying through X86InstrFMA3Info. These increases the size of the static tables, but is closer to what we would get if used the autogenerated table directly. This reduces the remaining large deltas between what's in the manual table and what's in the autogenerated table. llvm-svn: 334915
* [sanitizer] Fix tsan GO buildVitaly Buka2018-06-171-20/+20
| | | | llvm-svn: 334914
* [sanitizer] Fix s390 build after r334900Vitaly Buka2018-06-171-1/+1
| | | | llvm-svn: 334913
* [sanitizer] Use confstr to check libc version in InitTlsSizeVitaly Buka2018-06-172-39/+66
| | | | | | | | | | Reviewers: Lekensteyn, jakubjelinek Subscribers: kubamracek, llvm-commits Differential Revision: https://reviews.llvm.org/D48265 llvm-svn: 334912
* [ORC] Suppress an unused variable warning for a debug-mode only use.Lang Hames2018-06-171-0/+1
| | | | llvm-svn: 334911
* [ORC] Erase empty dependence sets when adding new symbol dependencies.Lang Hames2018-06-172-0/+41
| | | | llvm-svn: 334910
* [ORC] In MaterializationResponsibility, only maintain the Materializing flag onLang Hames2018-06-171-2/+12
| | | | | | | | | | | symbols in debug mode. The MaterializationResponsibility class hijacks the Materializing flag to track symbols that have not yet been resolved in order to guard against redundant resolution. Since this is an API contract check and only enforced in debug mode there is no reason to maintain the flag state in release mode. llvm-svn: 334909
* [X86] Pass the parent SDNode to X86DAGToDAGISel::selectScalarSSELoad to ↵Craig Topper2018-06-173-16/+14
| | | | | | | | | | simplify the hasSingleUseFromRoot handling. Some of the calls to hasSingleUseFromRoot were passing the load itself. If the load's chain result has a user this would count against that. By getting the true parent of the match and ensuring any intermediate between the match and the load have a single use we can avoid this case. isLegalToFold will take care of checking users of the load's data output. This fixed at least fma-scalar-memfold.ll to succed without the peephole pass. llvm-svn: 334908
* [llvm-mca][X86] Add some avx512f/avx512vl resource test placeholdersSimon Pilgrim2018-06-172-0/+514
| | | | | | There are a lot of instructions to add under these ISAs (and the other AVX512 variants) but this should demonstrate how to test for the EVEX instructions with different maskings llvm-svn: 334907
* [AArch64][SVE] Asm: Support for bitwise operations on predicate vectors.Sander de Smalen2018-06-1733-0/+780
| | | | | | | | | | | | | | | | | | | This patch adds support for instructions performing bitwise operations on predicate vectors, including AND, BIC, EOR, NAND, NOR, ORN, ORR, and their status flag setting variants ANDS, BICS, EORS, NANDS, ORNS, ORRS. This patch also adds several aliases: orr p0.b, p1/z, p1.b, p1.b => mov p0.b, p1.b orrs p0.b, p1/z, p1.b, p1.b => movs p0.b, p1.b and p0.b, p1/z, p2.b, p2.b => mov p0.b, p1/z, p2.b ands p0.b, p1/z, p2.b, p2.b => movs p0.b, p1/z, p2.b eor p0.b, p1/z, p2.b, p1.b => not p0.b, p1/z, p2.b eors p0.b, p1/z, p2.b, p1.b => nots p0.b, p1/z, p2.b llvm-svn: 334906
* [AArch64][SVE] Asm: Support for SEL (vector/predicate) instructions.Sander de Smalen2018-06-174-0/+185
| | | | | | | | Support for SVE's predicated select instructions to select elements from either vector, both in a data-vector and a predicate-vector variant. llvm-svn: 334905
* [NVPTX] Ignore target-cpu and -features for inliningJonas Hahnfeld2018-06-171-0/+8
| | | | | | | | | | We don't want to prevent inlining because of target-cpu and -features attributes that were added to newer versions of LLVM/Clang: There are no incompatible functions in PTX, ptxas will throw errors in such cases. Differential Revision: https://reviews.llvm.org/D47691 llvm-svn: 334904
* Revert "[CMake] Use a different source depending on C++ support"Jonas Hahnfeld2018-06-172-16/+8
| | | | | | | | | This reverts commit r332924 and followup r332936 silencing a warning. The change breaks the build on x86 if there is no 32-bit version of the C++ libraries, see discussion in https://reviews.llvm.org/D47169. llvm-svn: 334903
* [fuzzer] Python 3 print fixesVitaly Buka2018-06-172-4/+4
| | | | llvm-svn: 334902
* [fuzzer] Fix collect_data_flow.py for python 3Vitaly Buka2018-06-171-1/+1
| | | | llvm-svn: 334901
* [sanitizer] Use const char* in internal_simple_strtollVitaly Buka2018-06-177-8/+8
| | | | llvm-svn: 334900
* [WebAssembly] Simple comment fix. NFC.Heejin Ahn2018-06-171-1/+1
| | | | llvm-svn: 334899
* [X86] More additions to the load folding tables based on the autogenerated ↵Craig Topper2018-06-166-37/+820
| | | | | | | | tables. Including more additions for NotMemoryFoldable to remove some entries from the autogenerated table. llvm-svn: 334898
* [X86] Hide POP16/32/64rmr and PUSH16/32/64rmr instructions from the assembly ↵Craig Topper2018-06-161-0/+12
| | | | | | | | parser. These all have a short form encoding that the assembler already prefers. Though that preference seems to only be based on order in the .td fie. Hiding the long form saves space in the table and prevents us from breaking the implicit order based priority. llvm-svn: 334897
* [X86] Fix an inconsistency between AVX512 and AVX/SSE version on a couple ↵Craig Topper2018-06-161-2/+2
| | | | | | | | | | instructions. VMOVPQIto64Zmr is not a 64-bit mode only instruction. But I don't know how to test this because VMOVPQIto64mr should always have priority over it in 32-bit mode since its only advantage is XMM16-XMM31 which aren't usable in 32-bit mode. VMOVPQIto64Zrr is a 64-bit mode only instruction, but we don't need to explicitly mark it as such because it uses a GR64 register which won't parse in 32-bit mode. llvm-svn: 334896
* CorrelatedValuePropagation: Preserve DT.Michael Zolotukhin2018-06-164-8/+18
| | | | | | | | | | | | | | Summary: We only modify CFG in a couple of places, and we can preserve DT there with a little effort. Reviewers: davide, vsk Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D48059 llvm-svn: 334895
* Remove P0771, which was not passed in RapperswilMarshall Clow2018-06-161-1/+0
| | | | llvm-svn: 334894
* Adjust to recent LLVM changes to fix buildbotsTobias Grosser2018-06-161-2/+2
| | | | llvm-svn: 334893
* [Dominators] Change getNode parameter type to const NodeT * (NFC).Florian Hahn2018-06-162-3/+7
| | | | | | | | | | | | | | DominatorTreeBase::getNode does not modify its parameter and this change allows callers that only have access to const pointers to use it without casting. Reviewers: kuhar, dblaikie, chandlerc Reviewed By: dblaikie Differential Revision: https://reviews.llvm.org/D48231 llvm-svn: 334892
* [analyzer] Add method to the generic SMT API to dump the SMT formulaMikhail R. Gadelha2018-06-162-0/+9
| | | | | | | | | | | | | | | | | | | Summary: New method dump the SMT formula and the Z3 implementation. There is no test because I only used it for debugging. However, if requested, I can add an option to the static analyzer to dump the formula (whole program? per path?), maybe something like the trimmed graph but for SMT formulas. Reviewers: NoQ, george.karpenkov, ddcc Reviewed By: george.karpenkov Subscribers: xazax.hun, szepet, a.sidorin Differential Revision: https://reviews.llvm.org/D48221 llvm-svn: 334891
* Fix namespaces. No functionality change.Benjamin Kramer2018-06-163-3/+5
| | | | llvm-svn: 334890
* Revert r334887, as GCC 4.8 does not have is_trivially_copy_constructible & coFlorian Hahn2018-06-162-124/+0
| | | | llvm-svn: 334889
* [SmallSet] Avoid using is_trivially_XXX<>::value which is C++17Florian Hahn2018-06-161-5/+5
| | | | llvm-svn: 334888
* [SmallSet] Add SmallSetIterator.Florian Hahn2018-06-162-0/+124
| | | | | | | | | | | | | | | This patch adds a simple const_iterator implementation for SmallSet by delegating to either a SmallVector::const_iterator or std::set::const_iterator, depending on which storage is used by the SmallSet. Reviewers: dblaikie, craig.topper Reviewed By: dblaikie Differential Revision: https://reviews.llvm.org/D47942 llvm-svn: 334887
* Add RUN line for amdgcn to lit test conditional-temporaries.cppYaxun Liu2018-06-161-0/+2
| | | | | | This is partial re-commit of r332982. llvm-svn: 334886
* [ELF] Pass callables by function_refBenjamin Kramer2018-06-167-20/+20
| | | | | | | No need to create a heavyweight std::function if it's not stored. No functionality change intended. llvm-svn: 334885
* [sanitizer_common] Fix windows build caused by r334881Fangrui Song2018-06-161-1/+3
| | | | llvm-svn: 334884
* [asan] Enable fgets_fputs test on AndroidVitaly Buka2018-06-161-5/+2
| | | | | | | | | "echo data" didn't work because %run on android executes test on the device when lit shell command on the host system. https://github.com/google/sanitizers/issues/952 llvm-svn: 334883
* [AMDGPU] setcc (select cc, CT, CF), CF, eq | ne -> xor cc, -1 | ccStanislav Mekhanoshin2018-06-162-17/+147
| | | | | | | | | This is the common case in the BE when we serialize condition and then rematerialize it. Use either original or inverted condition. Differential Revision: https://reviews.llvm.org/D48246 llvm-svn: 334882
* [sanitizer_common] Use O_TRUNC for WrOnly access mode.Fangrui Song2018-06-163-2/+8
| | | | | | | | | | | | Summary: Otherwise if the file existed and was larger than the write size before the OpenFile call, the file will not be truncated and contain garbage in trailing bytes. Reviewers: glider, kcc, vitalybuka Subscribers: kubamracek, delcypher, llvm-commits, #sanitizers Differential Revision: https://reviews.llvm.org/D48250 llvm-svn: 334881
* Avoid needing to walk out legalization tables. NFCI.Nirav Dave2018-06-162-193/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Relanding after fixing expensive check from modifying tables. To avoid redundant work, during DAG legalization we keep tables mapping pre-legalized SDValues to post-legalized SDValues and a SDValue-to-SDValue map to enable fast node replacements. However, as the keys are nodes which may be reused it is possible that an entry in a table refers to a now deleted node N (that should have been renamed by the value replacement map) while a new node N' exists. If N' is then replaced that entry would be wrong. Previously we avoided this by when potentially violating this property, walking every table and updating all node pointers. This is very expensive but hopefully rare occurance. This patch assigns each instance of a SDValue used in legalization a unique id and uses these ids in the legalization tables. This avoids any such aliasing issue, avoiding the full table search and allowing more aggressive incremental table pruning. In some cases this is a 1000x speedup to compilation. Reviewers: jyknight, echristo, bogner, tra Reviewed By: bogner Subscribers: dberris, grandinj, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D47959 llvm-svn: 334880
* Call CreateTempAllocaWithoutCast for ActiveFlagYaxun Liu2018-06-161-2/+2
| | | | | | This is partial re-commit of r332982. llvm-svn: 334879
* Revert "[SCEV] Use LLVM_MARK_AS_BITMASK_ENUM in SCEV." -- breaks MSVC builds.Justin Lebar2018-06-163-40/+84
| | | | | | This reverts D48237. llvm-svn: 334878
* Revert "[SCEV] Simplify some flags expressions." -- dependent revision ↵Justin Lebar2018-06-161-4/+4
| | | | | | | | breaks MSVC builds. This reverts D48238. llvm-svn: 334877
* Utilize new SDNode flag functionality to expand current support for fmaMichael Berg2018-06-164-62/+32
| | | | | | | | | | | | | | Summary: This patch originated from D47388 and is a proper subset of the originating changes, containing only the fmf optimization guard extensions. Reviewers: spatel, hfinkel, wristow, arsenm, javed.absar, rampitec, nhaehnle, nemanjai Reviewed By: rampitec, nhaehnle Subscribers: tpr, nemanjai, wdng Differential Revision: https://reviews.llvm.org/D47918 llvm-svn: 334876
* [SCEV] Simplify some flags expressions.Justin Lebar2018-06-151-4/+4
| | | | | | | | | | | | | | Summary: Sending for presubmit review out of an abundance of caution; it would be bad to mess this up. Reviewers: sanjoy Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D48238 llvm-svn: 334875
* [SCEV] Use LLVM_MARK_AS_BITMASK_ENUM in SCEV.Justin Lebar2018-06-153-84/+40
| | | | | | | | | | | | | | | | | | Summary: Obviates the need for mask/clear/setFlags helpers. There are some expressions here which can be simplified, but to keep this easy to review, I have not simplified them in this patch. No functional change. Reviewers: sanjoy Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D48237 llvm-svn: 334874
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