[AArch64][SVE] Asm: Support for bitwise operations on predicate vectors.

This patch adds support for instructions performing bitwise operations
on predicate vectors, including AND, BIC, EOR, NAND, NOR, ORN, ORR, and
their status flag setting variants ANDS, BICS, EORS, NANDS, ORNS, ORRS.

This patch also adds several aliases:

  orr  p0.b, p1/z, p1.b, p1.b  => mov  p0.b, p1.b
  orrs p0.b, p1/z, p1.b, p1.b  => movs p0.b, p1.b

  and  p0.b, p1/z, p2.b, p2.b  => mov  p0.b, p1/z, p2.b
  ands p0.b, p1/z, p2.b, p2.b  => movs p0.b, p1/z, p2.b

  eor  p0.b, p1/z, p2.b, p1.b  => not  p0.b, p1/z, p2.b
  eors p0.b, p1/z, p2.b, p1.b  => nots p0.b, p1/z, p2.b

llvm-svn: 334906

33 files changed, 780 insertions, 0 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index c9fac39a709..2f9defd2688 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -60,7 +60,21 @@ let Predicates = [HasSVE] in {
   // Select elements from either vector (predicated)
   defm SEL_ZPZZ    : sve_int_sel_vvv<"sel">;
 
+  def AND_PPzPP   : sve_int_pred_log<0b0000, "and">;
+  def BIC_PPzPP   : sve_int_pred_log<0b0001, "bic">;
+  def EOR_PPzPP   : sve_int_pred_log<0b0010, "eor">;
   def SEL_PPPP    : sve_int_pred_log<0b0011, "sel">;
+  def ANDS_PPzPP  : sve_int_pred_log<0b0100, "ands">;
+  def BICS_PPzPP  : sve_int_pred_log<0b0101, "bics">;
+  def EORS_PPzPP  : sve_int_pred_log<0b0110, "eors">;
+  def ORR_PPzPP   : sve_int_pred_log<0b1000, "orr">;
+  def ORN_PPzPP   : sve_int_pred_log<0b1001, "orn">;
+  def NOR_PPzPP   : sve_int_pred_log<0b1010, "nor">;
+  def NAND_PPzPP  : sve_int_pred_log<0b1011, "nand">;
+  def ORRS_PPzPP  : sve_int_pred_log<0b1100, "orrs">;
+  def ORNS_PPzPP  : sve_int_pred_log<0b1101, "orns">;
+  def NORS_PPzPP  : sve_int_pred_log<0b1110, "nors">;
+  def NANDS_PPzPP : sve_int_pred_log<0b1111, "nands">;
 
   // continuous load with reg+immediate
   defm LD1B_IMM    : sve_mem_cld_si<0b0000, "ld1b",  Z_b, ZPR8>;
@@ -511,4 +525,19 @@ let Predicates = [HasSVE] in {
                   (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn), 1>;
   def : InstAlias<"mov $Pd, $Pg/m, $Pn",
                   (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd), 1>;
+  def : InstAlias<"mov $Pd, $Pn",
+                  (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn), 1>;
+  def : InstAlias<"mov $Pd, $Pg/z, $Pn",
+                  (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn), 1>;
+
+  def : InstAlias<"movs $Pd, $Pn",
+                  (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn), 1>;
+  def : InstAlias<"movs $Pd, $Pg/z, $Pn",
+                  (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn), 1>;
+
+  def : InstAlias<"not $Pd, $Pg/z, $Pn",
+                  (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg), 1>;
+
+  def : InstAlias<"nots $Pd, $Pg/z, $Pn",
+                  (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg), 1>;
 }
diff --git a/llvm/test/MC/AArch64/SVE/and-diagnostics.s b/llvm/test/MC/AArch64/SVE/and-diagnostics.s
index b3d1f8ec832..2ea6b3eb272 100644
--- a/llvm/test/MC/AArch64/SVE/and-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/and-diagnostics.s
@@ -65,3 +65,30 @@ and z0.d, p8/z, z0.d, z1.d
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
 // CHECK-NEXT: and z0.d, p8/z, z0.d, z1.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+and p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: and p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+and p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: and p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+and p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: and p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+and p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: and p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/and.s b/llvm/test/MC/AArch64/SVE/and.s
index 7606128fd0c..88e2439c44e 100644
--- a/llvm/test/MC/AArch64/SVE/and.s
+++ b/llvm/test/MC/AArch64/SVE/and.s
@@ -90,3 +90,21 @@ and     z31.d, p7/m, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x1f,0xda,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 1f da 04 <unknown>
+
+and     p0.b, p0/z, p0.b, p1.b
+// CHECK-INST: and     p0.b, p0/z, p0.b, p1.b
+// CHECK-ENCODING: [0x00,0x40,0x01,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 01 25 <unknown>
+
+and     p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: mov     p0.b, p0/z, p0.b
+// CHECK-ENCODING: [0x00,0x40,0x00,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 00 25 <unknown>
+
+and     p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: mov     p15.b, p15/z, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0x0f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d 0f 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ands-diagnostics.s b/llvm/test/MC/AArch64/SVE/ands-diagnostics.s
new file mode 100644
index 00000000000..423496b15c2
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ands-diagnostics.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+ands p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: ands p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ands p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: ands p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ands p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: ands p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+ands p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ands p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ands.s b/llvm/test/MC/AArch64/SVE/ands.s
new file mode 100644
index 00000000000..07c890709b4
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ands.s
@@ -0,0 +1,27 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ands    p0.b, p0/z, p0.b, p1.b
+// CHECK-INST: ands    p0.b, p0/z, p0.b, p1.b
+// CHECK-ENCODING: [0x00,0x40,0x41,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 41 25 <unknown>
+
+ands    p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: movs    p0.b, p0/z, p0.b
+// CHECK-ENCODING: [0x00,0x40,0x40,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 40 25 <unknown>
+
+ands    p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: movs    p15.b, p15/z, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0x4f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d 4f 25 <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE/bic-diagnostics.s b/llvm/test/MC/AArch64/SVE/bic-diagnostics.s
index e8ab74c3957..61d0231e4cf 100644
--- a/llvm/test/MC/AArch64/SVE/bic-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/bic-diagnostics.s
@@ -65,3 +65,30 @@ bic z0.d, p8/z, z0.d, z1.d
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
 // CHECK-NEXT: bic z0.d, p8/z, z0.d, z1.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+bic p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: bic p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bic p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: bic p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bic p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: bic p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+bic p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: bic p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/bic.s b/llvm/test/MC/AArch64/SVE/bic.s
index 0a26b927a7c..bd19fcd9fcf 100644
--- a/llvm/test/MC/AArch64/SVE/bic.s
+++ b/llvm/test/MC/AArch64/SVE/bic.s
@@ -90,3 +90,15 @@ bic     z31.d, p7/m, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x1f,0xdb,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 1f db 04 <unknown>
+
+bic     p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: bic     p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xff,0x7d,0x0f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 7d 0f 25 <unknown>
+
+bic     p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: bic     p0.b, p0/z, p0.b, p0.b
+// CHECK-ENCODING: [0x10,0x40,0x00,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 40 00 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/bics-diagnostics.s b/llvm/test/MC/AArch64/SVE/bics-diagnostics.s
new file mode 100644
index 00000000000..e47c291bc0f
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/bics-diagnostics.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+bics p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: bics p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bics p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: bics p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bics p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: bics p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+bics p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: bics p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/bics.s b/llvm/test/MC/AArch64/SVE/bics.s
new file mode 100644
index 00000000000..92447351fa8
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/bics.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+bics    p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: bics    p0.b, p0/z, p0.b, p0.b
+// CHECK-ENCODING: [0x10,0x40,0x40,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 40 40 25 <unknown>
+
+bics    p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: bics    p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xff,0x7d,0x4f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 7d 4f 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/eor-diagnostics.s b/llvm/test/MC/AArch64/SVE/eor-diagnostics.s
index 001bb9128c9..dbed470e7bd 100644
--- a/llvm/test/MC/AArch64/SVE/eor-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/eor-diagnostics.s
@@ -65,3 +65,30 @@ eor z0.d, p8/z, z0.d, z1.d
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
 // CHECK-NEXT: eor z0.d, p8/z, z0.d, z1.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+eor p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: eor p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: eor p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: eor p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+eor p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: eor p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/eor.s b/llvm/test/MC/AArch64/SVE/eor.s
index ff058df4652..8c68ec9c783 100644
--- a/llvm/test/MC/AArch64/SVE/eor.s
+++ b/llvm/test/MC/AArch64/SVE/eor.s
@@ -90,3 +90,21 @@ eor     z31.b, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x1f,0x19,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 1f 19 04 <unknown>
+
+eor     p0.b, p0/z, p0.b, p1.b
+// CHECK-INST: eor     p0.b, p0/z, p0.b, p1.b
+// CHECK-ENCODING: [0x00,0x42,0x01,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 42 01 25 <unknown>
+
+eor     p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: not     p0.b, p0/z, p0.b
+// CHECK-ENCODING: [0x00,0x42,0x00,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 42 00 25 <unknown>
+
+eor     p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: not     p15.b, p15/z, p15.b
+// CHECK-ENCODING: [0xef,0x7f,0x0f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7f 0f 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/eors-diagnostics.s b/llvm/test/MC/AArch64/SVE/eors-diagnostics.s
new file mode 100644
index 00000000000..bc1c19a3166
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/eors-diagnostics.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+eors p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: eors p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eors p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: eors p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eors p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: eors p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+eors p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: eors p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/eors.s b/llvm/test/MC/AArch64/SVE/eors.s
new file mode 100644
index 00000000000..9643cb4a06d
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/eors.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+eors    p0.b, p0/z, p0.b, p1.b
+// CHECK-INST: eors    p0.b, p0/z, p0.b, p1.b
+// CHECK-ENCODING: [0x00,0x42,0x41,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 42 41 25 <unknown>
+
+eors    p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: nots    p0.b, p0/z, p0.b
+// CHECK-ENCODING: [0x00,0x42,0x40,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 42 40 25 <unknown>
+
+eors    p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: nots    p15.b, p15/z, p15.b
+// CHECK-ENCODING: [0xef,0x7f,0x4f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7f 4f 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/mov.s b/llvm/test/MC/AArch64/SVE/mov.s
index 65e2907cb0d..c0a50e39c70 100644
--- a/llvm/test/MC/AArch64/SVE/mov.s
+++ b/llvm/test/MC/AArch64/SVE/mov.s
@@ -636,3 +636,27 @@ mov     z31.d, p15/m, z31.d
 // CHECK-ENCODING: [0xff,0xff,0xff,0x05]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff ff ff 05 <unknown>
+
+mov     p0.b, p0.b
+// CHECK-INST: mov     p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x40,0x80,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 80 25 <unknown>
+
+mov     p15.b, p15.b
+// CHECK-INST: mov     p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0x8f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d 8f 25 <unknown>
+
+mov     p0.b, p0/z, p0.b
+// CHECK-INST: mov     p0.b, p0/z, p0.b
+// CHECK-ENCODING: [0x00,0x40,0x00,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 00 25 <unknown>
+
+mov     p15.b, p15/z, p15.b
+// CHECK-INST: mov     p15.b, p15/z, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0x0f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d 0f 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/movs.s b/llvm/test/MC/AArch64/SVE/movs.s
new file mode 100644
index 00000000000..9ec0320297d
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/movs.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+movs    p0.b, p0.b
+// CHECK-INST: movs    p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x40,0xc0,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 c0 25 <unknown>
+
+movs    p15.b, p15.b
+// CHECK-INST: movs    p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0xcf,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d cf 25 <unknown>
+
+movs    p0.b, p0/z, p0.b
+// CHECK-INST: movs    p0.b, p0/z, p0.b
+// CHECK-ENCODING: [0x00,0x40,0x40,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 40 25 <unknown>
+
+movs    p15.b, p15/z, p15.b
+// CHECK-INST: movs    p15.b, p15/z, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0x4f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d 4f 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/nand-diagnostics.s b/llvm/test/MC/AArch64/SVE/nand-diagnostics.s
new file mode 100644
index 00000000000..5094d9a2461
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/nand-diagnostics.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+nand p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nand p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+nand p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nand p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+nand p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nand p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+nand p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: nand p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/nand.s b/llvm/test/MC/AArch64/SVE/nand.s
new file mode 100644
index 00000000000..c730ab488b4
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/nand.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+nand    p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: nand    p0.b, p0/z, p0.b, p0.b
+// CHECK-ENCODING: [0x10,0x42,0x80,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 42 80 25 <unknown>
+
+nand    p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: nand    p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xff,0x7f,0x8f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 7f 8f 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/nands-diagnostics.s b/llvm/test/MC/AArch64/SVE/nands-diagnostics.s
new file mode 100644
index 00000000000..8897a2aa0d5
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/nands-diagnostics.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+nands p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nands p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+nands p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nands p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+nands p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nands p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+nands p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: nands p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/nands.s b/llvm/test/MC/AArch64/SVE/nands.s
new file mode 100644
index 00000000000..01f019ad491
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/nands.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+nands   p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: nands   p0.b, p0/z, p0.b, p0.b
+// CHECK-ENCODING: [0x10,0x42,0xc0,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 42 c0 25 <unknown>
+
+nands   p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: nands   p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xff,0x7f,0xcf,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 7f cf 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/nor-diagnostics.s b/llvm/test/MC/AArch64/SVE/nor-diagnostics.s
new file mode 100644
index 00000000000..74c60644742
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/nor-diagnostics.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+nor p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nor p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+nor p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nor p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+nor p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nor p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+nor p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: nor p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/nor.s b/llvm/test/MC/AArch64/SVE/nor.s
new file mode 100644
index 00000000000..fdd5c536285
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/nor.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+nor     p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: nor     p0.b, p0/z, p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x42,0x80,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 42 80 25 <unknown>
+
+nor     p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: nor     p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x7f,0x8f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7f 8f 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/nors-diagnostics.s b/llvm/test/MC/AArch64/SVE/nors-diagnostics.s
new file mode 100644
index 00000000000..d08081f1854
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/nors-diagnostics.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+nors p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nors p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+nors p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nors p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+nors p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: nors p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+nors p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: nors p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/nors.s b/llvm/test/MC/AArch64/SVE/nors.s
new file mode 100644
index 00000000000..0de7d1b3b93
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/nors.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+nors    p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: nors    p0.b, p0/z, p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x42,0xc0,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 42 c0 25 <unknown>
+
+nors    p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: nors    p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x7f,0xcf,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7f cf 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/not.s b/llvm/test/MC/AArch64/SVE/not.s
new file mode 100644
index 00000000000..cf1a1472ff2
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/not.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+not     p0.b, p0/z, p0.b
+// CHECK-INST: not     p0.b, p0/z, p0.b
+// CHECK-ENCODING: [0x00,0x42,0x00,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 42 00 25 <unknown>
+
+not     p15.b, p15/z, p15.b
+// CHECK-INST: not     p15.b, p15/z, p15.b
+// CHECK-ENCODING: [0xef,0x7f,0x0f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7f 0f 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/nots.s b/llvm/test/MC/AArch64/SVE/nots.s
new file mode 100644
index 00000000000..833ddf9c94c
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/nots.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+nots    p0.b, p0/z, p0.b
+// CHECK-INST: nots    p0.b, p0/z, p0.b
+// CHECK-ENCODING: [0x00,0x42,0x40,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 42 40 25 <unknown>
+
+nots    p15.b, p15/z, p15.b
+// CHECK-INST: nots    p15.b, p15/z, p15.b
+// CHECK-ENCODING: [0xef,0x7f,0x4f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7f 4f 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/orn-diagnostics.s b/llvm/test/MC/AArch64/SVE/orn-diagnostics.s
index ff9827e6787..d33cf800906 100644
--- a/llvm/test/MC/AArch64/SVE/orn-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/orn-diagnostics.s
@@ -50,3 +50,30 @@ orn z7.d, z8.d, #254
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
 // CHECK-NEXT: orn z7.d, z8.d, #254
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+orn p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orn p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orn p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orn p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orn p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orn p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+orn p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: orn p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/orn.s b/llvm/test/MC/AArch64/SVE/orn.s
index 2a336ed4bfc..89b8ea5795e 100644
--- a/llvm/test/MC/AArch64/SVE/orn.s
+++ b/llvm/test/MC/AArch64/SVE/orn.s
@@ -54,3 +54,15 @@ orn     z0.d, z0.d, #0x6
 // CHECK-ENCODING: [0xa0,0xef,0x03,0x05]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: a0 ef 03 05 <unknown>
+
+orn     p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: orn     p0.b, p0/z, p0.b, p0.b
+// CHECK-ENCODING: [0x10,0x40,0x80,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 40 80 25 <unknown>
+
+orn     p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: orn     p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xff,0x7d,0x8f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 7d 8f 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/orns-diagnostics.s b/llvm/test/MC/AArch64/SVE/orns-diagnostics.s
new file mode 100644
index 00000000000..a7cba7eb4a5
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/orns-diagnostics.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+orns p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orns p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orns p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orns p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orns p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orns p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+orns p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: orns p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/orns.s b/llvm/test/MC/AArch64/SVE/orns.s
new file mode 100644
index 00000000000..e7b81efd1ed
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/orns.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+orns    p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: orns    p0.b, p0/z, p0.b, p0.b
+// CHECK-ENCODING: [0x10,0x40,0xc0,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 40 c0 25 <unknown>
+
+orns    p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: orns    p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xff,0x7d,0xcf,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 7d cf 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/orr-diagnostics.s b/llvm/test/MC/AArch64/SVE/orr-diagnostics.s
index b244d3f09f1..bcea515cc13 100644
--- a/llvm/test/MC/AArch64/SVE/orr-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/orr-diagnostics.s
@@ -65,3 +65,30 @@ orr z0.d, p8/z, z0.d, z1.d
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
 // CHECK-NEXT: orr z0.d, p8/z, z0.d, z1.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+orr p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orr p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orr p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orr p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orr p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orr p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+orr p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: orr p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/orr.s b/llvm/test/MC/AArch64/SVE/orr.s
index f1c8bf761fc..1cf48fdd7a0 100644
--- a/llvm/test/MC/AArch64/SVE/orr.s
+++ b/llvm/test/MC/AArch64/SVE/orr.s
@@ -92,3 +92,21 @@ orr     z31.d, p7/m, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x1f,0xd8,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 1f d8 04 <unknown>
+
+orr     p0.b, p0/z, p0.b, p1.b
+// CHECK-INST: orr     p0.b, p0/z, p0.b, p1.b
+// CHECK-ENCODING: [0x00,0x40,0x81,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 81 25 <unknown>
+
+orr     p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: mov     p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x40,0x80,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 80 25 <unknown>
+
+orr     p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: mov     p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0x8f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d 8f 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/orrs-diagnostics.s b/llvm/test/MC/AArch64/SVE/orrs-diagnostics.s
new file mode 100644
index 00000000000..5d8196e306f
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/orrs-diagnostics.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Predicate register must have .b suffix
+
+orrs p0.h, p0/z, p0.h, p1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orrs p0.h, p0/z, p0.h, p1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orrs p0.s, p0/z, p0.s, p1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orrs p0.s, p0/z, p0.s, p1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orrs p0.d, p0/z, p0.d, p1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: orrs p0.d, p0/z, p0.d, p1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Operation only has zeroing predicate behaviour (p0/z).
+
+orrs p0.b, p0/m, p1.b, p2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: orrs p0.b, p0/m, p1.b, p2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/orrs.s b/llvm/test/MC/AArch64/SVE/orrs.s
new file mode 100644
index 00000000000..0fda5d42228
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/orrs.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+orrs    p0.b, p0/z, p0.b, p1.b
+// CHECK-INST: orrs    p0.b, p0/z, p0.b, p1.b
+// CHECK-ENCODING: [0x00,0x40,0xc1,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 c1 25 <unknown>
+
+orrs    p0.b, p0/z, p0.b, p0.b
+// CHECK-INST: movs    p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x40,0xc0,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 c0 25 <unknown>
+
+orrs    p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: movs    p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0xcf,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d cf 25 <unknown>