summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
* [analyzer] Do not crash on callback for call_once passed by valueGeorge Karpenkov2018-05-162-10/+22
| | | | | | | | | https://bugs.llvm.org/show_bug.cgi?id=37312 rdar://40270582 Differential Revision: https://reviews.llvm.org/D46913 llvm-svn: 332422
* Revert commits r332160, r332164, r332236.Douglas Yung2018-05-164-24/+0
| | | | | | It was decided this is the wrong approach to fix this issue. llvm-svn: 332421
* ARM: Remove unnecessary argument. NFCI.Peter Collingbourne2018-05-162-6/+3
| | | | | | IsLittleEndian is already a field of ARMAsmBackend. llvm-svn: 332420
* ARM: Deduplicate code and remove unnecessary declaration. NFCI.Peter Collingbourne2018-05-163-47/+11
| | | | llvm-svn: 332419
* [Debugify] Fix test failing after r332416Anastasis Grammenos2018-05-161-1/+1
| | | | | | | | I missed a test that needed an update. Failing bot: http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/30071 llvm-svn: 332418
* [analyzer] Make plist-html diagnostic consumer produce multi-file reports.Artem Dergachev2018-05-163-1/+209
| | | | | | | | | | | Previously plist-html output produced multi-file HTML reports but only single-file Plist reports. Change plist-html output to produce multi-file Plist reports as well. Differential Revision: https://reviews.llvm.org/D46902 llvm-svn: 332417
* [Debugfiy] Print the pass name next to the resultAnastasis Grammenos2018-05-155-27/+38
| | | | | | | | CheckDebugify now prints the pass name right next to the result of the check. Differential Revision: https://reviews.llvm.org/D46908 llvm-svn: 332416
* [MachineOutliner] Add optsize markings to outlined functions.Eli Friedman2018-05-152-1/+11
| | | | | | | | | It doesn't matter much this late in the pipeline, but one place that does check for it is the function alignment code. Differential Revision: https://reviews.llvm.org/D46373 llvm-svn: 332415
* [libunwind][MIPS] Support MIPS floating-point registers for hard-float ABIs.John Baldwin2018-05-156-27/+439
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For MIPS ABIs with 64-bit floating point registers including newabi and O32 with 64-bit floating point registers, just save and restore the 32 floating-point registers as doubles. For O32 MIPS with 32-bit floating-point registers, save and restore the individual floating-point registers as "plain" registers. These registers are encoded as floats rather than doubles, but the DWARF unwinder assumes that floating-point registers are stored as doubles when reading them from memory (via AddressSpace::getDouble()). Treating the registers as "normal" registers instead causes the DWARF unwinder to fetch them from memory as a 32-bit register. This does mean that for O32 with 32-bit floating-point registers unw_get_fpreg() and unw_set_fpreg() do not work. One would have to use unw_get_reg() and unw_set_reg() instead. However, DWARF unwinding works correctly as the DWARF CFI emits records for individual 32-bit floating-point registers even when they are treated as doubles stored in paired registers. If the lack of unw_get/set_fpreg() becomes a pressing need in the future for O32 MIPS we could add in special handling to make it work. Reviewers: sdardis, compnerd Reviewed By: sdardis Differential Revision: https://reviews.llvm.org/D41968 llvm-svn: 332414
* Emit an error when include <atomic> after <stdatomic.h>Volodymyr Sapsai2018-05-151-0/+3
| | | | | | | | | | | | | | | | | | | | | C11 defines `kill_dependency` as a macro in <stdatomic.h>. When you include <atomic> after <stdatomic.h>, the macro clashes with `std::kill_dependency` and causes multiple errors. Explicit error should help in diagnosing those errors. No change for working code that includes <atomic> before <stdatomic.h>. rdar://problem/27435938 Reviewers: rsmith, EricWF, mclow.lists, jfb Reviewed By: jfb Subscribers: jfb, jkorous-apple, christof, bumblebritches57, JonChesterfield, smeenai, cfe-commits Differential Revision: https://reviews.llvm.org/D45470 llvm-svn: 332413
* [WebAssembly] Fix R_WEBASSEMBLY_FUNCTION_OFFSET_I32 relocation entriesSam Clegg2018-05-152-15/+5
| | | | | | | | | | | | | | | | | Fixes: lld: warning: unexpected existing value for R_WEBASSEMBLY_FUNCTION_OFFSET_I32: existing=839 expected=838 The existing solution is trying to erroneously recover correct offset of the function code from the body (which is not a function segment that includes its size, locals, and code). The D46763 is trying to maintain the offset of the function code allowing properly calculate the new relocation entry. Patch by Yury Delendik Differential Revision: https://reviews.llvm.org/D46765 llvm-svn: 332412
* [Attr] Don't print implicit attributesJoel E. Denny2018-05-152-6/+23
| | | | | | | | | | | | Fixes bug reported at: http://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20180514/228390.html Reviewed by: aaron.ballman Differential Revision: https://reviews.llvm.org/D46894 llvm-svn: 332411
* [X86][SSE] Add tests for vector rotates by splat variable.Simon Pilgrim2018-05-153-0/+1525
| | | | llvm-svn: 332410
* [AMDGPU] Fix handling of void types in isLegalAddressingModeStanislav Mekhanoshin2018-05-152-1/+38
| | | | | | | | | | | | | It is legal for the type passed to isLegalAddressingMode to be unsized or, more specifically, VoidTy. In this case, we must check the legality of load / stores for all legal types. Directly trying to call getTypeStoreSize is incorrect, and leads to breakage in e.g. Loop Strength Reduction. This change guards against that behaviour. Differential Revision: https://reviews.llvm.org/D40405 llvm-svn: 332409
* [lld] Make helpers static. NFC.Benjamin Kramer2018-05-154-5/+7
| | | | llvm-svn: 332408
* [InstCombine] fix binop (shuffle X), C --> shuffle (binop X, C') to check usesSanjay Patel2018-05-152-5/+4
| | | | llvm-svn: 332407
* [WebAssembly] Provide WasmFunction content offset information.Sam Clegg2018-05-152-0/+2
| | | | | | | | | | | | | WasmObjectWriter mostly operates with function segments offsets that do not include their size fields. WasmObjectFile needs to have and provide this information to the lld to maintain proper R_WEBASSEMBLY_FUNCTION_OFFSET_I32 relocations entries. Patch by Yury Delendik Differential Revision: https://reviews.llvm.org/D46763 llvm-svn: 332406
* [Documentation] Fix Release Notes format issues.Eugene Zelenko2018-05-151-7/+8
| | | | llvm-svn: 332405
* AMDGPU: Add a missing test for the 128-bit local addr space optionMarek Olsak2018-05-151-0/+20
| | | | | | | This should have been pushed with: "AMDGPU: enable 128-bit for local addr space under an option" llvm-svn: 332404
* StructurizeCFG: fix inverting conditionsMarek Olsak2018-05-152-2/+33
| | | | | | | | | | | | | | | | Author: Samuel Pitoiset Without this patch, it appears to me that we are selecting the wrong operand when inverting conditions. In the attached test, it will select %tmp3 instead of %tmp4. To fix it, just use 'A' as everywhere. This fixes a regression introduced by "[PatternMatch] define m_Not using m_Xor and cst_pred_ty" https://reviews.llvm.org/D46351 llvm-svn: 332403
* [msan] Instrument masked.store, masked.load intrinsics.Evgeniy Stepanov2018-05-152-0/+211
| | | | | | | | | | | | Summary: Instrument masked store/load intrinsics. Reviewers: kcc Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D46785 llvm-svn: 332402
* Don't produce a redundant "auto type is incompatible with C++98" on every ↵Richard Smith2018-05-152-1/+5
| | | | | | | | lambda with no explicit return type. We already warned about the lambda, and we don't have a source location for the imagined "auto" anyway. llvm-svn: 332401
* Move helper classes into anonymous namespaces. NFCI.Benjamin Kramer2018-05-154-8/+11
| | | | llvm-svn: 332400
* [InstCombine] clean up code for binop-shuffle transforms; NFCISanjay Patel2018-05-151-39/+34
| | | | llvm-svn: 332399
* [MinGW] Handle the GNU ld option -Map for outputting a linker mapMartin Storsjo2018-05-153-0/+10
| | | | | | Differential Revision: https://reviews.llvm.org/D46872 llvm-svn: 332398
* Address post-commit review comments after r328731. NFC.Akira Hatanaka2018-05-157-113/+95
| | | | | | | | | | | | | | | | | | | | | | - Define a function (canPassInRegisters) that determines whether a record can be passed in registers based on language rules and target-specific ABI rules. - Set flag RecordDecl::ParamDestroyedInCallee to true in MSVC mode and remove ASTContext::isParamDestroyedInCallee, which is no longer needed. - Use the same type (unsigned) for RecordDecl's bit-field members. For more background, see the following discussions that took place on cfe-commits. http://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20180326/223498.html http://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20180402/223688.html http://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20180409/224754.html http://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20180423/226494.html http://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20180507/227647.html llvm-svn: 332397
* [llvm-objcopy] Add --only-keep-debug as a noopJake Ehrlich2018-05-153-0/+24
| | | | | | | | | | | | | | | | | | | This option just keeps being a problem and really needs to be implemented in some fashion. Implementing it properly requires some kind of "replaceSectionReference" method because all the existing links need to be maintained. The desired behavior is just for allocated sections to become NOBITS but actually implementing that is rather tricky due to the current design of llvm-objcopy. However converting allocated sections to NOBITS is just an optimization and not something debuggers need. Debuggers can debug a stripped executable and take an unstripped executable for that stripped executable as input. Additionally allocated sections account for a very small part of debug binaries so this optimization is quite small. I propose that for the time being we implement this as a NOP so that people can use llvm-objcopy where they need to, just in a sub-optimal way. This option has already blocked a lot of people and its currently blocking me. llvm-svn: 332396
* [AArch64] Improve single vector lane unscaled storesEvandro Menezes2018-05-153-55/+92
| | | | | | | | | | When storing the 0th lane of a vector, use a simpler and usually more efficient scalar store instead. In this case, also using the unscaled offset. Differential revision: https://reviews.llvm.org/D46762 llvm-svn: 332394
* [InstCombine] add more tests for binop-shuffle; NFCSanjay Patel2018-05-151-5/+58
| | | | | | | The splat pattern is part of PR37463: https://bugs.llvm.org/show_bug.cgi?id=37463 llvm-svn: 332393
* [DAGCombine] Move load checks on store of loads into candidateNirav Dave2018-05-151-15/+13
| | | | | | | | | | search. NFCI. Migrate single-use and non-volatility, non-indexed requirements on stores of immediate store values to candidate collection pass from later stage. llvm-svn: 332392
* Nios2: Unbreak build.Peter Collingbourne2018-05-152-5/+6
| | | | llvm-svn: 332391
* [llvm-mca] Introduce a pipeline Stage class and FetchStage.Matt Davis2018-05-1510-39/+216
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is just an idea, really two ideas. I expect some push-back, but I realize that posting a diff is the most comprehensive way to express these concepts. This patch introduces a Stage class which represents the various stages of an instruction pipeline. As a start, I have created a simple FetchStage that is based on existing logic for how MCA produces instructions, but now encapsulated in a Stage. The idea should become more concrete once we introduce additional stages. The idea being, that when a stage completes, the next stage in the pipeline will be executed. Stages are chained together as a singly linked list to closely model a real pipeline. For now there is only one stage, so the stage-to-stage flow of instructions isn't immediately obvious. Eventually, Stage will also handle event notifications, but that functionality is not complete, and not destined for this patch. Ideally, an interested party can register for notifications from a particular stage. Callbacks will be issued to these listeners at various points in the execution of the stage. For now, eventing functionality remains similar to what it has been in mca::Backend. We will be building-up the Stage class as we move on, such as adding debug output. This patch also removes the unique_ptr<Instruction> return value from InstrBuilder::createInstruction. An Instruction pointer is still produced, but now it's up to the caller to decide how that item should be managed post-allocation (e.g., smart pointer). This allows the Fetch stage to create instructions and manage the lifetime of those instructions as it wishes, and not have to be bound to any specific managed pointer type. Other callers of createInstruction might have different requirements, and thus can manage the pointer to fit their needs. Another idea would be to push the ownership to the RCU. Currently, the FetchStage will wrap the Instruction pointer in a shared_ptr. This allows us to remove the Instruction container in Backend, which was probably going to disappear, or move, at some point anyways. Note that I did run these changes through valgrind, to make sure we are not leaking memory. While the shared_ptr comes with some additional overhead it relieves us from having to manage a list of generated instructions, and/or make lookup calls to remove the instructions. I realize that both the Stage class and the Instruction pointer management (mentioned directly above) are separate but related ideas, and probably should land as separate patches; I am happy to do that if either idea is decent. The main reason these two ideas are together is that Stage::execute() can mutate an InstRef. For the fetch stage, the InstRef is populated as the primary action of that stage (execute()). I didn't want to change the Stage interface to support the idea of generating an instruction. Ideally, instructions are to be pushed through the pipeline. I didn't want to draw too much of a specialization just for the fetch stage. Excuse the word-salad. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb Subscribers: llvm-commits, mgorny, javed.absar, tschuett, gbedwell Differential Revision: https://reviews.llvm.org/D46741 llvm-svn: 332390
* [x86][eflags] Fix PR37431 by teaching the EFLAGS copy lowering toChandler Carruth2018-05-153-3/+272
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | specially handle SETB_C* pseudo instructions. Summary: While the logic here is somewhat similar to the arithmetic lowering, it is different enough that it made sense to have its own function. I actually tried a bunch of different optimizations here and none worked well so I gave up and just always do the arithmetic based lowering. Looking at code from the PR test case, we actually pessimize a bunch of code when generating these. Because SETB_C* pseudo instructions clobber EFLAGS, we end up creating a bunch of copies of EFLAGS to feed multiple SETB_C* pseudos from a single set of EFLAGS. This in turn causes the lowering code to ruin all the clever code generation that SETB_C* was hoping to achieve. None of this is needed. Whenever we're generating multiple SETB_C* instructions from a single set of EFLAGS we should instead generate a single maximally wide one and extract subregs for all the different desired widths. That would result in substantially better code generation. But this patch doesn't attempt to address that. The test case from the PR is included as well as more directed testing of the specific lowering pattern used for these pseudos. Reviewers: craig.topper Subscribers: sanjoy, mcrosier, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D46799 llvm-svn: 332389
* Use perfect forwarding to deduplicate code in unit test. NFC.Benjamin Kramer2018-05-151-22/+2
| | | | llvm-svn: 332388
* AMDGPU: Fix v_dot{4, 8}* instruction encodingKonstantin Zhuravlyov2018-05-154-20/+525
| | | | | | Differential Revision: https://reviews.llvm.org/D46848 llvm-svn: 332387
* [llvm-rc] Add support for the optional CLASS statement for dialogsMartin Storsjo2018-05-159-3/+71
| | | | | | Differential Revision: https://reviews.llvm.org/D46875 llvm-svn: 332386
* [MemorySSA] Don't sort IDF blocks.Michael Zolotukhin2018-05-159-89/+79
| | | | | | | | | | | | | | | | Summary: After r332167 we started to sort the IDF blocks inside IDF calculation, so there is no need to re-sort them on the user site. The test changes are due to a slightly different order we're using now (originally we used DFSInNumber and now the blocks are sorted by a pair (LevelFromRoot, DFSInNumber)). Reviewers: dberlin, mgrang Subscribers: Prazek, hiraditya, george.burgess.iv, llvm-commits Differential Revision: https://reviews.llvm.org/D46899 llvm-svn: 332385
* Fixed some rtti-options tests.Sunil Srivastava2018-05-151-3/+3
| | | | | | | | | | | | Certain tests in rtti-options.cpp are not really testing anything because they are testing for the absence of -frtti option to the cc1 process. Since the cc1 process does not take -frtti option, these tests are passing tautologically. The RTTI mode is enabled by default in cc1, and -fno-rtti disables it. Therefore the correct way to check for enabling of RTTI is to check for the absence of -fno-rtti to cc1, and the correct way to check for disabling of RTTI is to check for the presence of -fno-rtti to cc1. This patch fixes those tests. Differential Revision: https://reviews.llvm.org/D46836 llvm-svn: 332384
* [Hexagon] Add driver options for subtarget featuresKrzysztof Parzyszek2018-05-154-5/+47
| | | | llvm-svn: 332383
* add AR to acronyms of clang-tidy property checkYan Zhang2018-05-151-0/+1
| | | | | | | | | | | | Reviewers: hokein, benhamilton Reviewed By: benhamilton Subscribers: klimek, cfe-commits Differential Revision: https://reviews.llvm.org/D46895 llvm-svn: 332382
* [llvm-mca] use a formatted_raw_ostream to insert padding and get rid of ↵Andrea Di Biagio2018-05-153-92/+76
| | | | | | tabs. NFC llvm-svn: 332381
* [OPENMP, NVPTX] Do not globalize variables with reference/pointer types.Alexey Bataev2018-05-156-62/+42
| | | | | | | | In generic data-sharing mode we do not need to globalize variables/parameters of reference/pointer types. They already are placed in the global memory. llvm-svn: 332380
* AMDGPU/GlobalISel: Implement select() for G_FCONSTANTTom Stellard2018-05-153-21/+114
| | | | | | | | | | | | Summary: Also clean up G_CONSTANT selection. Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D46170 llvm-svn: 332379
* [clangd] Extract scoring/ranking logic, and shave yaks.Sam McCall2018-05-1512-224/+589
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Code completion scoring was embedded in CodeComplete.cpp, which is bad: - awkward to test. The mechanisms (extracting info from index/sema) can be unit-tested well, the policy (scoring) should be quantitatively measured. Neither was easily possible, and debugging was hard. The intermediate signal struct makes this easier. - hard to reuse. This is a bug in workspaceSymbols: it just presents the results in the index order, which is not sorted in practice, it needs to rank them! Also, index implementations care about scoring (both query-dependent and independent) in order to truncate result lists appropriately. The main yak shaved here is the build() function that had 3 variants across unit tests is unified in TestTU.h (rather than adding a 4th variant). Reviewers: ilya-biryukov Subscribers: klimek, mgorny, ioeric, MaskRay, jkorous, mgrang, cfe-commits Differential Revision: https://reviews.llvm.org/D46524 llvm-svn: 332378
* AMDGPU: Add disasm tests for deep learning instructions + fix v_fmac_f32 disasmKonstantin Zhuravlyov2018-05-152-1/+975
| | | | | | Differential Revision: https://reviews.llvm.org/D46853 llvm-svn: 332377
* [X86] Split WriteCvtF2F into F32->F64 and F64->F32 scheduler classesSimon Pilgrim2018-05-1516-156/+201
| | | | | | | | BtVer2 - Fixes schedules for (V)CVTPS2PD instructions A lot of the Intel models still have too many InstRW overrides for these new classes - this needs cleaning up but I wanted to get the classes in first llvm-svn: 332376
* [InstCombine] fix binop-of-shuffles to check usesSanjay Patel2018-05-152-16/+13
| | | | llvm-svn: 332375
* [lld] Mitigate relocation overflow [part 1 of 2].Han Shen2018-05-1559-321/+376
| | | | | | | | | | | This CL places .dynsym and .dynstr at the beginning of SHF_ALLOC sections. We do this to mitigate the possibility that huge .dynsym and .dynstr sections placed between ro-data and text sections cause relocation overflow. Differential Revision: https://reviews.llvm.org/D45788 llvm-svn: 332374
* [InstCombine] add multi-use shuffle tests and regenerate checks; NFCSanjay Patel2018-05-151-141/+196
| | | | llvm-svn: 332373
* Remove \brief commands from doxygen comments.Fangrui Song2018-05-1514-78/+78
| | | | | | | | | | | | Summary: This is similar to D46290 D46320. Reviewers: ruiu, grimar Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D46861 llvm-svn: 332372
OpenPOWER on IntegriCloud