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* [SLPVectorizer] Move isOneOf after InstructionsState type. NFCI.Simon Pilgrim2018-06-201-71/+71
| | | | | | A future patch will have isOneOf use InstructionsState. llvm-svn: 335142
* [DAG] Don't map a TableId to itself in the ReplacedValues mapBjorn Pettersson2018-06-203-3/+23
| | | | | | | | | | | | | | | | | Summary: Found some regressions (infinite loop in DAGTypeLegalizer::RemapId) after r334880. This patch makes sure that we do map a TableId to itself. Reviewers: niravd Reviewed By: niravd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D48364 llvm-svn: 335141
* [ELF][MIPS] Fill a primary-GOT as much as possibleSimon Atanasyan2018-06-202-34/+28
| | | | | | | | | While building a Global Offset Table try to fill the primary GOT as much as possible because the primary GOT can be accessed in the most effective way. If it is not possible, try to fill the last GOT in the multi-GOT list, and finally create a new GOT if both attempts failed. llvm-svn: 335140
* Simplify. No behavior change.Nico Weber2018-06-201-7/+1
| | | | llvm-svn: 335139
* minor: fixed typo in debug printAndrey Churbanov2018-06-201-1/+1
| | | | llvm-svn: 335138
* [DAG] Fix and-mask folding when narrowing loads.Nirav Dave2018-06-202-2/+28
| | | | | | | | | | | | | | | | Summary: Check that and masks are strictly smaller than implicit mask from narrowed load. Fixes PR37820. Reviewers: samparker, RKSimon, nemanjai Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D48335 llvm-svn: 335137
* [LIT] Enable testing of LLVM gold plugin on Mac OS XEugene Leviant2018-06-208-3/+9
| | | | | | Differential revision: https://reviews.llvm.org/D48350 llvm-svn: 335136
* [WebAssembly] Update know failures for the wasm waterfallSam Clegg2018-06-201-7/+2
| | | | | | | | | | | | Summary: The waterfall no longer builds .s files and no longers uses the wasm-o when it builds object files. Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48371 llvm-svn: 335135
* [SLPVectorizer] Use InstructionsState to record AltOpcodeSimon Pilgrim2018-06-201-72/+73
| | | | | | | | | | | | This is part of a move towards generalizing the alternate opcode mechanism and not just supporting (F)Add/(F)Sub counterparts. The patch embeds the AltOpcode in the InstructionsState instead of calling getAltOpcode so often. I'm hoping to eventually remove all uses of getAltOpcode and handle alternate opcode selection entirely within getSameOpcode, that will require us to use InstructionsState throughout the BoUpSLP call hierarchy (similar to some of the changes in D28907), which I will begin in future patches. Differential Revision: https://reviews.llvm.org/D48359 llvm-svn: 335134
* Fix-up for r335123: Set default apple_platform to "osx".Kuba Mracek2018-06-201-1/+1
| | | | llvm-svn: 335133
* Make sure TestNumThreads works with libc++Pavel Labath2018-06-202-2/+6
| | | | | | | | | | | | | | | | The problem was that with libc++ the std::unique_lock declaration was completely inlined, so there was no line table entry in the main.cpp file to set a breakpoint on. Therefore, the breakpoint got moved to the next line, but that meant the test would deadlock as the thread would stop with the lock already held. I fix that issue by adding a dummy statement before the std::unique_lock line to anchor the breakpoint. I think this should fix the issue because of which this test was disabled on darwin, but someone should verify that before enabling it. llvm-svn: 335132
* [llvm-mca] use APint::operator[] to obtain the bit value. NFCAndrea Di Biagio2018-06-201-4/+2
| | | | llvm-svn: 335131
* [SLPVectorizer] Relax "alternate" opcode vectorisation to work with any ↵Simon Pilgrim2018-06-203-45/+47
| | | | | | | | | | | | | | SK_Select shuffle pattern D47985 saw the old SK_Alternate 'alternating' shuffle mask replaced with the SK_Select mask which accepts either input operand for each lane, equivalent to a vector select with a constant condition operand. This patch updates SLPVectorizer to make full use of this SK_Select shuffle pattern by removing the 'isOdd()' limitation. The AArch64 regression will be fixed by D48172. Differential Revision: https://reviews.llvm.org/D48174 llvm-svn: 335130
* [InstSimplify] Fix missed optimization in simplifyUnsignedRangeCheck()Sanjay Patel2018-06-202-19/+7
| | | | | | | | | | | | | | | | | | | | | For both operands are unsigned, the following optimizations are valid, and missing: 1. X > Y && X != 0 --> X > Y 2. X > Y || X != 0 --> X != 0 3. X <= Y || X != 0 --> true 4. X <= Y || X == 0 --> X <= Y 5. X > Y && X == 0 --> false unsigned foo(unsigned x, unsigned y) { return x > y && x != 0; } should fold to x > y, but I found we haven't done it right now. besides, unsigned foo(unsigned x, unsigned y) { return x < y && y != 0; } Has been folded to x < y, so there may be a bug. Patch by: Li Jia He! Differential Revision: https://reviews.llvm.org/D47922 llvm-svn: 335129
* [InstSimplify] Add tests for missed optimizations in ↵Sanjay Patel2018-06-201-2/+67
| | | | | | | | | | | | simplifyUnsignedRangeCheck (NFC) These are the baseline tests for the functional change in D47922. Patch by Li Jia He! Differential Revision: https://reviews.llvm.org/D48000 llvm-svn: 335128
* [RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d}Alex Bradbury2018-06-204-0/+28
| | | | | | | These are produced by GCC and supported by GAS, but not currently contained in the pseudoinstruction listing in the RISC-V ISA manual. llvm-svn: 335127
* [X86] Adding a test for PR37879Mikhail Dvoretckii2018-06-201-0/+11
| | | | llvm-svn: 335126
* [ADT] Allow llvm::hash_code as DenseMap key.Sam McCall2018-06-201-0/+7
| | | | | | | | | | | | | | Summary: This is useful when hash collisions are unlikely and acceptable, e.g. in clangd completion ranking. Reviewers: ioeric Subscribers: ilya-biryukov, llvm-commits Differential Revision: https://reviews.llvm.org/D48361 llvm-svn: 335125
* [Hexagon] Remove 'T' from HasVNN predicates, NFCKrzysztof Parzyszek2018-06-2014-258/+258
| | | | | | Patch by Sumanth Gundapaneni. llvm-svn: 335124
* [sanitizer] Unify and generalize Apple platforms in CMake and lit test configsKuba Mracek2018-06-2012-47/+68
| | | | | | | | There's more platforms than just "ios" and "iossim" that we should support, and adding more lit config variables for each platform isn't great. Let's generalize and have a single value that determines what the platform under test is. Differential Revision: https://reviews.llvm.org/D48309 llvm-svn: 335123
* [mips] Fix the predicates of some DSP instructions from AdditionalPredicates ↵Simon Dardis2018-06-203-8/+8
| | | | | | | | | | to ASEPredicate Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D48166 llvm-svn: 335122
* [InstCombine] ignore debuginfo when removing redundant assumes (PR37726)Sanjay Patel2018-06-202-6/+7
| | | | | | | | | | This is similar to: rL335083 Fixes:: https://bugs.llvm.org/show_bug.cgi?id=37726 llvm-svn: 335121
* [RISCV] Add InstAlias definitions for sgt and sgtuAlex Bradbury2018-06-202-0/+12
| | | | | | | These are produced by GCC and supported by GAS, but not currently contained in the pseudoinstruction listing in the RISC-V ISA manual. llvm-svn: 335120
* ARM: convert ORR instructions to ADD where possible on Thumb.Tim Northover2018-06-207-4/+84
| | | | | | | | | | | | Thumb has more 16-bit encoding space dedicated to ADD than ORR, allowing both a 3-address encoding and a wider range of immediates. So, particularly when optimizing for code size (but it doesn't make things worse elsewhere) it's beneficial to select an OR operation to an ADD if we know overflow won't occur. This is made even better by LLVM's penchant for putting operations in canonical form by converting the other way. llvm-svn: 335119
* [AArch64] Implement FLT_ROUNDS macro.Tim Northover2018-06-205-0/+59
| | | | | | | | | | Very similar to ARM implementation, just maps to an MRS. Should fix PR25191. Patch by Michael Brase. llvm-svn: 335118
* [llvm-exegesis] Add mechanism to add target-specific passes.Clement Courbet2018-06-206-6/+33
| | | | | | | | | | | | | | Summary: createX86FloatingPointStackifierPass is disabled until we handle TracksLiveness correctly. Reviewers: gchatelet Subscribers: mgorny, tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D48360 llvm-svn: 335117
* [analyzer] Optimize constraint generation when the range is a concrete valueMikhail R. Gadelha2018-06-201-52/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: If a constraint is something like: ``` $0 = [1,1] ``` it'll now be created as: ``` assert($0 == 1) ``` instead of: ``` assert($0 >= 1 && $0 <= 1) ``` In general, ~3% speedup when solving per query in my machine. Biggest improvement was when verifying sqlite3, total time went down from 3000s to 2200s. I couldn't create a test for this as there is no way to dump the formula yet. D48221 adds a method to dump the formula but there is no way to do it from the command line. Also, a test that prints the formula will most likely fail in the future, as different solvers print the formula in different formats. Reviewers: NoQ, george.karpenkov, ddcc Reviewed By: george.karpenkov Subscribers: xazax.hun, szepet, a.sidorin Differential Revision: https://reviews.llvm.org/D48227 llvm-svn: 335116
* [llvm-exegesis] Fix failing test.Guillaume Chatelet2018-06-201-2/+4
| | | | | | | | | | Reviewers: courbet Subscribers: tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D48358 llvm-svn: 335115
* IRInterpreter: fix sign extension of small types (pr37840)Pavel Labath2018-06-202-7/+9
| | | | | | | | | | | | | Sign-extension of small types (e.g. short) was not handled correctly. The reason for that was that when we were assigning the a value to the Scalar object, we would accidentally promote the type to int (even though the assignment code in AssignTypeToMatch tried to cast the value to the appropriate type, it would still invoke the "int" version of operator=). Instead, I use the APInt version of operator=, where the bitwidth is specified explicitly. Among other things, this allows us to fold the individual size cases into one. llvm-svn: 335114
* [llvm-mca][X86] Teach how to identify register writes that implicitly clear ↵Andrea Di Biagio2018-06-2015-201/+326
| | | | | | | | | | | | | | | | | | | | | | | | | | | | the upper portion of a super-register. This patch teaches llvm-mca how to identify register writes that implicitly zero the upper portion of a super-register. On X86-64, a general purpose register is implemented in hardware as a 64-bit register. Quoting the Intel 64 Software Developer's Manual: "an update to the lower 32 bits of a 64 bit integer register is architecturally defined to zero extend the upper 32 bits". Also, a write to an XMM register performed by an AVX instruction implicitly zeroes the upper 128 bits of the aliasing YMM register. This patch adds a new method named clearsSuperRegisters to the MCInstrAnalysis interface to help identify instructions that implicitly clear the upper portion of a super-register. The rest of the patch teaches llvm-mca how to use that new method to obtain the information, and update the register dependencies accordingly. I compared the kernels from tests clear-super-register-1.s and clear-super-register-2.s against the output from perf on btver2. Previously there was a large discrepancy between the estimated IPC and the measured IPC. Now the differences are mostly in the noise. Differential Revision: https://reviews.llvm.org/D48225 llvm-svn: 335113
* Fix compilation with mingw-w64 (pr37873)Pavel Labath2018-06-201-2/+2
| | | | llvm-svn: 335112
* [SPIR] Prevent SPIR targets from using half conversion intrinsicsSjoerd Meijer2018-06-202-0/+151
| | | | | | | | | | | | | | | | | | | | | The SPIR target currently allows for half precision floating point types to be emitted using the LLVM intrinsic functions which convert half types to floats and doubles. However, this is illegal in SPIR as the only intrinsic allowed by SPIR is memcpy, as per section 3 of the SPIR specification. Currently this is leading to an assert being hit in the Clang CodeGen when attempting to emit a constant or literal _Float16 type in a comparison operation on a SPIR or SPIR64 target. This assert stems from the CodeGen attempting to emit a constant half value as an integer because the backend has specified that it is using these half conversion intrinsics (which represents half as i16). This patch prevents SPIR targets from using these intrinsics by overloading the responsible target info method, marks SPIR targets as having a legal half type and provides additional regression testing for the _Float16 type on SPIR targets. Patch by: Stephen McGroarty Differential Revision: https://reviews.llvm.org/D48188 llvm-svn: 335111
* [SLPVectorizer] Split Tree/Reduction cost calls to simplify debugging. NFCI.Simon Pilgrim2018-06-201-2/+3
| | | | llvm-svn: 335110
* [llvm-exegesis] Remove noexcept in r335105.Clement Courbet2018-06-202-7/+8
| | | | | | gcc checks for transitivity (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53903) llvm-svn: 335109
* [llvm-exegesis] Fix missing move in r335105.Clement Courbet2018-06-202-6/+6
| | | | llvm-svn: 335108
* [Support] Add missing includes of <system_error> for std::error_codeMartin Storsjo2018-06-202-0/+2
| | | | | | | | | | This fixes compilation with MinGW after SVN r333798, which added a few functions within _WIN32 ifdefs, functions returning std::error_code. Include everything that is needed instead of hoping that this header being inclued transitively (which it apparently is in MSVC builds). llvm-svn: 335107
* Fix windows build broken by r335104Pavel Labath2018-06-201-0/+8
| | | | | | | lldb-python.h needs to be included first to work around some incompatibilities between windows and python headers. llvm-svn: 335106
* [llvm-exegesis] Use a Prototype to defer picking a value for free vars.Guillaume Chatelet2018-06-209-170/+228
| | | | | | | | | | | | Summary: Introducing a Prototype object to capture Variables that must be set but keeps degrees of freedom as Invalid. This allows exploring non constraint variables later on. Reviewers: courbet Subscribers: tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D48316 llvm-svn: 335105
* Remove dependency from Host to pythonPavel Labath2018-06-2012-137/+87
| | | | | | | | | | | | | | | | Summary: The only reason python was used in the Host module was to compute the python path. I resolve this the same way as D47384 did for clang, by moving the path computation into the python plugin and modifying SBHostOS class to call into this module for ePathTypePythonDir. Reviewers: zturner, jingham, davide Subscribers: mgorny, lldb-commits Differential Revision: https://reviews.llvm.org/D48215 llvm-svn: 335104
* [Sema] Allow creating types with multiple of the same addrspace.Alexey Bader2018-06-204-17/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The comment with the OpenCL clause about this clearly says: "No type shall be qualified by qualifiers for two or more different address spaces." This must mean that two or more qualifiers for the _same_ address space is allowed. However, it is likely unintended by the programmer, so emit a warning. For dependent address space types, reject them like before since we cannot know what the address space will be. Patch by Bevin Hansson (ebevhan). Reviewers: Anastasia Reviewed By: Anastasia Subscribers: bader, cfe-commits Differential Revision: https://reviews.llvm.org/D47630 llvm-svn: 335103
* BreakpointIDList: Use llvm::ArrayRef instead of pointer+length pairPavel Labath2018-06-203-9/+7
| | | | | | NFC llvm-svn: 335102
* [NFC][SCEV] Add tests related to bit masking (PR37793)Roman Lebedev2018-06-207-5/+553
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Related to https://bugs.llvm.org/show_bug.cgi?id=37793, https://reviews.llvm.org/D46760#1127287 We'd like to do this canonicalization https://rise4fun.com/Alive/Gmc But it is currently restricted by rL155136 / rL155362, which says: ``` // This is a constant shift of a constant shift. Be careful about hiding // shl instructions behind bit masks. They are used to represent multiplies // by a constant, and it is important that simple arithmetic expressions // are still recognizable by scalar evolution. // // The transforms applied to shl are very similar to the transforms applied // to mul by constant. We can be more aggressive about optimizing right // shifts. // // Combinations of right and left shifts will still be optimized in // DAGCombine where scalar evolution no longer applies. ``` I think these tests show that for *constants*, SCEV has no issues with that canonicalization. Reviewers: mkazantsev, spatel, efriedma, sanjoy Reviewed By: mkazantsev Subscribers: sanjoy, javed.absar, llvm-commits, stoklund, bixia Differential Revision: https://reviews.llvm.org/D48229 llvm-svn: 335101
* [PatternMatch] Add m_Store pattern match helperSjoerd Meijer2018-06-202-0/+63
| | | | | | Differential Revision: https://reviews.llvm.org/D48279 llvm-svn: 335100
* [X86][Znver1] Specify Register Files, RCU; FP scheduler capacity.Roman Lebedev2018-06-203-1/+37
| | | | | | | | | | | | | | | | | | | | | | | Summary: First off: i do not have any access to that processor, so this is purely theoretical, no benchmarks. I have been looking into b**d**ver2 scheduling profile, and while cross-referencing the existing b**t**ver2, znver1 profiles, and the reference docs (`Software Optimization Guide for AMD Family {15,16,17}h Processors`), i have noticed that only b**t**ver2 scheduling profile specifies these. Also, there is no mca test coverage. Reviewers: RKSimon, craig.topper, courbet, GGanesh, andreadb Reviewed By: GGanesh Subscribers: gbedwell, vprasad, ddibyend, shivaram, Ashutosh, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D47676 llvm-svn: 335099
* [X86] Fix r335097Clement Courbet2018-06-201-1/+5
| | | | | | Missed `Generic` test in llvm-mca. llvm-svn: 335098
* [X86] Add sched class WriteLAHFSAHF and fix values.Clement Courbet2018-06-2022-35/+112
| | | | | | | | | | | | | | | Summary: I ran llvm-exegesis on SKX, SKL, BDW, HSW, SNB. Atom is from Agner and SLM is a guess. I've left AMD processors alone. Reviewers: RKSimon, craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D48079 llvm-svn: 335097
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-06-206-43/+43
| | | | llvm-svn: 335096
* [DAGCombiner] Add some comments to some true/false arguments to make it ↵Craig Topper2018-06-201-2/+2
| | | | | | obvious what they are. NFC llvm-svn: 335095
* [X86] Remove a fptosi from the test_mm512_mask_reduce_max_pd fast-isel test.Craig Topper2018-06-201-10/+5
| | | | | | | | The clang test inadvertently turned a floating point value into a double by having the wrong return type on the test function relative to the intrinsic it was testing. This resulted in an extra fptosi instruction that propagated into this test when I copied the clang output. llvm-svn: 335094
* [SelectionDAG] Don't crash on inline assembly errors when the inline ↵Craig Topper2018-06-202-2/+28
| | | | | | | | | | | | | | | | | | | | | | | | | assembly return type is a struct. Summary: If we get an error building the SelectionDAG for inline assembly we try to continue and still build the DAG. But if the return type for the inline assembly is a struct we end up crashing because we try to create an UNDEF node with a struct type which isn't valid. Instead we need to create an UNDEF for each element of the struct and join them with merge_values. This patch relies on single operand merge_values being handled gracefully by getMergeValues. If the return type is void there will be no VTs returned by ComputeValueVTs and now we just return instead of calling setValue. Hopefully that's ok, I assumed nothing would need to look up the mapped value for void node. Fixes PR37359 Reviewers: rengolin, rovka, echristo, efriedma, bogner Reviewed By: efriedma Subscribers: craig.topper, llvm-commits Differential Revision: https://reviews.llvm.org/D46560 llvm-svn: 335093
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