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* [X86][SSE] Regenerate fp2int/int2fp testsSimon Pilgrim2018-01-272-101/+1621
| | | | | | Cleanup check prefixes and check full codegen llvm-svn: 323591
* Attempt to make the PS4 build bot happy.Gabor Horvath2018-01-271-2/+2
| | | | llvm-svn: 323590
* [ASTImporter] Add support to import some AST nodes:Gabor Horvath2018-01-272-23/+200
| | | | | | | | | | | | | | | | * CXXOperatorCallExpr * SizeOfPackExpr * DependentTemplateSpecializationType * DependentSizedArray * CXXTypeidExpr * Fix importing CXXTemporaryObjectExpr Some of the changes are based on https://github.com/haoNoQ/clang/blob/summary-ipa-draft/lib/AST/ASTImporter.cpp Differential Revision: https://reviews.llvm.org/D42335 llvm-svn: 323589
* Regenerate test results for and-su.ll . NFCAmaury Sechet2018-01-271-7/+38
| | | | llvm-svn: 323588
* [X86][SSE] Add broadcast from v2i32 memory tests (PR34394)Simon Pilgrim2018-01-271-0/+98
| | | | llvm-svn: 323587
* Remove unused class declarationsJan Kratochvil2018-01-272-6/+0
| | | | | | | | Simplification by removing excessive DWARFCompileUnit references for D40466 . Differential revision: https://reviews.llvm.org/D42613 llvm-svn: 323586
* [TargetLowering] Teach TargetLowering::SimplifySetCC to simplify setcc of ↵Craig Topper2018-01-274-96/+90
| | | | | | | | vXi1 vectors into logic ops. This transform was already being done for setcc of scalar i1. This extends it to vectors. llvm-svn: 323585
* [ELF] - Extend lto/asmundef.ll testcase.George Rimar2018-01-272-1/+6
| | | | | | | | | | | Patch adds one more module with non-prevailing version of asm symbol, defined in main module This is for D42107, which is under review. Extended version of testcase would fail with the diff 9 version of patch posted. llvm-svn: 323584
* [SelectionDAG] Make DAGTypeLegalizer::PromoteSetCCOperands handle ↵Craig Topper2018-01-272-22/+8
| | | | | | | | SETEQ/SETNE correctly for vector types. The code was using getValueSizeInBits and combining with the result of a call to DAG.ComputeNumSignBits. But for vector types getValueSizeInBits returns the width of the full vector while ComputeNumSignBits is going to give a number no larger than the width of a single element. So we should be using getScalarValueSizeInBits to get the element width. llvm-svn: 323583
* [GlobalISel][Legalizer] Convert the FP constants to the right APFloat type ↵Amara Emerson2018-01-272-2/+19
| | | | | | | | | | | for G_FCONSTANT. We weren't converting the immediate ConstantFP during legalization, which caused the wrong bit patterns to be emitted for half type FP constants. Fixes PR36106. llvm-svn: 323582
* Revert "[SLP] Fix for PR32086: Count InsertElementInstr of the same elements ↵Alexey Bataev2018-01-274-393/+155
| | | | | | | | as shuffle." This reverts commit r323530 to fix possible problems in users code. llvm-svn: 323581
* Revert "[SLP] Removed the warning about unused variable, NFC."Alexey Bataev2018-01-271-1/+1
| | | | | | This reverts commit r323533 to fix possible problems in users code. llvm-svn: 323580
* Add the /order option.Rui Ueyama2018-01-277-0/+304
| | | | | | | | | | | | With the /order option, you can give an order file. An order file contains symbol names, one per line, and the linker places comdat sections in that given order. The option is used often to optimize an output binary for (in particular, startup) speed by improving locality. Differential Revision: https://reviews.llvm.org/D42598 llvm-svn: 323579
* [CodeGen] Use the non-virtual alignment when emitting the baseAkira Hatanaka2018-01-272-1/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | constructor. Previously, clang would emit an over-aligned (16-byte) store to initialize B::x in B's base constructor when compiling the following code: struct A { __attribute__((aligned(16))) double data1; }; struct B : public virtual A { B() : x(123) {} double a; int x; }; struct C : public virtual B {}; void test() { B b; C c; } This was happening because the code in IRGen that does member initialization was using the alignment of a complete object instead of the non-virtual alignment. This commit fixes the bug. rdar://problem/36382481 Differential Revision: https://reviews.llvm.org/D42521 llvm-svn: 323578
* Always allow "#pragma region".Matt Davis2018-01-272-2/+9
| | | | | | | | | | | | | | | | | | | | | Summary: Both MS and PS4 targets are capable of recognizing the existence of: #pragma region, #pragma endregion. Since this pragma is only a hint for certain editors, and has no logic, it seems helpful to permit this pragma in all cases, not just MS compatibility mode. Reviewers: rnk, rsmith, majnemer Reviewed By: majnemer Subscribers: Quuxplusone, probinson, majnemer, cfe-commits Differential Revision: https://reviews.llvm.org/D42248 llvm-svn: 323577
* [InstrProfiling] Don't exit early when an unused intrinsic is foundVedant Kumar2018-01-272-3/+21
| | | | | | This fixes a think-o in r323574. llvm-svn: 323576
* [LangRef] Update out-of-date instrprof namesVedant Kumar2018-01-261-15/+15
| | | | llvm-svn: 323575
* [InstrProfiling] Improve compile time when there is no workVedant Kumar2018-01-261-2/+21
| | | | | | | When there are no uses of profiling intrinsics in a module, and there's no coverage data to lower, InstrProfiling has no work to do. llvm-svn: 323574
* update_mir_test_checks: Accept "." in function namesJustin Bogner2018-01-261-1/+1
| | | | llvm-svn: 323573
* [X86] Use vpternlog to implement vector not under AVX512.Craig Topper2018-01-267-246/+516
| | | | | | | | Previously we had to materialize all 1s in a register using vpternlog or pcmpeq and then xor with that. By using vpternlog directly we can do it in one operation. This is implemented using isel patterns, but we should maybe consider creating a generalized vpternlog combiner. llvm-svn: 323572
* [x86] auto-generate complete checks; NFCSanjay Patel2018-01-263-93/+443
| | | | llvm-svn: 323571
* [InstCombine] Preserve debug values for eliminable castsVedant Kumar2018-01-263-1/+37
| | | | | | | | | | | | | | | | | A cast from A to B is eliminable if its result is casted to C, and if the pair of casts could just be expressed as a single cast. E.g here, %c1 is eliminable: %c1 = zext i16 %A to i32 %c2 = sext i32 %c1 to i64 InstCombine optimizes away eliminable casts. This patch teaches it to insert a dbg.value intrinsic pointing to the final result, so that local variables pointing to the eliminable result are preserved. Differential Revision: https://reviews.llvm.org/D42566 llvm-svn: 323570
* Inline variable only used within assert.Richard Trieu2018-01-261-2/+1
| | | | llvm-svn: 323569
* [Hexagon] Generate constant splats instead of loads from constant poolKrzysztof Parzyszek2018-01-264-27/+67
| | | | llvm-svn: 323568
* [lldbtestsuite] Don't crash on `None` input for is_exe().Davide Italiano2018-01-261-0/+2
| | | | | | | | Now the function returns `False`, and the caller can take the appropriate action (in this case, for --executable, reporting that the file doesn't exist). llvm-svn: 323566
* [DWARF] Temporarily removing test to make buildbots happy while investigating.Wolfgang Pieb2018-01-261-122/+0
| | | | llvm-svn: 323564
* Fix the BinaryPredicate form of std::is_permutation to not rely on operator==Peter Collingbourne2018-01-262-2/+34
| | | | | | | | | | | | | | | | According to [1], forms 2 and 4 of std::is_permutation should use the passed in binary predicate to compare elements. operator== should only be used for forms 1 and 3 which do not take a binary predicate. This CL fixes forms 2 and 4 which relied on operator== for some comparisons. [1] http://en.cppreference.com/w/cpp/algorithm/is_permutation Patch by Thomas Anderson! Differential Revision: https://reviews.llvm.org/D42518 llvm-svn: 323563
* [Hexagon] Make sure that offset on globals matches alignment requirementsKrzysztof Parzyszek2018-01-262-14/+72
| | | | | | | | | | | | | A correctly aligned address may happen to be separated into a variable part and a constant part, where the constant part does not match the alignment needed in a load/store that uses this address. Such a constant cannot be used as an immediate offset in an indexed instruction. When lowering a global address, make sure that if there is an offset folded into the global, the offset is valid for all uses in load/store instructions. llvm-svn: 323562
* [Hexagon] Replace multiple vector extracts with store-load combinationsKrzysztof Parzyszek2018-01-264-0/+202
| | | | llvm-svn: 323561
* [DWARF] Temporarily removing a test that caused an independent failure on ↵Wolfgang Pieb2018-01-261-159/+0
| | | | | | | | the mingw target. Will recommit once that is addressed. llvm-svn: 323560
* [LivePhysRegs] Preserve pristine regs in blocks with no successors.Eli Friedman2018-01-262-2/+49
| | | | | | | | | | | | | | | One common source of blocks with no successors is calls to noreturn functions; we want to preserve pristine registers in case they throw an exception. The whole pristine register thing is messy (we should really prefer to explicitly model registers), but this fills a hole in the model for now. Fixes https://bugs.llvm.org/show_bug.cgi?id=36073. Differential Revision: https://reviews.llvm.org/D42509 llvm-svn: 323559
* [Support] Move PrintEscapedString into the library its declaration is inBenjamin Kramer2018-01-262-10/+10
| | | | llvm-svn: 323558
* [X86] Unbreak the build.Benjamin Kramer2018-01-261-1/+2
| | | | | | | | X86ISelLowering.cpp:34130:5: error: return type 'llvm::SDValue' must match previous return type 'const llvm::SDValue' when lambda expression has unspecified explicit return type llvm-svn: 323557
* [SLP] Test for trunc vectorization, NFC.Alexey Bataev2018-01-261-0/+33
| | | | llvm-svn: 323556
* [X86] Allow any_extend to be combined with setcc on VLX targets.Craig Topper2018-01-262-22/+18
| | | | | | For VLX target getSetccResultType returns vXi1 which prevents the target independent DAG combine from doing this tranform itself. llvm-svn: 323555
* Try to unbreak 32 bit builds after r323528.Benjamin Kramer2018-01-261-3/+6
| | | | llvm-svn: 323554
* [X86][AVX512] Add combining support for X86ISD::VTRUNCSSimon Pilgrim2018-01-262-40/+56
| | | | | | | | Similar to the existing support for X86ISD::VTRUNCUS. Differential Revision: https://reviews.llvm.org/D42544 llvm-svn: 323553
* [X86] Add 'rdrnd' feature to silvermont to match recent gcc bug fix.Craig Topper2018-01-262-1/+3
| | | | | | gcc recently fixed this bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83546 llvm-svn: 323552
* [SelectionDAGISel] Add a debug print before call to Select. Adjust where ↵Craig Topper2018-01-2612-44/+5
| | | | | | | | | | | | blank lines are printed during isel process to make things more sensibly grouped. Previously some targets printed their own message at the start of Select to indicate what they were selecting. For the targets that didn't, it means there was no print of the root node before any custom handling in the target executed. So if the target did something custom and never called SelectNodeCommon, no print would be made. For the targets that did print a message in Select, if they didn't custom handle a node SelectNodeCommon would reprint the root node before walking the isel table. It seems better to just print the message before the call to Select so all targets behave the same. And then remove the root node printing from SelectNodeCommon and just leave a message that says we're starting the table search. There were also some oddities in blank line behavior. Usually due to a \n after a call to SelectionDAGNode::dump which already inserted a new line. llvm-svn: 323551
* [X86] Add 'rdrnd' feature to silvermont to match recent gcc bug fix.Craig Topper2018-01-261-0/+1
| | | | | | gcc recently fixed this bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83546 llvm-svn: 323550
* [index] Fix crash when indexing a C++14 PCH/module related to ↵Argyrios Kyrtzidis2018-01-263-3/+25
| | | | | | | | | | | | | TemplateTemplateParmDecls of alias templates TemplateTemplateParmDecls of alias templates ended-up serialized as 'file-level decls' which was causing a crash while trying to index a PCH/module file that contained them. Commit makes sure TemplateTemplateParmDecls are not recorded as such kind of decls. Fixes crash of rdar://36608297 Differential Revision: https://reviews.llvm.org/D42588 llvm-svn: 323549
* [Hexagon] Fix an incorrect assertion in HexagonConstExtendersKrzysztof Parzyszek2018-01-262-8/+68
| | | | llvm-svn: 323548
* AST: support protocol conformances on id/class/interfaces in MS ABISaleem Abdulrasool2018-01-262-3/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for mangling ObjC protocol conformances in MS ABI as if they are COM interfaces. By diverging from the itanium mangling of `objc_protocol` prefixed names, this approach allows for a semi-reasonable, albeit of questionable sanity, undecoration via existing tooling. There is also the possibility of adding an extension and taking part of the namespace to add the conformance via the `L` and `Z` "modifiers", but the existing tooling would not be able to properly undecorated the symbol even though incidentally `undname` currently produces something legible while wine's implementation is not able to cope with the extension. This allows for the disambiguation of overloads where the parameter differs only in the protocol conformance of the ObjC type, e.g. ``` @protocol P; void f(std::vector<id>); void f(std::vector<id<P>>); ``` which clang would previously fail due to the mangling being identical as the protocol conformance was ignored. llvm-svn: 323547
* [DWARF] Generate DWARF v5 string offsets tables along with strx* index forms.Wolfgang Pieb2018-01-2612-38/+755
| | | | | | | | | | | | Summary: This is the producer side for DWARF v5 string offsets tables. The reader/consumer side was committed with r321295. All compile and type units in a module share a contribution to the string offsets table. Indirect strings use the strx{1,2,3,4} index forms. Reviewers: dblaikie, aprantl, JDevliegehere Differential Revision: https://reviews.llvm.org/D42021 llvm-svn: 323546
* [x86] fix typo in comment; NFCSanjay Patel2018-01-261-1/+1
| | | | llvm-svn: 323545
* [NFC] Remove apostrophe to use 'it' in the possessive form.Matt Davis2018-01-261-1/+1
| | | | | | | | | | Summary: This is a simple change to test commit access with. Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42586 llvm-svn: 323544
* [X86] Define __IBT__ when -mibt is specified.Craig Topper2018-01-262-2/+8
| | | | llvm-svn: 323543
* [X86][AVX] LowerBUILD_VECTORAsVariablePermute - add support for VPERMILPV to ↵Simon Pilgrim2018-01-262-26/+9
| | | | | | | | v4i32/v4f32 Extension to D42431, adding support for v4i32/v4f32 as well as v2i64/v2f64 now that D42308 has landed llvm-svn: 323542
* [X86][SSE] Don't colaesce v4i32 extractsSimon Pilgrim2018-01-267-427/+254
| | | | | | | | | | We currently coalesce v4i32 extracts from all 4 elements to 2 v2i64 extracts + shifts/sign-extends. This seems to have been added back in the days when we tended to spill vectors and reload scalars, or ended up with repeated shuffles moving everything down to 0'th index. I don't think either of these are likely these days as we have better EXTRACT_VECTOR_ELT and VECTOR_SHUFFLE handling, and the existing code tends to make it very difficult for various vector and load combines. Differential Revision: https://reviews.llvm.org/D42308 llvm-svn: 323541
* [X86][SSE] Drop PMADDWD in lowerMulSimon Pilgrim2018-01-261-7/+0
| | | | | | As mentioned in D42258, we don't need this any more llvm-svn: 323540
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