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* Add a missing check, which broke a bunch of vector tests.Chris Lattner2006-04-031-3/+6
| | | | llvm-svn: 27374
* shrinkify intrinsics more by using some local classesChris Lattner2006-04-031-60/+32
| | | | llvm-svn: 27373
* Add the full set of min/max instructionsChris Lattner2006-04-031-6/+14
| | | | llvm-svn: 27372
* Add some classes to make it easier to define intrinsics. Add min/max ↵Chris Lattner2006-04-031-45/+87
| | | | | | intrinsics. llvm-svn: 27371
* support x * (c1 + c2) where c1 and c2 are pow2s. special case for c2 == 4Andrew Lenharth2006-04-032-10/+32
| | | | llvm-svn: 27370
* test powers of 2Andrew Lenharth2006-04-031-0/+18
| | | | llvm-svn: 27369
* mul by const conversion sequences. more coming soonAndrew Lenharth2006-04-033-2/+61
| | | | llvm-svn: 27368
* back this outAndrew Lenharth2006-04-031-25/+0
| | | | llvm-svn: 27367
* test some more mul by constant removalAndrew Lenharth2006-04-031-2/+13
| | | | llvm-svn: 27366
* Make sure mul by constant 5 is turned into a s4addqAndrew Lenharth2006-04-021-0/+16
| | | | llvm-svn: 27365
* This should be a win of every archAndrew Lenharth2006-04-021-1/+26
| | | | llvm-svn: 27364
* This makes McCat/12-IOtest go 8x faster or soAndrew Lenharth2006-04-021-2/+14
| | | | llvm-svn: 27363
* This will be needed soonAndrew Lenharth2006-04-021-1/+146
| | | | llvm-svn: 27362
* For PR722:Reid Spencer2006-04-021-4/+4
| | | | | | | | | | Change the check for llvm-gcc from using LLVMGCCDIR to LLVMGCC. This checks for the actual tool rather than the directory in which the tool resides. In the case of this bug, it is possible that the directory exists but that the tools in that directory do not. This fix should avoid the makefile from erroneously proceeding without the actual tools being available. llvm-svn: 27361
* add a noteChris Lattner2006-04-021-0/+9
| | | | llvm-svn: 27360
* Inform the dag combiner that the predicate compares only return a low bit.Chris Lattner2006-04-022-1/+39
| | | | llvm-svn: 27359
* relax assertionChris Lattner2006-04-021-1/+4
| | | | llvm-svn: 27358
* Allow targets to compute masked bits for intrinsics.Chris Lattner2006-04-021-4/+9
| | | | llvm-svn: 27357
* Add a little dag combine to compile this:Chris Lattner2006-04-021-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | int %AreSecondAndThirdElementsBothNegative(<4 x float>* %in) { entry: %tmp1 = load <4 x float>* %in ; <<4 x float>> [#uses=1] %tmp = tail call int %llvm.ppc.altivec.vcmpgefp.p( int 1, <4 x float> < float 0x7FF8000000000000, float 0.000000e+00, float 0.000000e+00, float 0x7FF8000000000000 >, <4 x float> %tmp1 ) ; <int> [#uses=1] %tmp = seteq int %tmp, 0 ; <bool> [#uses=1] %tmp3 = cast bool %tmp to int ; <int> [#uses=1] ret int %tmp3 } into this: _AreSecondAndThirdElementsBothNegative: mfspr r2, 256 oris r4, r2, 49152 mtspr 256, r4 li r4, lo16(LCPI1_0) lis r5, ha16(LCPI1_0) lvx v0, 0, r3 lvx v1, r5, r4 vcmpgefp. v0, v1, v0 mfcr r3, 2 rlwinm r3, r3, 27, 31, 31 mtspr 256, r2 blr instead of this: _AreSecondAndThirdElementsBothNegative: mfspr r2, 256 oris r4, r2, 49152 mtspr 256, r4 li r4, lo16(LCPI1_0) lis r5, ha16(LCPI1_0) lvx v0, 0, r3 lvx v1, r5, r4 vcmpgefp. v0, v1, v0 mfcr r3, 2 rlwinm r3, r3, 27, 31, 31 xori r3, r3, 1 cntlzw r3, r3 srwi r3, r3, 5 mtspr 256, r2 blr llvm-svn: 27356
* vector casts of casts are eliminable. Transform this:Chris Lattner2006-04-021-0/+4
| | | | | | | | | | | %tmp = cast <4 x uint> %tmp to <4 x int> ; <<4 x int>> [#uses=1] %tmp = cast <4 x int> %tmp to <4 x float> ; <<4 x float>> [#uses=1] into: %tmp = cast <4 x uint> %tmp to <4 x float> ; <<4 x float>> [#uses=1] llvm-svn: 27355
* vector casts never reinterpret bitsChris Lattner2006-04-021-0/+5
| | | | llvm-svn: 27354
* Allow transforming this:Chris Lattner2006-04-021-2/+4
| | | | | | | | | | | | %tmp = cast <4 x uint>* %testData to <4 x int>* ; <<4 x int>*> [#uses=1] %tmp = load <4 x int>* %tmp ; <<4 x int>> [#uses=1] to this: %tmp = load <4 x uint>* %testData ; <<4 x uint>> [#uses=1] %tmp = cast <4 x uint> %tmp to <4 x int> ; <<4 x int>> [#uses=1] llvm-svn: 27353
* Turn altivec lvx/stvx intrinsics into loads and stores. This allows theChris Lattner2006-04-021-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | elimination of one load from this: int AreSecondAndThirdElementsBothNegative( vector float *in ) { #define QNaN 0x7FC00000 const vector unsigned int testData = (vector unsigned int)( QNaN, 0, 0, QNaN ); vector float test = vec_ld( 0, (float*) &testData ); return ! vec_any_ge( test, *in ); } Now generating: _AreSecondAndThirdElementsBothNegative: mfspr r2, 256 oris r4, r2, 49152 mtspr 256, r4 li r4, lo16(LCPI1_0) lis r5, ha16(LCPI1_0) addi r6, r1, -16 lvx v0, r5, r4 stvx v0, 0, r6 lvx v1, 0, r3 vcmpgefp. v0, v0, v1 mfcr r3, 2 rlwinm r3, r3, 27, 31, 31 xori r3, r3, 1 cntlzw r3, r3 srwi r3, r3, 5 mtspr 256, r2 blr llvm-svn: 27352
* Remove done itemChris Lattner2006-04-021-5/+0
| | | | llvm-svn: 27351
* Fix tablegen related dependencies in Visual Studio.Jeff Cohen2006-04-022-10/+27
| | | | llvm-svn: 27350
* Implement promotion for EXTRACT_VECTOR_ELT, allowing v16i8 multiplies to ↵Chris Lattner2006-04-021-16/+27
| | | | | | work with PowerPC. llvm-svn: 27349
* add a noteChris Lattner2006-04-021-0/+11
| | | | llvm-svn: 27348
* Implement the Expand action for binary vector operations to break the binopChris Lattner2006-04-021-1/+18
| | | | | | | into elements and operate on each piece. This allows generic vector integer multiplies to work on PPC, though the generated code is horrible. llvm-svn: 27347
* Intrinsics that just load from memory can be treated like loads: they don'tChris Lattner2006-04-021-4/+25
| | | | | | | have to serialize against each other. This allows us to schedule lvx's across each other, for example. llvm-svn: 27346
* Adjust the Intrinsics.gen interface a little bitChris Lattner2006-04-021-2/+2
| | | | llvm-svn: 27345
* Adjust to change in Intrinsics.gen interface.Chris Lattner2006-04-021-0/+1
| | | | llvm-svn: 27344
* Constant fold all of the vector binops. This allows us to compile this:Chris Lattner2006-04-021-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "vector unsigned char mergeLowHigh = (vector unsigned char) ( 8, 9, 10, 11, 16, 17, 18, 19, 12, 13, 14, 15, 20, 21, 22, 23 ); vector unsigned char mergeHighLow = vec_xor( mergeLowHigh, vec_splat_u8(8));" aka: void %test2(<16 x sbyte>* %P) { store <16 x sbyte> cast (<4 x int> xor (<4 x int> cast (<16 x ubyte> < ubyte 8, ubyte 9, ubyte 10, ubyte 11, ubyte 16, ubyte 17, ubyte 18, ubyte 19, ubyte 12, ubyte 13, ubyte 14, ubyte 15, ubyte 20, ubyte 21, ubyte 22, ubyte 23 > to <4 x int>), <4 x int> cast (<16 x sbyte> < sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8 > to <4 x int>)) to <16 x sbyte>), <16 x sbyte> * %P ret void } into this: _test2: mfspr r2, 256 oris r4, r2, 32768 mtspr 256, r4 li r4, lo16(LCPI2_0) lis r5, ha16(LCPI2_0) lvx v0, r5, r4 stvx v0, 0, r3 mtspr 256, r2 blr instead of this: _test2: mfspr r2, 256 oris r4, r2, 49152 mtspr 256, r4 li r4, lo16(LCPI2_0) lis r5, ha16(LCPI2_0) vspltisb v0, 8 lvx v1, r5, r4 vxor v0, v1, v0 stvx v0, 0, r3 mtspr 256, r2 blr ... which occurs here: http://developer.apple.com/hardware/ve/calcspeed.html llvm-svn: 27343
* Add a new -view-legalize-dags command line optionChris Lattner2006-04-022-3/+13
| | | | llvm-svn: 27342
* Implement constant folding of bit_convert of arbitrary constant ↵Chris Lattner2006-04-021-2/+139
| | | | | | vbuild_vector nodes. llvm-svn: 27341
* These entries already existChris Lattner2006-04-021-4/+0
| | | | llvm-svn: 27340
* Add some missing node namesChris Lattner2006-04-021-0/+9
| | | | llvm-svn: 27339
* simplify this methodChris Lattner2006-04-021-3/+1
| | | | llvm-svn: 27338
* New noteChris Lattner2006-04-021-0/+6
| | | | llvm-svn: 27337
* Constant fold casts from things like <4 x int> -> <4 x uint>, likewise int<->fp.Chris Lattner2006-04-021-0/+108
| | | | llvm-svn: 27336
* Custom lower all BUILD_VECTOR's so that we can compile vec_splat_u8(8) intoChris Lattner2006-04-021-0/+2
| | | | | | "vspltisb v0, 8" instead of a constant pool load. llvm-svn: 27335
* Prefer larger register classes over smaller ones when a register occurs inChris Lattner2006-04-021-7/+21
| | | | | | multiple register classes. This fixes PowerPC/2006-04-01-FloatDoubleExtend.ll llvm-svn: 27334
* New testcase that crashes the compiler.Chris Lattner2006-04-021-0/+7
| | | | llvm-svn: 27333
* add valuemapper support for inline asmChris Lattner2006-04-011-1/+1
| | | | llvm-svn: 27332
* Implement vnot using VNOR instead of using 'vspltisb v0, -1' and vxorChris Lattner2006-04-011-0/+4
| | | | llvm-svn: 27331
* Fix InstCombine/2006-04-01-InfLoop.llChris Lattner2006-04-011-1/+2
| | | | llvm-svn: 27330
* New testcase that caused instcombine to infinitely loop (with my recentChris Lattner2006-04-011-0/+441
| | | | | | patch), distilled from Applications/JM/ldecod llvm-svn: 27329
* Fold A^(B&A) -> (B&A)^AChris Lattner2006-04-011-7/+46
| | | | | | | | Fold (B&A)^A == ~B & A This implements InstCombine/xor.ll:test2[56] llvm-svn: 27328
* new testcasesChris Lattner2006-04-011-0/+15
| | | | llvm-svn: 27327
* Fix Transforms/IndVarsSimplify/2006-03-31-NegativeStride.ll andChris Lattner2006-04-013-39/+39
| | | | | | | PR726 by performing consistent signed division, not consistent unsigned division when evaluating scev's. Do not touch udivs. llvm-svn: 27326
* new testcase for PR726Chris Lattner2006-04-011-0/+21
| | | | llvm-svn: 27325
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