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| author | Andrew Lenharth <andrewl@lenharth.org> | 2006-04-02 21:08:39 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2006-04-02 21:08:39 +0000 |
| commit | 444bdb069abca004ce91ca469b0b3db84730d7e5 (patch) | |
| tree | 431110ea96263fefe2cbee19bf1e819c73cad6a9 | |
| parent | 01bd5523a3234d891ec38a918c5a8afd5a02ad49 (diff) | |
| download | bcm5719-llvm-444bdb069abca004ce91ca469b0b3db84730d7e5.tar.gz bcm5719-llvm-444bdb069abca004ce91ca469b0b3db84730d7e5.zip | |
This makes McCat/12-IOtest go 8x faster or so
llvm-svn: 27363
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelLowering.cpp | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp index 3eb38e64516..b1111a6a826 100644 --- a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp @@ -585,10 +585,22 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64)); } - case ISD::SDIV: - case ISD::UDIV: case ISD::UREM: case ISD::SREM: + //Expand only on constant case + if (Op.getOperand(1).getOpcode() == ISD::Constant) { + MVT::ValueType VT = Op.Val->getValueType(0); + unsigned Opc = Op.Val->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV; + SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ? + BuildUDIVSequence(Op, &DAG) : + BuildSDIVSequence(Op, &DAG); + Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1)); + Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1); + return Tmp1; + } + //fall through + case ISD::SDIV: + case ISD::UDIV: if (MVT::isInteger(Op.getValueType())) { const char* opstr = 0; switch(Op.getOpcode()) { |

