diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/include/llvm/CodeGen/MIRYamlMapping.h | 2 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/MIRPrinter.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/merge-m0.mir | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/compactbranches/empty-block.mir | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Thumb2/tbb-removeadd.mir | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/GlobalISel/irtranslator-call.ll | 1 | ||||
| -rw-r--r-- | llvm/test/DebugInfo/MIR/X86/empty-inline.mir | 1 |
10 files changed, 0 insertions, 14 deletions
diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h index 47b40de6fe1..30e88fe38ac 100644 --- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h +++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h @@ -381,7 +381,6 @@ struct MachineFunction { StringRef Name; unsigned Alignment = 0; bool ExposesReturnsTwice = false; - bool NoVRegs; // GISel MachineFunctionProperties. bool Legalized = false; bool RegBankSelected = false; @@ -406,7 +405,6 @@ template <> struct MappingTraits<MachineFunction> { YamlIO.mapRequired("name", MF.Name); YamlIO.mapOptional("alignment", MF.Alignment); YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice); - YamlIO.mapOptional("noVRegs", MF.NoVRegs); YamlIO.mapOptional("legalized", MF.Legalized); YamlIO.mapOptional("regBankSelected", MF.RegBankSelected); YamlIO.mapOptional("selected", MF.Selected); diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp index bd04acd049d..ff12297e3fc 100644 --- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp @@ -332,8 +332,6 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) { MF.setAlignment(YamlMF.Alignment); MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice); - if (YamlMF.NoVRegs) - MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs); if (YamlMF.Legalized) MF.getProperties().set(MachineFunctionProperties::Property::Legalized); if (YamlMF.RegBankSelected) diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index 6f6a67d81b0..293fc7358b8 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -183,8 +183,6 @@ void MIRPrinter::print(const MachineFunction &MF) { YamlMF.Alignment = MF.getAlignment(); YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice(); - YamlMF.NoVRegs = MF.getProperties().hasProperty( - MachineFunctionProperties::Property::NoVRegs); YamlMF.Legalized = MF.getProperties().hasProperty( MachineFunctionProperties::Property::Legalized); YamlMF.RegBankSelected = MF.getProperties().hasProperty( diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir index 96436209451..c35d1719f84 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir @@ -13,7 +13,6 @@ name: main alignment: 2 exposesReturnsTwice: false -noVRegs: false legalized: true regBankSelected: true selected: false diff --git a/llvm/test/CodeGen/AMDGPU/merge-m0.mir b/llvm/test/CodeGen/AMDGPU/merge-m0.mir index 064db49924e..720642ad1dd 100644 --- a/llvm/test/CodeGen/AMDGPU/merge-m0.mir +++ b/llvm/test/CodeGen/AMDGPU/merge-m0.mir @@ -50,7 +50,6 @@ name: test alignment: 0 exposesReturnsTwice: false -noVRegs: false legalized: false regBankSelected: false selected: false diff --git a/llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir b/llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir index 0e9bc42565f..6577ef84867 100644 --- a/llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir +++ b/llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir @@ -190,7 +190,6 @@ name: foo alignment: 1 exposesReturnsTwice: false -noVRegs: true legalized: false regBankSelected: false selected: false @@ -289,7 +288,6 @@ body: | name: bar alignment: 1 exposesReturnsTwice: false -noVRegs: true legalized: false regBankSelected: false selected: false diff --git a/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir b/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir index 7831e51e315..7fb1afae912 100644 --- a/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir +++ b/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir @@ -39,7 +39,6 @@ name: l5 alignment: 2 exposesReturnsTwice: false -noVRegs: true legalized: false regBankSelected: false selected: false diff --git a/llvm/test/CodeGen/Thumb2/tbb-removeadd.mir b/llvm/test/CodeGen/Thumb2/tbb-removeadd.mir index 89ed9872053..10606679134 100644 --- a/llvm/test/CodeGen/Thumb2/tbb-removeadd.mir +++ b/llvm/test/CodeGen/Thumb2/tbb-removeadd.mir @@ -39,7 +39,6 @@ name: Func alignment: 1 exposesReturnsTwice: false -noVRegs: true legalized: false regBankSelected: false selected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/irtranslator-call.ll b/llvm/test/CodeGen/X86/GlobalISel/irtranslator-call.ll index bc394f6e156..6c60aed67a7 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/irtranslator-call.ll +++ b/llvm/test/CodeGen/X86/GlobalISel/irtranslator-call.ll @@ -5,7 +5,6 @@ define void @test_void_return() { ; CHECK-LABEL: name: test_void_return ; CHECK: alignment: 4 ; CHECK-NEXT: exposesReturnsTwice: false -; CHECK-NEXT: noVRegs: false ; CHECK-NEXT: legalized: false ; CHECK-NEXT: regBankSelected: false ; CHECK-NEXT: selected: false diff --git a/llvm/test/DebugInfo/MIR/X86/empty-inline.mir b/llvm/test/DebugInfo/MIR/X86/empty-inline.mir index 1766a8f4461..71d10fe9de9 100644 --- a/llvm/test/DebugInfo/MIR/X86/empty-inline.mir +++ b/llvm/test/DebugInfo/MIR/X86/empty-inline.mir @@ -73,7 +73,6 @@ name: _ZN1C5m_fn3Ev alignment: 4 exposesReturnsTwice: false -noVRegs: true legalized: false regBankSelected: false selected: false |
