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-rw-r--r--llvm/lib/Target/ARM/ARMSubtarget.cpp2
-rw-r--r--llvm/lib/Target/ARM/ARMTargetMachine.cpp5
-rw-r--r--llvm/test/CodeGen/ARM/no-arm-mode.ll21
3 files changed, 26 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 29d6d148d91..a52c723053c 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -138,8 +138,6 @@ ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
: (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
TLInfo(TM, *this) {
- assert((isThumb() || hasARMOps()) &&
- "Target must either be thumb or support ARM operations!");
ARMGISelActualAccessor *GISel = new ARMGISelActualAccessor();
GISel->CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index d68ffa2313c..3d7bcf9f013 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -272,7 +272,12 @@ ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
// function that reside in TargetOptions.
resetTargetOptions(F);
I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
+
+ if (!I->isThumb() && !I->hasARMOps())
+ F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
+ "instructions, but the target does not support ARM mode execution.");
}
+
return I.get();
}
diff --git a/llvm/test/CodeGen/ARM/no-arm-mode.ll b/llvm/test/CodeGen/ARM/no-arm-mode.ll
new file mode 100644
index 00000000000..6e22e646f4e
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/no-arm-mode.ll
@@ -0,0 +1,21 @@
+; RUN: not llc -mtriple=armv7-windows-itanium -mcpu=cortex-a9 -o /dev/null %s 2>&1 \
+; RUN: | FileCheck %s -check-prefixes=CHECK-OPTIONS,CHECK-FEATURE
+
+; RUN: not llc -mtriple=thumb-unknown-linux -mcpu=cortex-m0 -o /dev/null %s 2>&1 \
+; RUN: | FileCheck %s -check-prefix=CHECK-FEATURE
+
+define void @foo() {
+entry:
+ ret void
+}
+
+; CHECK-OPTIONS: Function 'foo' uses ARM instructions, but the target does not support ARM mode execution.
+
+define void @no_thumb_mode_feature() #0 {
+entry:
+ ret void
+}
+
+; CHECK-FEATURE: Function 'no_thumb_mode_feature' uses ARM instructions, but the target does not support ARM mode execution.
+
+attributes #0 = { "target-features"="-thumb-mode" }
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