diff options
Diffstat (limited to 'llvm')
10 files changed, 736 insertions, 680 deletions
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h index 8d61f9a6827..207c127f0e8 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h @@ -68,38 +68,17 @@ static Optional<APInt> ConstantFoldBinOp(unsigned Opcode, const unsigned Op1, /// An MIRBuilder which does trivial constant folding of binary ops. /// Calls to buildInstr will also try to constant fold binary ops. -class ConstantFoldingMIRBuilder - : public FoldableInstructionsBuilder<ConstantFoldingMIRBuilder> { +class ConstantFoldingMIRBuilder : public MachineIRBuilder { public: // Pull in base class constructors. - using FoldableInstructionsBuilder< - ConstantFoldingMIRBuilder>::FoldableInstructionsBuilder; - // Unhide buildInstr - using FoldableInstructionsBuilder<ConstantFoldingMIRBuilder>::buildInstr; + using MachineIRBuilder::MachineIRBuilder; - // Implement buildBinaryOp required by FoldableInstructionsBuilder which - // tries to constant fold. - MachineInstrBuilder buildBinaryOp(unsigned Opcode, unsigned Dst, - unsigned Src0, unsigned Src1) { - validateBinaryOp(Dst, Src0, Src1); - auto MaybeCst = ConstantFoldBinOp(Opcode, Src0, Src1, getMF().getRegInfo()); - if (MaybeCst) - return buildConstant(Dst, MaybeCst->getSExtValue()); - return buildInstr(Opcode).addDef(Dst).addUse(Src0).addUse(Src1); - } - - template <typename DstTy, typename UseArg1Ty, typename UseArg2Ty> - MachineInstrBuilder buildInstr(unsigned Opc, DstTy &&Ty, UseArg1Ty &&Arg1, - UseArg2Ty &&Arg2) { - unsigned Dst = getDestFromArg(Ty); - return buildInstr(Opc, Dst, getRegFromArg(std::forward<UseArg1Ty>(Arg1)), - getRegFromArg(std::forward<UseArg2Ty>(Arg2))); - } + virtual ~ConstantFoldingMIRBuilder() = default; // Try to provide an overload for buildInstr for binary ops in order to // constant fold. - MachineInstrBuilder buildInstr(unsigned Opc, unsigned Dst, unsigned Src0, - unsigned Src1) { + MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, + ArrayRef<SrcOp> SrcOps) override { switch (Opc) { default: break; @@ -116,19 +95,18 @@ public: case TargetOpcode::G_SDIV: case TargetOpcode::G_UREM: case TargetOpcode::G_SREM: { - return buildBinaryOp(Opc, Dst, Src0, Src1); + assert(DstOps.size() == 1 && "Invalid dst ops"); + assert(SrcOps.size() == 2 && "Invalid src ops"); + const DstOp &Dst = DstOps[0]; + const SrcOp &Src0 = SrcOps[0]; + const SrcOp &Src1 = SrcOps[1]; + if (auto MaybeCst = + ConstantFoldBinOp(Opc, Src0.getReg(), Src1.getReg(), *getMRI())) + return buildConstant(Dst, MaybeCst->getSExtValue()); + break; } } - return buildInstr(Opc).addDef(Dst).addUse(Src0).addUse(Src1); - } - - // Fallback implementation of buildInstr. - template <typename DstTy, typename... UseArgsTy> - MachineInstrBuilder buildInstr(unsigned Opc, DstTy &&Ty, - UseArgsTy &&... Args) { - auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty)); - addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...); - return MIB; + return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps); } }; } // namespace llvm diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h index 27956d05bab..868af641e91 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h @@ -59,7 +59,7 @@ public: m_all_of(m_MInstr(ExtMI), m_any_of(m_GAnyExt(m_Reg(ExtSrc)), m_GSExt(m_Reg(ExtSrc)), m_GZExt(m_Reg(ExtSrc)))))) { - Builder.buildInstr(ExtMI->getOpcode(), DstReg, ExtSrc); + Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc}); markInstAndDefDead(MI, *ExtMI, DeadInsts); return true; } @@ -118,9 +118,9 @@ public: unsigned ShAmt = DstTy.getSizeInBits() - SrcTy.getSizeInBits(); auto MIBShAmt = Builder.buildConstant(DstTy, ShAmt); auto MIBShl = Builder.buildInstr( - TargetOpcode::G_SHL, DstTy, - Builder.buildAnyExtOrTrunc(DstTy, TruncSrc), MIBShAmt); - Builder.buildInstr(TargetOpcode::G_ASHR, DstReg, MIBShl, MIBShAmt); + TargetOpcode::G_SHL, {DstTy}, + {Builder.buildAnyExtOrTrunc(DstTy, TruncSrc), MIBShAmt}); + Builder.buildInstr(TargetOpcode::G_ASHR, {DstReg}, {MIBShl, MIBShAmt}); markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); return true; } @@ -146,7 +146,7 @@ public: if (isInstUnsupported({TargetOpcode::G_IMPLICIT_DEF, {DstTy}})) return false; LLVM_DEBUG(dbgs() << ".. Combine G_ANYEXT(G_IMPLICIT_DEF): " << MI;); - Builder.buildInstr(TargetOpcode::G_IMPLICIT_DEF, DstReg); + Builder.buildInstr(TargetOpcode::G_IMPLICIT_DEF, {DstReg}, {}); } else { // G_[SZ]EXT (G_IMPLICIT_DEF) -> G_CONSTANT 0 because the top // bits will be 0 for G_ZEXT and 0/1 for the G_SEXT. diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index 965c6b9b61c..21cdeee28a5 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -54,55 +54,152 @@ struct MachineIRBuilderState { GISelChangeObserver *Observer; }; -/// Helper class to build MachineInstr. -/// It keeps internally the insertion point and debug location for all -/// the new instructions we want to create. -/// This information can be modify via the related setters. -class MachineIRBuilderBase { +class DstOp { + union { + LLT LLTTy; + unsigned Reg; + const TargetRegisterClass *RC; + }; - MachineIRBuilderState State; - void validateTruncExt(unsigned Dst, unsigned Src, bool IsExtend); - void recordInsertion(MachineInstr *MI) const; - -protected: - unsigned getDestFromArg(unsigned Reg) { return Reg; } - unsigned getDestFromArg(LLT Ty) { - return getMF().getRegInfo().createGenericVirtualRegister(Ty); +public: + enum class DstType { Ty_LLT, Ty_Reg, Ty_RC }; + DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {} + DstOp(const LLT &T) : LLTTy(T), Ty(DstType::Ty_LLT) {} + DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} + + void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const { + switch (Ty) { + case DstType::Ty_Reg: + MIB.addDef(Reg); + break; + case DstType::Ty_LLT: + MIB.addDef(MRI.createGenericVirtualRegister(LLTTy)); + break; + case DstType::Ty_RC: + MIB.addDef(MRI.createVirtualRegister(RC)); + break; + } } - unsigned getDestFromArg(const TargetRegisterClass *RC) { - return getMF().getRegInfo().createVirtualRegister(RC); + + DstType getType() const { return Ty; } + + LLT getLLTTy(const MachineRegisterInfo &MRI) const { + switch (Ty) { + case DstType::Ty_RC: + return LLT{}; + case DstType::Ty_LLT: + return LLTTy; + case DstType::Ty_Reg: + return MRI.getType(Reg); + } } - void addUseFromArg(MachineInstrBuilder &MIB, unsigned Reg) { - MIB.addUse(Reg); + DstType getDstOpKind() const { return Ty; } + +private: + DstType Ty; +}; + +class SrcOp { + union { + MachineInstrBuilder SrcMIB; + unsigned Reg; + CmpInst::Predicate Pred; + }; + +public: + enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate }; + SrcOp(unsigned R) : Reg(R), Ty(SrcType::Ty_Reg) {} + SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {} + SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {} + + void addSrcToMIB(MachineInstrBuilder &MIB) const { + switch (Ty) { + case SrcType::Ty_Predicate: + MIB.addPredicate(Pred); + break; + case SrcType::Ty_Reg: + MIB.addUse(Reg); + break; + case SrcType::Ty_MIB: + MIB.addUse(SrcMIB->getOperand(0).getReg()); + break; + } } - void addUseFromArg(MachineInstrBuilder &MIB, const MachineInstrBuilder &UseMIB) { - MIB.addUse(UseMIB->getOperand(0).getReg()); + LLT getLLTTy(const MachineRegisterInfo &MRI) const { + switch (Ty) { + case SrcType::Ty_Predicate: + llvm_unreachable("Not a register operand"); + case SrcType::Ty_Reg: + return MRI.getType(Reg); + case SrcType::Ty_MIB: + return MRI.getType(SrcMIB->getOperand(0).getReg()); + } } - void addUsesFromArgs(MachineInstrBuilder &MIB) { } - template<typename UseArgTy, typename ... UseArgsTy> - void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) { - addUseFromArg(MIB, Arg1); - addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...); + unsigned getReg() const { + switch (Ty) { + case SrcType::Ty_Predicate: + llvm_unreachable("Not a register operand"); + case SrcType::Ty_Reg: + return Reg; + case SrcType::Ty_MIB: + return SrcMIB->getOperand(0).getReg(); + } } - unsigned getRegFromArg(unsigned Reg) { return Reg; } - unsigned getRegFromArg(const MachineInstrBuilder &MIB) { - return MIB->getOperand(0).getReg(); + + CmpInst::Predicate getPredicate() const { + switch (Ty) { + case SrcType::Ty_Predicate: + return Pred; + default: + llvm_unreachable("Not a register operand"); + } } - void validateBinaryOp(unsigned Res, unsigned Op0, unsigned Op1); + SrcType getSrcOpKind() const { return Ty; } + +private: + SrcType Ty; +}; + +class FlagsOp { + Optional<unsigned> Flags; + +public: + explicit FlagsOp(unsigned F) : Flags(F) {} + FlagsOp() : Flags(None) {} + Optional<unsigned> getFlags() const { return Flags; } +}; +/// Helper class to build MachineInstr. +/// It keeps internally the insertion point and debug location for all +/// the new instructions we want to create. +/// This information can be modify via the related setters. +class MachineIRBuilder { + + MachineIRBuilderState State; + +protected: + void validateTruncExt(const LLT &Dst, const LLT &Src, bool IsExtend); + + void validateBinaryOp(const LLT &Res, const LLT &Op0, const LLT &Op1); + + void validateSelectOp(const LLT &ResTy, const LLT &TstTy, const LLT &Op0Ty, + const LLT &Op1Ty); + void recordInsertion(MachineInstr *MI) const; public: /// Some constructors for easy use. - MachineIRBuilderBase() = default; - MachineIRBuilderBase(MachineFunction &MF) { setMF(MF); } - MachineIRBuilderBase(MachineInstr &MI) : MachineIRBuilderBase(*MI.getMF()) { + MachineIRBuilder() = default; + MachineIRBuilder(MachineFunction &MF) { setMF(MF); } + MachineIRBuilder(MachineInstr &MI) : MachineIRBuilder(*MI.getMF()) { setInstr(MI); } - MachineIRBuilderBase(const MachineIRBuilderState &BState) : State(BState) {} + virtual ~MachineIRBuilder() = default; + + MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {} const TargetInstrInfo &getTII() { assert(State.TII && "TargetInstrInfo is not set"); @@ -298,9 +395,9 @@ public: /// registers with the same scalar type (typically s1) /// /// \return The newly created instruction. - MachineInstrBuilder buildUAdde(unsigned Res, unsigned CarryOut, unsigned Op0, - unsigned Op1, unsigned CarryIn); - + MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, + const SrcOp &Op0, const SrcOp &Op1, + const SrcOp &CarryIn); /// Build and insert \p Res = G_ANYEXT \p Op0 /// @@ -316,11 +413,7 @@ public: /// /// \return The newly created instruction. - MachineInstrBuilder buildAnyExt(unsigned Res, unsigned Op); - template <typename DstType, typename ArgType> - MachineInstrBuilder buildAnyExt(DstType &&Res, ArgType &&Arg) { - return buildAnyExt(getDestFromArg(Res), getRegFromArg(Arg)); - } + MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op); /// Build and insert \p Res = G_SEXT \p Op /// @@ -334,11 +427,7 @@ public: /// \pre \p Op must be smaller than \p Res /// /// \return The newly created instruction. - template <typename DstType, typename ArgType> - MachineInstrBuilder buildSExt(DstType &&Res, ArgType &&Arg) { - return buildSExt(getDestFromArg(Res), getRegFromArg(Arg)); - } - MachineInstrBuilder buildSExt(unsigned Res, unsigned Op); + MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op); /// Build and insert \p Res = G_ZEXT \p Op /// @@ -352,11 +441,7 @@ public: /// \pre \p Op must be smaller than \p Res /// /// \return The newly created instruction. - template <typename DstType, typename ArgType> - MachineInstrBuilder buildZExt(DstType &&Res, ArgType &&Arg) { - return buildZExt(getDestFromArg(Res), getRegFromArg(Arg)); - } - MachineInstrBuilder buildZExt(unsigned Res, unsigned Op); + MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op); /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. @@ -366,11 +451,7 @@ public: /// \pre \p Op must be a generic virtual register with scalar or vector type. /// /// \return The newly created instruction. - template <typename DstTy, typename UseArgTy> - MachineInstrBuilder buildSExtOrTrunc(DstTy &&Dst, UseArgTy &&Use) { - return buildSExtOrTrunc(getDestFromArg(Dst), getRegFromArg(Use)); - } - MachineInstrBuilder buildSExtOrTrunc(unsigned Res, unsigned Op); + MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op); /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. @@ -380,11 +461,7 @@ public: /// \pre \p Op must be a generic virtual register with scalar or vector type. /// /// \return The newly created instruction. - template <typename DstTy, typename UseArgTy> - MachineInstrBuilder buildZExtOrTrunc(DstTy &&Dst, UseArgTy &&Use) { - return buildZExtOrTrunc(getDestFromArg(Dst), getRegFromArg(Use)); - } - MachineInstrBuilder buildZExtOrTrunc(unsigned Res, unsigned Op); + MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op); // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. @@ -394,11 +471,7 @@ public: /// \pre \p Op must be a generic virtual register with scalar or vector type. /// /// \return The newly created instruction. - template <typename DstTy, typename UseArgTy> - MachineInstrBuilder buildAnyExtOrTrunc(DstTy &&Dst, UseArgTy &&Use) { - return buildAnyExtOrTrunc(getDestFromArg(Dst), getRegFromArg(Use)); - } - MachineInstrBuilder buildAnyExtOrTrunc(unsigned Res, unsigned Op); + MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op); /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and @@ -409,15 +482,11 @@ public: /// \pre \p Op must be a generic virtual register with scalar or vector type. /// /// \return The newly created instruction. - MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, unsigned Res, - unsigned Op); + MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, + const SrcOp &Op); /// Build and insert an appropriate cast between two registers of equal size. - template <typename DstType, typename ArgType> - MachineInstrBuilder buildCast(DstType &&Res, ArgType &&Arg) { - return buildCast(getDestFromArg(Res), getRegFromArg(Arg)); - } - MachineInstrBuilder buildCast(unsigned Dst, unsigned Src); + MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src); /// Build and insert G_BR \p Dest /// @@ -462,7 +531,7 @@ public: /// type. /// /// \return The newly created instruction. - MachineInstrBuilder buildConstant(unsigned Res, const ConstantInt &Val); + MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val); /// Build and insert \p Res = G_CONSTANT \p Val /// @@ -472,12 +541,8 @@ public: /// \pre \p Res must be a generic virtual register with scalar type. /// /// \return The newly created instruction. - MachineInstrBuilder buildConstant(unsigned Res, int64_t Val); + MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val); - template <typename DstType> - MachineInstrBuilder buildConstant(DstType &&Res, int64_t Val) { - return buildConstant(getDestFromArg(Res), Val); - } /// Build and insert \p Res = G_FCONSTANT \p Val /// /// G_FCONSTANT is a floating-point constant with the specified size and @@ -487,17 +552,9 @@ public: /// \pre \p Res must be a generic virtual register with scalar type. /// /// \return The newly created instruction. - template <typename DstType> - MachineInstrBuilder buildFConstant(DstType &&Res, const ConstantFP &Val) { - return buildFConstant(getDestFromArg(Res), Val); - } - MachineInstrBuilder buildFConstant(unsigned Res, const ConstantFP &Val); + MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val); - template <typename DstType> - MachineInstrBuilder buildFConstant(DstType &&Res, double Val) { - return buildFConstant(getDestFromArg(Res), Val); - } - MachineInstrBuilder buildFConstant(unsigned Res, double Val); + MachineInstrBuilder buildFConstant(const DstOp &Res, double Val); /// Build and insert \p Res = COPY Op /// @@ -506,11 +563,7 @@ public: /// \pre setBasicBlock or setMI must have been called. /// /// \return a MachineInstrBuilder for the newly created instruction. - MachineInstrBuilder buildCopy(unsigned Res, unsigned Op); - template <typename DstType, typename SrcType> - MachineInstrBuilder buildCopy(DstType &&Res, SrcType &&Src) { - return buildCopy(getDestFromArg(Res), getRegFromArg(Src)); - } + MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op); /// Build and insert `Res = G_LOAD Addr, MMO`. /// @@ -557,10 +610,7 @@ public: MachineInstrBuilder buildExtract(unsigned Res, unsigned Src, uint64_t Index); /// Build and insert \p Res = IMPLICIT_DEF. - template <typename DstType> MachineInstrBuilder buildUndef(DstType &&Res) { - return buildUndef(getDestFromArg(Res)); - } - MachineInstrBuilder buildUndef(unsigned Res); + MachineInstrBuilder buildUndef(const DstOp &Res); /// Build and insert instructions to put \p Ops together at the specified p /// Indices to form a larger register. @@ -589,7 +639,7 @@ public: /// \pre The type of all \p Ops registers must be identical. /// /// \return a MachineInstrBuilder for the newly created instruction. - MachineInstrBuilder buildMerge(unsigned Res, ArrayRef<unsigned> Ops); + MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<unsigned> Ops); /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op /// @@ -601,7 +651,8 @@ public: /// \pre The type of all \p Res registers must be identical. /// /// \return a MachineInstrBuilder for the newly created instruction. - MachineInstrBuilder buildUnmerge(ArrayRef<unsigned> Res, unsigned Op); + MachineInstrBuilder buildUnmerge(ArrayRef<LLT> Res, const SrcOp &Op); + MachineInstrBuilder buildUnmerge(ArrayRef<unsigned> Res, const SrcOp &Op); /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... /// @@ -612,7 +663,8 @@ public: /// \pre The type of all \p Ops registers must be identical. /// /// \return a MachineInstrBuilder for the newly created instruction. - MachineInstrBuilder buildBuildVector(unsigned Res, ArrayRef<unsigned> Ops); + MachineInstrBuilder buildBuildVector(const DstOp &Res, + ArrayRef<unsigned> Ops); /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ... /// @@ -627,7 +679,7 @@ public: /// \pre The type of all \p Ops registers must be identical. /// /// \return a MachineInstrBuilder for the newly created instruction. - MachineInstrBuilder buildBuildVectorTrunc(unsigned Res, + MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef<unsigned> Ops); /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ... @@ -641,7 +693,8 @@ public: /// \pre The type of all source operands must be identical. /// /// \return a MachineInstrBuilder for the newly created instruction. - MachineInstrBuilder buildConcatVectors(unsigned Res, ArrayRef<unsigned> Ops); + MachineInstrBuilder buildConcatVectors(const DstOp &Res, + ArrayRef<unsigned> Ops); MachineInstrBuilder buildInsert(unsigned Res, unsigned Src, unsigned Op, unsigned Index); @@ -669,11 +722,7 @@ public: /// \pre \p Res must be smaller than \p Op /// /// \return The newly created instruction. - template <typename DstType, typename SrcType> - MachineInstrBuilder buildFPTrunc(DstType &&Res, SrcType &&Src) { - return buildFPTrunc(getDestFromArg(Res), getRegFromArg(Src)); - } - MachineInstrBuilder buildFPTrunc(unsigned Res, unsigned Op); + MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op); /// Build and insert \p Res = G_TRUNC \p Op /// @@ -686,11 +735,7 @@ public: /// \pre \p Res must be smaller than \p Op /// /// \return The newly created instruction. - MachineInstrBuilder buildTrunc(unsigned Res, unsigned Op); - template <typename DstType, typename SrcType> - MachineInstrBuilder buildTrunc(DstType &&Res, SrcType &&Src) { - return buildTrunc(getDestFromArg(Res), getRegFromArg(Src)); - } + MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op); /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1 /// @@ -704,13 +749,8 @@ public: /// \pre \p Pred must be an integer predicate. /// /// \return a MachineInstrBuilder for the newly created instruction. - MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, - unsigned Res, unsigned Op0, unsigned Op1); - template <typename DstTy, typename... UseArgsTy> - MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, DstTy &&Dst, - UseArgsTy &&... UseArgs) { - return buildICmp(Pred, getDestFromArg(Dst), getRegFromArg(UseArgs)...); - } + MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, + const SrcOp &Op0, const SrcOp &Op1); /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1 /// @@ -724,8 +764,8 @@ public: /// \pre \p Pred must be a floating-point predicate. /// /// \return a MachineInstrBuilder for the newly created instruction. - MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, - unsigned Res, unsigned Op0, unsigned Op1); + MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, + const SrcOp &Op0, const SrcOp &Op1); /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1 /// @@ -737,12 +777,8 @@ public: /// elements as the other parameters. /// /// \return a MachineInstrBuilder for the newly created instruction. - MachineInstrBuilder buildSelect(unsigned Res, unsigned Tst, - unsigned Op0, unsigned Op1); - template <typename DstTy, typename... UseArgsTy> - MachineInstrBuilder buildSelect(DstTy &&Dst, UseArgsTy &&... UseArgs) { - return buildSelect(getDestFromArg(Dst), getRegFromArg(UseArgs)...); - } + MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, + const SrcOp &Op0, const SrcOp &Op1); /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val, /// \p Elt, \p Idx @@ -754,8 +790,10 @@ public: /// with scalar type. /// /// \return The newly created instruction. - MachineInstrBuilder buildInsertVectorElement(unsigned Res, unsigned Val, - unsigned Elt, unsigned Idx); + MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, + const SrcOp &Val, + const SrcOp &Elt, + const SrcOp &Idx); /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx /// @@ -765,8 +803,9 @@ public: /// \pre \p Idx must be a generic virtual register with scalar type. /// /// \return The newly created instruction. - MachineInstrBuilder buildExtractVectorElement(unsigned Res, unsigned Val, - unsigned Idx); + MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, + const SrcOp &Val, + const SrcOp &Idx); /// Build and insert `OldValRes<def>, SuccessRes<def> = /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`. @@ -1003,19 +1042,7 @@ public: /// /// \return The newly created instruction. MachineInstrBuilder buildBlockAddress(unsigned Res, const BlockAddress *BA); -}; -/// A CRTP class that contains methods for building instructions that can -/// be constant folded. MachineIRBuilders that want to inherit from this will -/// need to implement buildBinaryOp (for constant folding binary ops). -/// Alternatively, they can implement buildInstr(Opc, Dst, Uses...) to perform -/// additional folding for Opc. -template <typename Base> -class FoldableInstructionsBuilder : public MachineIRBuilderBase { - Base &base() { return static_cast<Base &>(*this); } - -public: - using MachineIRBuilderBase::MachineIRBuilderBase; /// Build and insert \p Res = G_ADD \p Op0, \p Op1 /// /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1, @@ -1027,13 +1054,9 @@ public: /// /// \return a MachineInstrBuilder for the newly created instruction. - MachineInstrBuilder buildAdd(unsigned Dst, unsigned Src0, unsigned Src1) { - return base().buildBinaryOp(TargetOpcode::G_ADD, Dst, Src0, Src1); - } - template <typename DstTy, typename... UseArgsTy> - MachineInstrBuilder buildAdd(DstTy &&Ty, UseArgsTy &&... UseArgs) { - unsigned Res = base().getDestFromArg(Ty); - return base().buildAdd(Res, (base().getRegFromArg(UseArgs))...); + MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, + const SrcOp &Src1) { + return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}); } /// Build and insert \p Res = G_SUB \p Op0, \p Op1 @@ -1047,13 +1070,9 @@ public: /// /// \return a MachineInstrBuilder for the newly created instruction. - MachineInstrBuilder buildSub(unsigned Dst, unsigned Src0, unsigned Src1) { - return base().buildBinaryOp(TargetOpcode::G_SUB, Dst, Src0, Src1); - } - template <typename DstTy, typename... UseArgsTy> - MachineInstrBuilder buildSub(DstTy &&Ty, UseArgsTy &&... UseArgs) { - unsigned Res = base().getDestFromArg(Ty); - return base().buildSub(Res, (base().getRegFromArg(UseArgs))...); + MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, + const SrcOp &Src1) { + return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}); } /// Build and insert \p Res = G_MUL \p Op0, \p Op1 @@ -1066,13 +1085,9 @@ public: /// with the same (scalar or vector) type). /// /// \return a MachineInstrBuilder for the newly created instruction. - MachineInstrBuilder buildMul(unsigned Dst, unsigned Src0, unsigned Src1) { - return base().buildBinaryOp(TargetOpcode::G_MUL, Dst, Src0, Src1); - } - template <typename DstTy, typename... UseArgsTy> - MachineInstrBuilder buildMul(DstTy &&Ty, UseArgsTy &&... UseArgs) { - unsigned Res = base().getDestFromArg(Ty); - return base().buildMul(Res, (base().getRegFromArg(UseArgs))...); + MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, + const SrcOp &Src1) { + return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}); } /// Build and insert \p Res = G_AND \p Op0, \p Op1 @@ -1086,13 +1101,9 @@ public: /// /// \return a MachineInstrBuilder for the newly created instruction. - MachineInstrBuilder buildAnd(unsigned Dst, unsigned Src0, unsigned Src1) { - return base().buildBinaryOp(TargetOpcode::G_AND, Dst, Src0, Src1); - } - template <typename DstTy, typename... UseArgsTy> - MachineInstrBuilder buildAnd(DstTy &&Ty, UseArgsTy &&... UseArgs) { - unsigned Res = base().getDestFromArg(Ty); - return base().buildAnd(Res, (base().getRegFromArg(UseArgs))...); + MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, + const SrcOp &Src1) { + return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1}); } /// Build and insert \p Res = G_OR \p Op0, \p Op1 @@ -1105,39 +1116,13 @@ public: /// with the same (scalar or vector) type). /// /// \return a MachineInstrBuilder for the newly created instruction. - MachineInstrBuilder buildOr(unsigned Dst, unsigned Src0, unsigned Src1) { - return base().buildBinaryOp(TargetOpcode::G_OR, Dst, Src0, Src1); + MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, + const SrcOp &Src1) { + return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1}); } - template <typename DstTy, typename... UseArgsTy> - MachineInstrBuilder buildOr(DstTy &&Ty, UseArgsTy &&... UseArgs) { - unsigned Res = base().getDestFromArg(Ty); - return base().buildOr(Res, (base().getRegFromArg(UseArgs))...); - } -}; -class MachineIRBuilder : public FoldableInstructionsBuilder<MachineIRBuilder> { -public: - using FoldableInstructionsBuilder< - MachineIRBuilder>::FoldableInstructionsBuilder; - MachineInstrBuilder buildBinaryOp(unsigned Opcode, unsigned Dst, - unsigned Src0, unsigned Src1) { - validateBinaryOp(Dst, Src0, Src1); - return buildInstr(Opcode).addDef(Dst).addUse(Src0).addUse(Src1); - } - using FoldableInstructionsBuilder<MachineIRBuilder>::buildInstr; - /// DAG like Generic method for building arbitrary instructions as above. - /// \Opc opcode for the instruction. - /// \Ty Either LLT/TargetRegisterClass/unsigned types for Dst - /// \Args Variadic list of uses of types(unsigned/MachineInstrBuilder) - /// Uses of type MachineInstrBuilder will perform - /// getOperand(0).getReg() to convert to register. - template <typename DstTy, typename... UseArgsTy> - MachineInstrBuilder buildInstr(unsigned Opc, DstTy &&Ty, - UseArgsTy &&... Args) { - auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty)); - addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...); - return MIB; - } + virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, + ArrayRef<SrcOp> SrcOps); }; } // End namespace llvm. diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 6278804a171..5098e15faa5 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -933,11 +933,11 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, TLI.isFMAFasterThanFMulAndFAdd(TLI.getValueType(*DL, CI.getType()))) { // TODO: Revisit this to see if we should move this part of the // lowering to the combiner. - MIRBuilder.buildInstr(TargetOpcode::G_FMA, Dst, Op0, Op1, Op2); + MIRBuilder.buildInstr(TargetOpcode::G_FMA, {Dst}, {Op0, Op1, Op2}); } else { LLT Ty = getLLTForType(*CI.getType(), *DL); - auto FMul = MIRBuilder.buildInstr(TargetOpcode::G_FMUL, Ty, Op0, Op1); - MIRBuilder.buildInstr(TargetOpcode::G_FADD, Dst, FMul, Op2); + auto FMul = MIRBuilder.buildInstr(TargetOpcode::G_FMUL, {Ty}, {Op0, Op1}); + MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Dst}, {FMul, Op2}); } return true; } @@ -1414,7 +1414,7 @@ bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) { SmallVector<MachineInstr *, 4> Insts; for (auto Reg : getOrCreateVRegs(PI)) { - auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, Reg); + auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, {Reg}, {}); Insts.push_back(MIB.getInstr()); } diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index f116a59b20d..197bf256584 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -634,7 +634,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx, unsigned ExtOpcode) { MachineOperand &MO = MI.getOperand(OpIdx); - auto ExtB = MIRBuilder.buildInstr(ExtOpcode, WideTy, MO.getReg()); + auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()}); MO.setReg(ExtB->getOperand(0).getReg()); } @@ -643,7 +643,7 @@ void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy, MachineOperand &MO = MI.getOperand(OpIdx); unsigned DstExt = MRI.createGenericVirtualRegister(WideTy); MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); - MIRBuilder.buildInstr(TruncOpcode, MO.getReg(), DstExt); + MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt}); MO.setReg(DstExt); } @@ -658,20 +658,20 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { case TargetOpcode::G_USUBO: { if (TypeIdx == 1) return UnableToLegalize; // TODO - auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, WideTy, - MI.getOperand(2).getReg()); - auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, WideTy, - MI.getOperand(3).getReg()); + auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy}, + {MI.getOperand(2).getReg()}); + auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy}, + {MI.getOperand(3).getReg()}); unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO ? TargetOpcode::G_ADD : TargetOpcode::G_SUB; // Do the arithmetic in the larger type. - auto NewOp = MIRBuilder.buildInstr(Opcode, WideTy, LHSZext, RHSZext); + auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext}); LLT OrigTy = MRI.getType(MI.getOperand(0).getReg()); APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits()); auto AndOp = MIRBuilder.buildInstr( - TargetOpcode::G_AND, WideTy, NewOp, - MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())); + TargetOpcode::G_AND, {WideTy}, + {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())}); // There is no overflow if the AndOp is the same as NewOp. MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp, AndOp); @@ -695,19 +695,19 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { auto TopBit = APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits()); MIBSrc = MIRBuilder.buildInstr( - TargetOpcode::G_OR, WideTy, MIBSrc, - MIRBuilder.buildConstant(WideTy, TopBit.getSExtValue())); + TargetOpcode::G_OR, {WideTy}, + {MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit.getSExtValue())}); } // Perform the operation at the larger size. - auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), WideTy, MIBSrc); + auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc}); // This is already the correct result for CTPOP and CTTZs if (MI.getOpcode() == TargetOpcode::G_CTLZ || MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) { // The correct result is NewOp - (Difference in widety and current ty). unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits(); - MIBNewOp = - MIRBuilder.buildInstr(TargetOpcode::G_SUB, WideTy, MIBNewOp, - MIRBuilder.buildConstant(WideTy, SizeDiff)); + MIBNewOp = MIRBuilder.buildInstr( + TargetOpcode::G_SUB, {WideTy}, + {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)}); } auto &TII = *MI.getMF()->getSubtarget().getInstrInfo(); // Make the original instruction a trunc now, and update its source. @@ -1161,8 +1161,8 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) { unsigned Len = Ty.getSizeInBits(); if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty}})) { // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero. - auto MIBCtlzZU = - MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, Ty, SrcReg); + auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, + {Ty}, {SrcReg}); auto MIBZero = MIRBuilder.buildConstant(Ty, 0); auto MIBLen = MIRBuilder.buildConstant(Ty, Len); auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), @@ -1188,13 +1188,14 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) { for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) { auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i); auto MIBOp = MIRBuilder.buildInstr( - TargetOpcode::G_OR, Ty, Op, - MIRBuilder.buildInstr(TargetOpcode::G_LSHR, Ty, Op, MIBShiftAmt)); + TargetOpcode::G_OR, {Ty}, + {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty}, + {Op, MIBShiftAmt})}); Op = MIBOp->getOperand(0).getReg(); } - auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, Ty, Op); - MIRBuilder.buildInstr(TargetOpcode::G_SUB, MI.getOperand(0).getReg(), - MIRBuilder.buildConstant(Ty, Len), MIBPop); + auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op}); + MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()}, + {MIRBuilder.buildConstant(Ty, Len), MIBPop}); MI.eraseFromParent(); return Legalized; } @@ -1210,8 +1211,8 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) { if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty}})) { // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with // zero. - auto MIBCttzZU = - MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, Ty, SrcReg); + auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, + {Ty}, {SrcReg}); auto MIBZero = MIRBuilder.buildConstant(Ty, 0); auto MIBLen = MIRBuilder.buildConstant(Ty, Len); auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), @@ -1227,17 +1228,18 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) { // Ref: "Hacker's Delight" by Henry Warren auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1); auto MIBNot = - MIRBuilder.buildInstr(TargetOpcode::G_XOR, Ty, SrcReg, MIBCstNeg1); + MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1}); auto MIBTmp = MIRBuilder.buildInstr( - TargetOpcode::G_AND, Ty, MIBNot, - MIRBuilder.buildInstr(TargetOpcode::G_ADD, Ty, SrcReg, MIBCstNeg1)); + TargetOpcode::G_AND, {Ty}, + {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty}, + {SrcReg, MIBCstNeg1})}); if (!isSupported({TargetOpcode::G_CTPOP, {Ty}}) && isSupported({TargetOpcode::G_CTLZ, {Ty}})) { auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len); MIRBuilder.buildInstr( - TargetOpcode::G_SUB, MI.getOperand(0).getReg(), - MIBCstLen, - MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, Ty, MIBTmp)); + TargetOpcode::G_SUB, {MI.getOperand(0).getReg()}, + {MIBCstLen, + MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})}); MI.eraseFromParent(); return Legalized; } diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 95600cdd9dd..9d485a08612 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -23,7 +23,7 @@ using namespace llvm; -void MachineIRBuilderBase::setMF(MachineFunction &MF) { +void MachineIRBuilder::setMF(MachineFunction &MF) { State.MF = &MF; State.MBB = nullptr; State.MRI = &MF.getRegInfo(); @@ -33,60 +33,60 @@ void MachineIRBuilderBase::setMF(MachineFunction &MF) { State.Observer = nullptr; } -void MachineIRBuilderBase::setMBB(MachineBasicBlock &MBB) { +void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) { State.MBB = &MBB; State.II = MBB.end(); assert(&getMF() == MBB.getParent() && "Basic block is in a different function"); } -void MachineIRBuilderBase::setInstr(MachineInstr &MI) { +void MachineIRBuilder::setInstr(MachineInstr &MI) { assert(MI.getParent() && "Instruction is not part of a basic block"); setMBB(*MI.getParent()); State.II = MI.getIterator(); } -void MachineIRBuilderBase::setInsertPt(MachineBasicBlock &MBB, - MachineBasicBlock::iterator II) { +void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB, + MachineBasicBlock::iterator II) { assert(MBB.getParent() == &getMF() && "Basic block is in a different function"); State.MBB = &MBB; State.II = II; } -void MachineIRBuilderBase::recordInsertion(MachineInstr *InsertedInstr) const { +void MachineIRBuilder::recordInsertion(MachineInstr *InsertedInstr) const { if (State.Observer) State.Observer->createdInstr(*InsertedInstr); } -void MachineIRBuilderBase::setChangeObserver(GISelChangeObserver &Observer) { +void MachineIRBuilder::setChangeObserver(GISelChangeObserver &Observer) { State.Observer = &Observer; } -void MachineIRBuilderBase::stopObservingChanges() { State.Observer = nullptr; } +void MachineIRBuilder::stopObservingChanges() { State.Observer = nullptr; } //------------------------------------------------------------------------------ // Build instruction variants. //------------------------------------------------------------------------------ -MachineInstrBuilder MachineIRBuilderBase::buildInstr(unsigned Opcode) { +MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) { return insertInstr(buildInstrNoInsert(Opcode)); } -MachineInstrBuilder MachineIRBuilderBase::buildInstrNoInsert(unsigned Opcode) { +MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) { MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode)); return MIB; } -MachineInstrBuilder MachineIRBuilderBase::insertInstr(MachineInstrBuilder MIB) { +MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) { getMBB().insert(getInsertPt(), MIB); recordInsertion(MIB); return MIB; } MachineInstrBuilder -MachineIRBuilderBase::buildDirectDbgValue(unsigned Reg, const MDNode *Variable, - const MDNode *Expr) { +MachineIRBuilder::buildDirectDbgValue(unsigned Reg, const MDNode *Variable, + const MDNode *Expr) { assert(isa<DILocalVariable>(Variable) && "not a variable"); assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); assert( @@ -97,8 +97,9 @@ MachineIRBuilderBase::buildDirectDbgValue(unsigned Reg, const MDNode *Variable, /*IsIndirect*/ false, Reg, Variable, Expr)); } -MachineInstrBuilder MachineIRBuilderBase::buildIndirectDbgValue( - unsigned Reg, const MDNode *Variable, const MDNode *Expr) { +MachineInstrBuilder +MachineIRBuilder::buildIndirectDbgValue(unsigned Reg, const MDNode *Variable, + const MDNode *Expr) { assert(isa<DILocalVariable>(Variable) && "not a variable"); assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); assert( @@ -109,9 +110,9 @@ MachineInstrBuilder MachineIRBuilderBase::buildIndirectDbgValue( /*IsIndirect*/ true, Reg, Variable, Expr)); } -MachineInstrBuilder -MachineIRBuilderBase::buildFIDbgValue(int FI, const MDNode *Variable, - const MDNode *Expr) { +MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI, + const MDNode *Variable, + const MDNode *Expr) { assert(isa<DILocalVariable>(Variable) && "not a variable"); assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); assert( @@ -124,8 +125,9 @@ MachineIRBuilderBase::buildFIDbgValue(int FI, const MDNode *Variable, .addMetadata(Expr); } -MachineInstrBuilder MachineIRBuilderBase::buildConstDbgValue( - const Constant &C, const MDNode *Variable, const MDNode *Expr) { +MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C, + const MDNode *Variable, + const MDNode *Expr) { assert(isa<DILocalVariable>(Variable) && "not a variable"); assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); assert( @@ -147,7 +149,7 @@ MachineInstrBuilder MachineIRBuilderBase::buildConstDbgValue( return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr); } -MachineInstrBuilder MachineIRBuilderBase::buildDbgLabel(const MDNode *Label) { +MachineInstrBuilder MachineIRBuilder::buildDbgLabel(const MDNode *Label) { assert(isa<DILabel>(Label) && "not a label"); assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) && "Expected inlined-at fields to agree"); @@ -156,16 +158,15 @@ MachineInstrBuilder MachineIRBuilderBase::buildDbgLabel(const MDNode *Label) { return MIB.addMetadata(Label); } -MachineInstrBuilder MachineIRBuilderBase::buildFrameIndex(unsigned Res, - int Idx) { +MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) { assert(getMRI()->getType(Res).isPointer() && "invalid operand type"); return buildInstr(TargetOpcode::G_FRAME_INDEX) .addDef(Res) .addFrameIndex(Idx); } -MachineInstrBuilder -MachineIRBuilderBase::buildGlobalValue(unsigned Res, const GlobalValue *GV) { +MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res, + const GlobalValue *GV) { assert(getMRI()->getType(Res).isPointer() && "invalid operand type"); assert(getMRI()->getType(Res).getAddressSpace() == GV->getType()->getAddressSpace() && @@ -176,17 +177,14 @@ MachineIRBuilderBase::buildGlobalValue(unsigned Res, const GlobalValue *GV) { .addGlobalAddress(GV); } -void MachineIRBuilderBase::validateBinaryOp(unsigned Res, unsigned Op0, - unsigned Op1) { - assert((getMRI()->getType(Res).isScalar() || - getMRI()->getType(Res).isVector()) && - "invalid operand type"); - assert(getMRI()->getType(Res) == getMRI()->getType(Op0) && - getMRI()->getType(Res) == getMRI()->getType(Op1) && "type mismatch"); +void MachineIRBuilder::validateBinaryOp(const LLT &Res, const LLT &Op0, + const LLT &Op1) { + assert(Res.isScalar() || Res.isVector() && "invalid operand type"); + assert((Res == Op0 && Res == Op1) && "type mismatch"); } -MachineInstrBuilder MachineIRBuilderBase::buildGEP(unsigned Res, unsigned Op0, - unsigned Op1) { +MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0, + unsigned Op1) { assert(getMRI()->getType(Res).isPointer() && getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch"); assert(getMRI()->getType(Op1).isScalar() && "invalid offset type"); @@ -198,8 +196,8 @@ MachineInstrBuilder MachineIRBuilderBase::buildGEP(unsigned Res, unsigned Op0, } Optional<MachineInstrBuilder> -MachineIRBuilderBase::materializeGEP(unsigned &Res, unsigned Op0, - const LLT &ValueTy, uint64_t Value) { +MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0, + const LLT &ValueTy, uint64_t Value) { assert(Res == 0 && "Res is a result argument"); assert(ValueTy.isScalar() && "invalid offset type"); @@ -215,9 +213,8 @@ MachineIRBuilderBase::materializeGEP(unsigned &Res, unsigned Op0, return buildGEP(Res, Op0, TmpReg); } -MachineInstrBuilder MachineIRBuilderBase::buildPtrMask(unsigned Res, - unsigned Op0, - uint32_t NumBits) { +MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0, + uint32_t NumBits) { assert(getMRI()->getType(Res).isPointer() && getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch"); @@ -227,24 +224,23 @@ MachineInstrBuilder MachineIRBuilderBase::buildPtrMask(unsigned Res, .addImm(NumBits); } -MachineInstrBuilder MachineIRBuilderBase::buildBr(MachineBasicBlock &Dest) { +MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) { return buildInstr(TargetOpcode::G_BR).addMBB(&Dest); } -MachineInstrBuilder MachineIRBuilderBase::buildBrIndirect(unsigned Tgt) { +MachineInstrBuilder MachineIRBuilder::buildBrIndirect(unsigned Tgt) { assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination"); return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt); } -MachineInstrBuilder MachineIRBuilderBase::buildCopy(unsigned Res, unsigned Op) { - assert(getMRI()->getType(Res) == LLT() || getMRI()->getType(Op) == LLT() || - getMRI()->getType(Res) == getMRI()->getType(Op)); - return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op); +MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res, + const SrcOp &Op) { + return buildInstr(TargetOpcode::COPY, Res, Op); } -MachineInstrBuilder -MachineIRBuilderBase::buildConstant(unsigned Res, const ConstantInt &Val) { - LLT Ty = getMRI()->getType(Res); +MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, + const ConstantInt &Val) { + LLT Ty = Res.getLLTTy(*getMRI()); assert((Ty.isScalar() || Ty.isPointer()) && "invalid operand type"); @@ -253,48 +249,55 @@ MachineIRBuilderBase::buildConstant(unsigned Res, const ConstantInt &Val) { NewVal = ConstantInt::get(getMF().getFunction().getContext(), Val.getValue().sextOrTrunc(Ty.getSizeInBits())); - return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addCImm(NewVal); + auto MIB = buildInstr(TargetOpcode::G_CONSTANT); + Res.addDefToMIB(*getMRI(), MIB); + MIB.addCImm(NewVal); + return MIB; } -MachineInstrBuilder MachineIRBuilderBase::buildConstant(unsigned Res, - int64_t Val) { +MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, + int64_t Val) { auto IntN = IntegerType::get(getMF().getFunction().getContext(), - getMRI()->getType(Res).getSizeInBits()); + Res.getLLTTy(*getMRI()).getSizeInBits()); ConstantInt *CI = ConstantInt::get(IntN, Val, true); return buildConstant(Res, *CI); } -MachineInstrBuilder -MachineIRBuilderBase::buildFConstant(unsigned Res, const ConstantFP &Val) { - assert(getMRI()->getType(Res).isScalar() && "invalid operand type"); +MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res, + const ConstantFP &Val) { + assert(Res.getLLTTy(*getMRI()).isScalar() && "invalid operand type"); - return buildInstr(TargetOpcode::G_FCONSTANT).addDef(Res).addFPImm(&Val); + auto MIB = buildInstr(TargetOpcode::G_FCONSTANT); + Res.addDefToMIB(*getMRI(), MIB); + MIB.addFPImm(&Val); + return MIB; } -MachineInstrBuilder MachineIRBuilderBase::buildFConstant(unsigned Res, - double Val) { - LLT DstTy = getMRI()->getType(Res); +MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res, + double Val) { + LLT DstTy = Res.getLLTTy(*getMRI()); auto &Ctx = getMF().getFunction().getContext(); auto *CFP = ConstantFP::get(Ctx, getAPFloatFromSize(Val, DstTy.getSizeInBits())); return buildFConstant(Res, *CFP); } -MachineInstrBuilder MachineIRBuilderBase::buildBrCond(unsigned Tst, - MachineBasicBlock &Dest) { +MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst, + MachineBasicBlock &Dest) { assert(getMRI()->getType(Tst).isScalar() && "invalid operand type"); return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest); } -MachineInstrBuilder MachineIRBuilderBase::buildLoad(unsigned Res, unsigned Addr, - MachineMemOperand &MMO) { +MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr, + MachineMemOperand &MMO) { return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO); } -MachineInstrBuilder -MachineIRBuilderBase::buildLoadInstr(unsigned Opcode, unsigned Res, - unsigned Addr, MachineMemOperand &MMO) { +MachineInstrBuilder MachineIRBuilder::buildLoadInstr(unsigned Opcode, + unsigned Res, + unsigned Addr, + MachineMemOperand &MMO) { assert(getMRI()->getType(Res).isValid() && "invalid operand type"); assert(getMRI()->getType(Addr).isPointer() && "invalid operand type"); @@ -304,9 +307,8 @@ MachineIRBuilderBase::buildLoadInstr(unsigned Opcode, unsigned Res, .addMemOperand(&MMO); } -MachineInstrBuilder MachineIRBuilderBase::buildStore(unsigned Val, - unsigned Addr, - MachineMemOperand &MMO) { +MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr, + MachineMemOperand &MMO) { assert(getMRI()->getType(Val).isValid() && "invalid operand type"); assert(getMRI()->getType(Addr).isPointer() && "invalid operand type"); @@ -316,83 +318,73 @@ MachineInstrBuilder MachineIRBuilderBase::buildStore(unsigned Val, .addMemOperand(&MMO); } -MachineInstrBuilder MachineIRBuilderBase::buildUAdde(unsigned Res, - unsigned CarryOut, - unsigned Op0, unsigned Op1, - unsigned CarryIn) { - assert(getMRI()->getType(Res).isScalar() && "invalid operand type"); - assert(getMRI()->getType(Res) == getMRI()->getType(Op0) && - getMRI()->getType(Res) == getMRI()->getType(Op1) && "type mismatch"); - assert(getMRI()->getType(CarryOut).isScalar() && "invalid operand type"); - assert(getMRI()->getType(CarryOut) == getMRI()->getType(CarryIn) && - "type mismatch"); - - return buildInstr(TargetOpcode::G_UADDE) - .addDef(Res) - .addDef(CarryOut) - .addUse(Op0) - .addUse(Op1) - .addUse(CarryIn); +MachineInstrBuilder MachineIRBuilder::buildUAdde(const DstOp &Res, + const DstOp &CarryOut, + const SrcOp &Op0, + const SrcOp &Op1, + const SrcOp &CarryIn) { + return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut}, + {Op0, Op1, CarryIn}); } -MachineInstrBuilder MachineIRBuilderBase::buildAnyExt(unsigned Res, - unsigned Op) { - validateTruncExt(Res, Op, true); - return buildInstr(TargetOpcode::G_ANYEXT).addDef(Res).addUse(Op); +MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res, + const SrcOp &Op) { + return buildInstr(TargetOpcode::G_ANYEXT, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildSExt(unsigned Res, unsigned Op) { - validateTruncExt(Res, Op, true); - return buildInstr(TargetOpcode::G_SEXT).addDef(Res).addUse(Op); +MachineInstrBuilder MachineIRBuilder::buildSExt(const DstOp &Res, + const SrcOp &Op) { + return buildInstr(TargetOpcode::G_SEXT, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildZExt(unsigned Res, unsigned Op) { - validateTruncExt(Res, Op, true); - return buildInstr(TargetOpcode::G_ZEXT).addDef(Res).addUse(Op); +MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res, + const SrcOp &Op) { + return buildInstr(TargetOpcode::G_ZEXT, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildExtOrTrunc(unsigned ExtOpc, - unsigned Res, - unsigned Op) { +MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc, + const DstOp &Res, + const SrcOp &Op) { assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc || TargetOpcode::G_SEXT == ExtOpc) && "Expecting Extending Opc"); - assert(getMRI()->getType(Res).isScalar() || - getMRI()->getType(Res).isVector()); - assert(getMRI()->getType(Res).isScalar() == getMRI()->getType(Op).isScalar()); + assert(Res.getLLTTy(*getMRI()).isScalar() || + Res.getLLTTy(*getMRI()).isVector()); + assert(Res.getLLTTy(*getMRI()).isScalar() == + Op.getLLTTy(*getMRI()).isScalar()); unsigned Opcode = TargetOpcode::COPY; - if (getMRI()->getType(Res).getSizeInBits() > - getMRI()->getType(Op).getSizeInBits()) + if (Res.getLLTTy(*getMRI()).getSizeInBits() > + Op.getLLTTy(*getMRI()).getSizeInBits()) Opcode = ExtOpc; - else if (getMRI()->getType(Res).getSizeInBits() < - getMRI()->getType(Op).getSizeInBits()) + else if (Res.getLLTTy(*getMRI()).getSizeInBits() < + Op.getLLTTy(*getMRI()).getSizeInBits()) Opcode = TargetOpcode::G_TRUNC; else - assert(getMRI()->getType(Res) == getMRI()->getType(Op)); + assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI())); - return buildInstr(Opcode).addDef(Res).addUse(Op); + return buildInstr(Opcode, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildSExtOrTrunc(unsigned Res, - unsigned Op) { +MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(const DstOp &Res, + const SrcOp &Op) { return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildZExtOrTrunc(unsigned Res, - unsigned Op) { +MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(const DstOp &Res, + const SrcOp &Op) { return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildAnyExtOrTrunc(unsigned Res, - unsigned Op) { +MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc(const DstOp &Res, + const SrcOp &Op) { return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildCast(unsigned Dst, - unsigned Src) { - LLT SrcTy = getMRI()->getType(Src); - LLT DstTy = getMRI()->getType(Dst); +MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst, + const SrcOp &Src) { + LLT SrcTy = Src.getLLTTy(*getMRI()); + LLT DstTy = Dst.getLLTTy(*getMRI()); if (SrcTy == DstTy) return buildCopy(Dst, Src); @@ -406,11 +398,11 @@ MachineInstrBuilder MachineIRBuilderBase::buildCast(unsigned Dst, Opcode = TargetOpcode::G_BITCAST; } - return buildInstr(Opcode).addDef(Dst).addUse(Src); + return buildInstr(Opcode, Dst, Src); } -MachineInstrBuilder -MachineIRBuilderBase::buildExtract(unsigned Res, unsigned Src, uint64_t Index) { +MachineInstrBuilder MachineIRBuilder::buildExtract(unsigned Res, unsigned Src, + uint64_t Index) { #ifndef NDEBUG assert(getMRI()->getType(Src).isValid() && "invalid operand type"); assert(getMRI()->getType(Res).isValid() && "invalid operand type"); @@ -431,8 +423,8 @@ MachineIRBuilderBase::buildExtract(unsigned Res, unsigned Src, uint64_t Index) { .addImm(Index); } -void MachineIRBuilderBase::buildSequence(unsigned Res, ArrayRef<unsigned> Ops, - ArrayRef<uint64_t> Indices) { +void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops, + ArrayRef<uint64_t> Indices) { #ifndef NDEBUG assert(Ops.size() == Indices.size() && "incompatible args"); assert(!Ops.empty() && "invalid trivial sequence"); @@ -472,118 +464,67 @@ void MachineIRBuilderBase::buildSequence(unsigned Res, ArrayRef<unsigned> Ops, } } -MachineInstrBuilder MachineIRBuilderBase::buildUndef(unsigned Res) { - return buildInstr(TargetOpcode::G_IMPLICIT_DEF).addDef(Res); +MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) { + return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {}); } -MachineInstrBuilder MachineIRBuilderBase::buildMerge(unsigned Res, - ArrayRef<unsigned> Ops) { - -#ifndef NDEBUG - assert(!Ops.empty() && "invalid trivial sequence"); - LLT Ty = getMRI()->getType(Ops[0]); - for (auto Reg : Ops) - assert(getMRI()->getType(Reg) == Ty && "type mismatch in input list"); - assert(Ops.size() * getMRI()->getType(Ops[0]).getSizeInBits() == - getMRI()->getType(Res).getSizeInBits() && - "input operands do not cover output register"); -#endif - - if (Ops.size() == 1) - return buildCast(Res, Ops[0]); - - // If we're trying to merge vectors, we should use G_CONCAT_VECTORS instead. - if (getMRI()->getType(Res).isVector()) - return buildConcatVectors(Res, Ops); - - MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_MERGE_VALUES); - MIB.addDef(Res); - for (unsigned i = 0; i < Ops.size(); ++i) - MIB.addUse(Ops[i]); - return MIB; +MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res, + ArrayRef<unsigned> Ops) { + // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>, + // we need some temporary storage for the DstOp objects. Here we use a + // sufficiently large SmallVector to not go through the heap. + SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end()); + return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec); } -MachineInstrBuilder MachineIRBuilderBase::buildUnmerge(ArrayRef<unsigned> Res, - unsigned Op) { - -#ifndef NDEBUG - assert(!Res.empty() && "invalid trivial sequence"); - LLT Ty = getMRI()->getType(Res[0]); - for (auto Reg : Res) - assert(getMRI()->getType(Reg) == Ty && "type mismatch in input list"); - assert(Res.size() * getMRI()->getType(Res[0]).getSizeInBits() == - getMRI()->getType(Op).getSizeInBits() && - "input operands do not cover output register"); -#endif +MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res, + const SrcOp &Op) { + // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>, + // we need some temporary storage for the DstOp objects. Here we use a + // sufficiently large SmallVector to not go through the heap. + SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end()); + return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op); +} - MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_UNMERGE_VALUES); - for (unsigned i = 0; i < Res.size(); ++i) - MIB.addDef(Res[i]); - MIB.addUse(Op); - return MIB; +MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res, + const SrcOp &Op) { + // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<DstOp>, + // we need some temporary storage for the DstOp objects. Here we use a + // sufficiently large SmallVector to not go through the heap. + SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end()); + return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op); } -MachineInstrBuilder -MachineIRBuilderBase::buildBuildVector(unsigned Res, ArrayRef<unsigned> Ops) { -#ifndef NDEBUG - assert((!Ops.empty() || Ops.size() < 2) && "Must have at least 2 operands"); - assert(getMRI()->getType(Res).isVector() && "Res type must be a vector"); - LLT Ty = getMRI()->getType(Ops[0]); - for (auto Reg : Ops) - assert(getMRI()->getType(Reg) == Ty && "type mismatch in input list"); - assert(Ops.size() * Ty.getSizeInBits() == - getMRI()->getType(Res).getSizeInBits() && - "input scalars do not exactly cover the outpur vector register"); -#endif - MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_BUILD_VECTOR); - MIB.addDef(Res); - for (auto Op : Ops) - MIB.addUse(Op); - return MIB; +MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res, + ArrayRef<unsigned> Ops) { + // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>, + // we need some temporary storage for the DstOp objects. Here we use a + // sufficiently large SmallVector to not go through the heap. + SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end()); + return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec); } MachineInstrBuilder -MachineIRBuilderBase::buildBuildVectorTrunc(unsigned Res, - ArrayRef<unsigned> Ops) { -#ifndef NDEBUG - assert((!Ops.empty() || Ops.size() < 2) && "Must have at least 2 operands"); - LLT Ty = getMRI()->getType(Ops[0]); - for (auto Reg : Ops) - assert(getMRI()->getType(Reg) == Ty && "type mismatch in input list"); -#endif - if (getMRI()->getType(Ops[0]).getSizeInBits() == - getMRI()->getType(Res).getElementType().getSizeInBits()) - return buildBuildVector(Res, Ops); - MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC); - MIB.addDef(Res); - for (auto Op : Ops) - MIB.addUse(Op); - return MIB; +MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res, + ArrayRef<unsigned> Ops) { + // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>, + // we need some temporary storage for the DstOp objects. Here we use a + // sufficiently large SmallVector to not go through the heap. + SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end()); + return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec); } MachineInstrBuilder -MachineIRBuilderBase::buildConcatVectors(unsigned Res, ArrayRef<unsigned> Ops) { - #ifndef NDEBUG - assert((!Ops.empty() || Ops.size() < 2) && "Must have at least 2 operands"); - LLT Ty = getMRI()->getType(Ops[0]); - for (auto Reg : Ops) { - assert(getMRI()->getType(Reg).isVector() && "expected vector operand"); - assert(getMRI()->getType(Reg) == Ty && "type mismatch in input list"); - } - assert(Ops.size() * Ty.getSizeInBits() == - getMRI()->getType(Res).getSizeInBits() && - "input vectors do not exactly cover the outpur vector register"); - #endif - MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_CONCAT_VECTORS); - MIB.addDef(Res); - for (auto Op : Ops) - MIB.addUse(Op); - return MIB; +MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<unsigned> Ops) { + // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>, + // we need some temporary storage for the DstOp objects. Here we use a + // sufficiently large SmallVector to not go through the heap. + SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end()); + return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec); } -MachineInstrBuilder MachineIRBuilderBase::buildInsert(unsigned Res, - unsigned Src, unsigned Op, - unsigned Index) { +MachineInstrBuilder MachineIRBuilder::buildInsert(unsigned Res, unsigned Src, + unsigned Op, unsigned Index) { assert(Index + getMRI()->getType(Op).getSizeInBits() <= getMRI()->getType(Res).getSizeInBits() && "insertion past the end of a register"); @@ -600,9 +541,9 @@ MachineInstrBuilder MachineIRBuilderBase::buildInsert(unsigned Res, .addImm(Index); } -MachineInstrBuilder MachineIRBuilderBase::buildIntrinsic(Intrinsic::ID ID, - unsigned Res, - bool HasSideEffects) { +MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID, + unsigned Res, + bool HasSideEffects) { auto MIB = buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS : TargetOpcode::G_INTRINSIC); @@ -612,133 +553,52 @@ MachineInstrBuilder MachineIRBuilderBase::buildIntrinsic(Intrinsic::ID ID, return MIB; } -MachineInstrBuilder MachineIRBuilderBase::buildTrunc(unsigned Res, - unsigned Op) { - validateTruncExt(Res, Op, false); - return buildInstr(TargetOpcode::G_TRUNC).addDef(Res).addUse(Op); +MachineInstrBuilder MachineIRBuilder::buildTrunc(const DstOp &Res, + const SrcOp &Op) { + return buildInstr(TargetOpcode::G_TRUNC, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildFPTrunc(unsigned Res, - unsigned Op) { - validateTruncExt(Res, Op, false); - return buildInstr(TargetOpcode::G_FPTRUNC).addDef(Res).addUse(Op); +MachineInstrBuilder MachineIRBuilder::buildFPTrunc(const DstOp &Res, + const SrcOp &Op) { + return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildICmp(CmpInst::Predicate Pred, - unsigned Res, unsigned Op0, - unsigned Op1) { -#ifndef NDEBUG - assert(getMRI()->getType(Op0) == getMRI()->getType(Op0) && "type mismatch"); - assert(CmpInst::isIntPredicate(Pred) && "invalid predicate"); - if (getMRI()->getType(Op0).isScalar() || getMRI()->getType(Op0).isPointer()) - assert(getMRI()->getType(Res).isScalar() && "type mismatch"); - else - assert(getMRI()->getType(Res).isVector() && - getMRI()->getType(Res).getNumElements() == - getMRI()->getType(Op0).getNumElements() && - "type mismatch"); -#endif - - return buildInstr(TargetOpcode::G_ICMP) - .addDef(Res) - .addPredicate(Pred) - .addUse(Op0) - .addUse(Op1); +MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred, + const DstOp &Res, + const SrcOp &Op0, + const SrcOp &Op1) { + return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1}); } -MachineInstrBuilder MachineIRBuilderBase::buildFCmp(CmpInst::Predicate Pred, - unsigned Res, unsigned Op0, - unsigned Op1) { -#ifndef NDEBUG - assert((getMRI()->getType(Op0).isScalar() || - getMRI()->getType(Op0).isVector()) && - "invalid operand type"); - assert(getMRI()->getType(Op0) == getMRI()->getType(Op1) && "type mismatch"); - assert(CmpInst::isFPPredicate(Pred) && "invalid predicate"); - if (getMRI()->getType(Op0).isScalar()) - assert(getMRI()->getType(Res).isScalar() && "type mismatch"); - else - assert(getMRI()->getType(Res).isVector() && - getMRI()->getType(Res).getNumElements() == - getMRI()->getType(Op0).getNumElements() && - "type mismatch"); -#endif +MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred, + const DstOp &Res, + const SrcOp &Op0, + const SrcOp &Op1) { - return buildInstr(TargetOpcode::G_FCMP) - .addDef(Res) - .addPredicate(Pred) - .addUse(Op0) - .addUse(Op1); + return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}); } -MachineInstrBuilder MachineIRBuilderBase::buildSelect(unsigned Res, - unsigned Tst, - unsigned Op0, - unsigned Op1) { -#ifndef NDEBUG - LLT ResTy = getMRI()->getType(Res); - assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) && - "invalid operand type"); - assert(ResTy == getMRI()->getType(Op0) && ResTy == getMRI()->getType(Op1) && - "type mismatch"); - if (ResTy.isScalar() || ResTy.isPointer()) - assert(getMRI()->getType(Tst).isScalar() && "type mismatch"); - else - assert((getMRI()->getType(Tst).isScalar() || - (getMRI()->getType(Tst).isVector() && - getMRI()->getType(Tst).getNumElements() == - getMRI()->getType(Op0).getNumElements())) && - "type mismatch"); -#endif +MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res, + const SrcOp &Tst, + const SrcOp &Op0, + const SrcOp &Op1) { - return buildInstr(TargetOpcode::G_SELECT) - .addDef(Res) - .addUse(Tst) - .addUse(Op0) - .addUse(Op1); + return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}); } MachineInstrBuilder -MachineIRBuilderBase::buildInsertVectorElement(unsigned Res, unsigned Val, - unsigned Elt, unsigned Idx) { -#ifndef NDEBUG - LLT ResTy = getMRI()->getType(Res); - LLT ValTy = getMRI()->getType(Val); - LLT EltTy = getMRI()->getType(Elt); - LLT IdxTy = getMRI()->getType(Idx); - assert(ResTy.isVector() && ValTy.isVector() && "invalid operand type"); - assert(IdxTy.isScalar() && "invalid operand type"); - assert(ResTy.getNumElements() == ValTy.getNumElements() && "type mismatch"); - assert(ResTy.getElementType() == EltTy && "type mismatch"); -#endif - - return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT) - .addDef(Res) - .addUse(Val) - .addUse(Elt) - .addUse(Idx); +MachineIRBuilder::buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, + const SrcOp &Elt, const SrcOp &Idx) { + return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx}); } MachineInstrBuilder -MachineIRBuilderBase::buildExtractVectorElement(unsigned Res, unsigned Val, - unsigned Idx) { -#ifndef NDEBUG - LLT ResTy = getMRI()->getType(Res); - LLT ValTy = getMRI()->getType(Val); - LLT IdxTy = getMRI()->getType(Idx); - assert(ValTy.isVector() && "invalid operand type"); - assert((ResTy.isScalar() || ResTy.isPointer()) && "invalid operand type"); - assert(IdxTy.isScalar() && "invalid operand type"); - assert(ValTy.getElementType() == ResTy && "type mismatch"); -#endif - - return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT) - .addDef(Res) - .addUse(Val) - .addUse(Idx); +MachineIRBuilder::buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, + const SrcOp &Idx) { + return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx}); } -MachineInstrBuilder MachineIRBuilderBase::buildAtomicCmpXchgWithSuccess( +MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchgWithSuccess( unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal, unsigned NewVal, MachineMemOperand &MMO) { #ifndef NDEBUG @@ -766,9 +626,9 @@ MachineInstrBuilder MachineIRBuilderBase::buildAtomicCmpXchgWithSuccess( } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr, - unsigned CmpVal, unsigned NewVal, - MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr, + unsigned CmpVal, unsigned NewVal, + MachineMemOperand &MMO) { #ifndef NDEBUG LLT OldValResTy = getMRI()->getType(OldValRes); LLT AddrTy = getMRI()->getType(Addr); @@ -790,10 +650,11 @@ MachineIRBuilderBase::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr, .addMemOperand(&MMO); } -MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMW(unsigned Opcode, unsigned OldValRes, - unsigned Addr, unsigned Val, - MachineMemOperand &MMO) { +MachineInstrBuilder MachineIRBuilder::buildAtomicRMW(unsigned Opcode, + unsigned OldValRes, + unsigned Addr, + unsigned Val, + MachineMemOperand &MMO) { #ifndef NDEBUG LLT OldValResTy = getMRI()->getType(OldValRes); LLT AddrTy = getMRI()->getType(Addr); @@ -812,74 +673,75 @@ MachineIRBuilderBase::buildAtomicRMW(unsigned Opcode, unsigned OldValRes, } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWSub(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWSub(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWNand(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWNand(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val, MMO); } -MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWOr(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr(unsigned OldValRes, + unsigned Addr, + unsigned Val, + MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWXor(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWXor(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWMax(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWMax(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWMin(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWMin(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildBlockAddress(unsigned Res, const BlockAddress *BA) { +MachineIRBuilder::buildBlockAddress(unsigned Res, const BlockAddress *BA) { #ifndef NDEBUG assert(getMRI()->getType(Res).isPointer() && "invalid res type"); #endif @@ -887,12 +749,9 @@ MachineIRBuilderBase::buildBlockAddress(unsigned Res, const BlockAddress *BA) { return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA); } -void MachineIRBuilderBase::validateTruncExt(unsigned Dst, unsigned Src, - bool IsExtend) { +void MachineIRBuilder::validateTruncExt(const LLT &DstTy, const LLT &SrcTy, + bool IsExtend) { #ifndef NDEBUG - LLT SrcTy = getMRI()->getType(Src); - LLT DstTy = getMRI()->getType(Dst); - if (DstTy.isVector()) { assert(SrcTy.isVector() && "mismatched cast between vector and non-vector"); assert(SrcTy.getNumElements() == DstTy.getNumElements() && @@ -908,3 +767,233 @@ void MachineIRBuilderBase::validateTruncExt(unsigned Dst, unsigned Src, "invalid widening trunc"); #endif } + +void MachineIRBuilder::validateSelectOp(const LLT &ResTy, const LLT &TstTy, + const LLT &Op0Ty, const LLT &Op1Ty) { +#ifndef NDEBUG + assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) && + "invalid operand type"); + assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch"); + if (ResTy.isScalar() || ResTy.isPointer()) + assert(TstTy.isScalar() && "type mismatch"); + else + assert((TstTy.isScalar() || + (TstTy.isVector() && + TstTy.getNumElements() == Op0Ty.getNumElements())) && + "type mismatch"); +#endif +} + +MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc, + ArrayRef<DstOp> DstOps, + ArrayRef<SrcOp> SrcOps) { + switch (Opc) { + default: + break; + case TargetOpcode::G_SELECT: { + assert(DstOps.size() == 1 && "Invalid select"); + assert(SrcOps.size() == 3 && "Invalid select"); + validateSelectOp( + DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()), + SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI())); + break; + } + case TargetOpcode::G_ADD: + case TargetOpcode::G_AND: + case TargetOpcode::G_ASHR: + case TargetOpcode::G_LSHR: + case TargetOpcode::G_MUL: + case TargetOpcode::G_OR: + case TargetOpcode::G_SHL: + case TargetOpcode::G_SUB: + case TargetOpcode::G_XOR: + case TargetOpcode::G_UDIV: + case TargetOpcode::G_SDIV: + case TargetOpcode::G_UREM: + case TargetOpcode::G_SREM: { + // All these are binary ops. + assert(DstOps.size() == 1 && "Invalid Dst"); + assert(SrcOps.size() == 2 && "Invalid Srcs"); + validateBinaryOp(DstOps[0].getLLTTy(*getMRI()), + SrcOps[0].getLLTTy(*getMRI()), + SrcOps[1].getLLTTy(*getMRI())); + break; + case TargetOpcode::G_SEXT: + case TargetOpcode::G_ZEXT: + case TargetOpcode::G_ANYEXT: + assert(DstOps.size() == 1 && "Invalid Dst"); + assert(SrcOps.size() == 1 && "Invalid Srcs"); + validateTruncExt(DstOps[0].getLLTTy(*getMRI()), + SrcOps[0].getLLTTy(*getMRI()), true); + break; + case TargetOpcode::G_TRUNC: + case TargetOpcode::G_FPTRUNC: + assert(DstOps.size() == 1 && "Invalid Dst"); + assert(SrcOps.size() == 1 && "Invalid Srcs"); + validateTruncExt(DstOps[0].getLLTTy(*getMRI()), + SrcOps[0].getLLTTy(*getMRI()), false); + break; + } + case TargetOpcode::COPY: + assert(DstOps.size() == 1 && "Invalid Dst"); + assert(SrcOps.size() == 1 && "Invalid Srcs"); + assert(DstOps[0].getLLTTy(*getMRI()) == LLT() || + SrcOps[0].getLLTTy(*getMRI()) == LLT() || + DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())); + break; + case TargetOpcode::G_FCMP: + case TargetOpcode::G_ICMP: { + assert(DstOps.size() == 1 && "Invalid Dst Operands"); + assert(SrcOps.size() == 3 && "Invalid Src Operands"); + // For F/ICMP, the first src operand is the predicate, followed by + // the two comparands. + assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate && + "Expecting predicate"); + assert([&]() -> bool { + CmpInst::Predicate Pred = SrcOps[0].getPredicate(); + return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred) + : CmpInst::isFPPredicate(Pred); + }() && "Invalid predicate"); + assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) && + "Type mismatch"); + assert([&]() -> bool { + LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI()); + LLT DstTy = DstOps[0].getLLTTy(*getMRI()); + if (Op0Ty.isScalar() || Op0Ty.isPointer()) + return DstTy.isScalar(); + else + return DstTy.isVector() && + DstTy.getNumElements() == Op0Ty.getNumElements(); + }() && "Type Mismatch"); + break; + } + case TargetOpcode::G_UNMERGE_VALUES: { + assert(!DstOps.empty() && "Invalid trivial sequence"); + assert(SrcOps.size() == 1 && "Invalid src for Unmerge"); + assert(std::all_of(DstOps.begin(), DstOps.end(), + [&, this](const DstOp &Op) { + return Op.getLLTTy(*getMRI()) == + DstOps[0].getLLTTy(*getMRI()); + }) && + "type mismatch in output list"); + assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() == + SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() && + "input operands do not cover output register"); + break; + } + case TargetOpcode::G_MERGE_VALUES: { + assert(!SrcOps.empty() && "invalid trivial sequence"); + assert(DstOps.size() == 1 && "Invalid Dst"); + assert(std::all_of(SrcOps.begin(), SrcOps.end(), + [&, this](const SrcOp &Op) { + return Op.getLLTTy(*getMRI()) == + SrcOps[0].getLLTTy(*getMRI()); + }) && + "type mismatch in input list"); + assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() == + DstOps[0].getLLTTy(*getMRI()).getSizeInBits() && + "input operands do not cover output register"); + if (SrcOps.size() == 1) + return buildCast(DstOps[0], SrcOps[0]); + if (DstOps[0].getLLTTy(*getMRI()).isVector()) + return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps); + break; + } + case TargetOpcode::G_EXTRACT_VECTOR_ELT: { + assert(DstOps.size() == 1 && "Invalid Dst size"); + assert(SrcOps.size() == 2 && "Invalid Src size"); + assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type"); + assert((DstOps[0].getLLTTy(*getMRI()).isScalar() || + DstOps[0].getLLTTy(*getMRI()).isPointer()) && + "Invalid operand type"); + assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type"); + assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() == + DstOps[0].getLLTTy(*getMRI()) && + "Type mismatch"); + break; + } + case TargetOpcode::G_INSERT_VECTOR_ELT: { + assert(DstOps.size() == 1 && "Invalid dst size"); + assert(SrcOps.size() == 3 && "Invalid src size"); + assert(DstOps[0].getLLTTy(*getMRI()).isVector() && + SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type"); + assert(DstOps[0].getLLTTy(*getMRI()).getElementType() == + SrcOps[1].getLLTTy(*getMRI()) && + "Type mismatch"); + assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index"); + assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() == + SrcOps[0].getLLTTy(*getMRI()).getNumElements() && + "Type mismatch"); + break; + } + case TargetOpcode::G_BUILD_VECTOR: { + assert((!SrcOps.empty() || SrcOps.size() < 2) && + "Must have at least 2 operands"); + assert(DstOps.size() == 1 && "Invalid DstOps"); + assert(DstOps[0].getLLTTy(*getMRI()).isVector() && + "Res type must be a vector"); + assert(std::all_of(SrcOps.begin(), SrcOps.end(), + [&, this](const SrcOp &Op) { + return Op.getLLTTy(*getMRI()) == + SrcOps[0].getLLTTy(*getMRI()); + }) && + "type mismatch in input list"); + assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() == + DstOps[0].getLLTTy(*getMRI()).getSizeInBits() && + "input scalars do not exactly cover the outpur vector register"); + break; + } + case TargetOpcode::G_BUILD_VECTOR_TRUNC: { + assert((!SrcOps.empty() || SrcOps.size() < 2) && + "Must have at least 2 operands"); + assert(DstOps.size() == 1 && "Invalid DstOps"); + assert(DstOps[0].getLLTTy(*getMRI()).isVector() && + "Res type must be a vector"); + assert(std::all_of(SrcOps.begin(), SrcOps.end(), + [&, this](const SrcOp &Op) { + return Op.getLLTTy(*getMRI()) == + SrcOps[0].getLLTTy(*getMRI()); + }) && + "type mismatch in input list"); + if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() == + DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits()) + return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps); + break; + } + case TargetOpcode::G_CONCAT_VECTORS: { + assert(DstOps.size() == 1 && "Invalid DstOps"); + assert((!SrcOps.empty() || SrcOps.size() < 2) && + "Must have at least 2 operands"); + assert(std::all_of(SrcOps.begin(), SrcOps.end(), + [&, this](const SrcOp &Op) { + return (Op.getLLTTy(*getMRI()).isVector() && + Op.getLLTTy(*getMRI()) == + SrcOps[0].getLLTTy(*getMRI())); + }) && + "type mismatch in input list"); + assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() == + DstOps[0].getLLTTy(*getMRI()).getSizeInBits() && + "input vectors do not exactly cover the outpur vector register"); + break; + } + case TargetOpcode::G_UADDE: { + assert(DstOps.size() == 2 && "Invalid no of dst operands"); + assert(SrcOps.size() == 3 && "Invalid no of src operands"); + assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand"); + assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) && + (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) && + "Invalid operand"); + assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand"); + assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) && + "type mismatch"); + break; + } + } + + auto MIB = buildInstr(Opc); + for (const DstOp &Op : DstOps) + Op.addDefToMIB(*getMRI(), MIB); + for (const SrcOp &Op : SrcOps) + Op.addSrcToMIB(MIB); + return MIB; +} diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 3741dcdcd54..90258cc1555 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -676,7 +676,7 @@ void AArch64InstructionSelector::materializeLargeCMVal( MachineRegisterInfo &MRI = MF.getRegInfo(); MachineIRBuilder MIB(I); - auto MovZ = MIB.buildInstr(AArch64::MOVZXi, &AArch64::GPR64RegClass); + auto MovZ = MIB.buildInstr(AArch64::MOVZXi, {&AArch64::GPR64RegClass}, {}); MovZ->addOperand(MF, I.getOperand(1)); MovZ->getOperand(1).setTargetFlags(OpFlags | AArch64II::MO_G0 | AArch64II::MO_NC); diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp index fbc15649c8a..4ac94775396 100644 --- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp +++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp @@ -258,8 +258,8 @@ bool MipsInstructionSelector::select(MachineInstr &I, MachineIRBuilder B(I); for (const struct Instr &Instruction : Instructions) { - MachineInstrBuilder MIB = - B.buildInstr(Instruction.Opcode, Instruction.Def, Instruction.LHS); + MachineInstrBuilder MIB = B.buildInstr( + Instruction.Opcode, {Instruction.Def}, {Instruction.LHS}); if (Instruction.hasImm()) MIB.addImm(Instruction.RHS); diff --git a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp index 9ab5a80f5ae..997bd926305 100644 --- a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp +++ b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp @@ -28,7 +28,8 @@ TEST_F(LegalizerHelperTest, LowerBitCountingCTTZ0) { DefineLegalizerInfo( A, { getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF).legalFor({s64}); }); // Build Instr - auto MIBCTTZ = B.buildInstr(TargetOpcode::G_CTTZ, LLT::scalar(64), Copies[0]); + auto MIBCTTZ = + B.buildInstr(TargetOpcode::G_CTTZ, {LLT::scalar(64)}, {Copies[0]}); AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer); @@ -57,7 +58,8 @@ TEST_F(LegalizerHelperTest, LowerBitCountingCTTZ1) { DefineLegalizerInfo(A, { getActionDefinitionsBuilder(G_CTLZ).legalFor({s64}); }); // Build Instr - auto MIBCTTZ = B.buildInstr(TargetOpcode::G_CTTZ, LLT::scalar(64), Copies[0]); + auto MIBCTTZ = + B.buildInstr(TargetOpcode::G_CTTZ, {LLT::scalar(64)}, {Copies[0]}); AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer); @@ -88,7 +90,8 @@ TEST_F(LegalizerHelperTest, LowerBitCountingCTTZ2) { DefineLegalizerInfo( A, { getActionDefinitionsBuilder(G_CTPOP).legalFor({s64}); }); // Build - auto MIBCTTZ = B.buildInstr(TargetOpcode::G_CTTZ, LLT::scalar(64), Copies[0]); + auto MIBCTTZ = + B.buildInstr(TargetOpcode::G_CTTZ, {LLT::scalar(64)}, {Copies[0]}); AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer); @@ -116,8 +119,8 @@ TEST_F(LegalizerHelperTest, LowerBitCountingCTTZ3) { DefineLegalizerInfo(A, { getActionDefinitionsBuilder(G_CTTZ).legalFor({s64}); }); // Build - auto MIBCTTZ = - B.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, LLT::scalar(64), Copies[0]); + auto MIBCTTZ = B.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, + {LLT::scalar(64)}, {Copies[0]}); AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer); @@ -141,7 +144,8 @@ TEST_F(LegalizerHelperTest, LowerBitCountingCTLZ0) { DefineLegalizerInfo( A, { getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF).legalFor({s64}); }); // Build - auto MIBCTLZ = B.buildInstr(TargetOpcode::G_CTLZ, LLT::scalar(64), Copies[0]); + auto MIBCTLZ = + B.buildInstr(TargetOpcode::G_CTLZ, {LLT::scalar(64)}, {Copies[0]}); AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer); @@ -169,7 +173,8 @@ TEST_F(LegalizerHelperTest, LowerBitCountingCTLZLibcall) { DefineLegalizerInfo( A, { getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF).libcallFor({s64}); }); // Build - auto MIBCTLZ = B.buildInstr(TargetOpcode::G_CTLZ, LLT::scalar(64), Copies[0]); + auto MIBCTLZ = + B.buildInstr(TargetOpcode::G_CTLZ, {LLT::scalar(64)}, {Copies[0]}); AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer); @@ -200,7 +205,7 @@ TEST_F(LegalizerHelperTest, LowerBitCountingCTLZ1) { // Trunc it to s8. LLT s8{LLT::scalar(8)}; auto MIBTrunc = B.buildTrunc(s8, Copies[0]); - auto MIBCTLZ = B.buildInstr(TargetOpcode::G_CTLZ, s8, MIBTrunc); + auto MIBCTLZ = B.buildInstr(TargetOpcode::G_CTLZ, {s8}, {MIBTrunc}); AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer); @@ -240,7 +245,7 @@ TEST_F(LegalizerHelperTest, WidenBitCountingCTLZ) { LLT s8{LLT::scalar(8)}; LLT s16{LLT::scalar(16)}; auto MIBTrunc = B.buildTrunc(s8, Copies[0]); - auto MIBCTLZ = B.buildInstr(TargetOpcode::G_CTLZ, s8, MIBTrunc); + auto MIBCTLZ = B.buildInstr(TargetOpcode::G_CTLZ, {s8}, {MIBTrunc}); AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer); @@ -273,7 +278,8 @@ TEST_F(LegalizerHelperTest, WidenBitCountingCTLZZeroUndef) { LLT s8{LLT::scalar(8)}; LLT s16{LLT::scalar(16)}; auto MIBTrunc = B.buildTrunc(s8, Copies[0]); - auto MIBCTLZ_ZU = B.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, s8, MIBTrunc); + auto MIBCTLZ_ZU = + B.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {s8}, {MIBTrunc}); AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer); @@ -306,7 +312,7 @@ TEST_F(LegalizerHelperTest, WidenBitCountingCTPOP) { LLT s8{LLT::scalar(8)}; LLT s16{LLT::scalar(16)}; auto MIBTrunc = B.buildTrunc(s8, Copies[0]); - auto MIBCTPOP = B.buildInstr(TargetOpcode::G_CTPOP, s8, MIBTrunc); + auto MIBCTPOP = B.buildInstr(TargetOpcode::G_CTPOP, {s8}, {MIBTrunc}); AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer); @@ -338,7 +344,7 @@ TEST_F(LegalizerHelperTest, WidenBitCountingCTTZ_ZERO_UNDEF) { LLT s16{LLT::scalar(16)}; auto MIBTrunc = B.buildTrunc(s8, Copies[0]); auto MIBCTTZ_ZERO_UNDEF = - B.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, s8, MIBTrunc); + B.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {s8}, {MIBTrunc}); AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer); @@ -369,7 +375,7 @@ TEST_F(LegalizerHelperTest, WidenBitCountingCTTZ) { LLT s8{LLT::scalar(8)}; LLT s16{LLT::scalar(16)}; auto MIBTrunc = B.buildTrunc(s8, Copies[0]); - auto MIBCTTZ = B.buildInstr(TargetOpcode::G_CTTZ, s8, MIBTrunc); + auto MIBCTTZ = B.buildInstr(TargetOpcode::G_CTTZ, {s8}, {MIBTrunc}); AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer); @@ -402,10 +408,8 @@ TEST_F(LegalizerHelperTest, WidenUADDO) { LLT s16{LLT::scalar(16)}; auto MIBTrunc = B.buildTrunc(s8, Copies[0]); unsigned CarryReg = MRI->createGenericVirtualRegister(LLT::scalar(1)); - auto MIBUAddO = B.buildInstr(TargetOpcode::G_UADDO, s8) - .addDef(CarryReg) - .addUse(MIBTrunc->getOperand(0).getReg()) - .addUse(MIBTrunc->getOperand(0).getReg()); + auto MIBUAddO = + B.buildInstr(TargetOpcode::G_UADDO, {s8, CarryReg}, {MIBTrunc, MIBTrunc}); AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer); @@ -441,10 +445,8 @@ TEST_F(LegalizerHelperTest, WidenUSUBO) { LLT s16{LLT::scalar(16)}; auto MIBTrunc = B.buildTrunc(s8, Copies[0]); unsigned CarryReg = MRI->createGenericVirtualRegister(LLT::scalar(1)); - auto MIBUSUBO = B.buildInstr(TargetOpcode::G_USUBO, s8) - .addDef(CarryReg) - .addUse(MIBTrunc->getOperand(0).getReg()) - .addUse(MIBTrunc->getOperand(0).getReg()); + auto MIBUSUBO = + B.buildInstr(TargetOpcode::G_USUBO, {s8, CarryReg}, {MIBTrunc, MIBTrunc}); AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer); diff --git a/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp b/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp index 1f3a690ad01..466a2dd6b06 100644 --- a/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp +++ b/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp @@ -204,8 +204,8 @@ TEST(PatternMatchInstr, MatchBinaryOp) { m_GSub(m_ICst(Cst), m_Reg(Src0))); ASSERT_FALSE(match); - auto MIBFMul = B.buildInstr(TargetOpcode::G_FMUL, s64, Copies[0], - B.buildConstant(s64, 42)); + auto MIBFMul = B.buildInstr(TargetOpcode::G_FMUL, {s64}, + {Copies[0], B.buildConstant(s64, 42)}); // Match and test commutativity for FMUL. match = mi_match(MIBFMul->getOperand(0).getReg(), MRI, m_GFMul(m_ICst(Cst), m_Reg(Src0))); @@ -214,8 +214,8 @@ TEST(PatternMatchInstr, MatchBinaryOp) { ASSERT_EQ(Src0, Copies[0]); // FSUB - auto MIBFSub = B.buildInstr(TargetOpcode::G_FSUB, s64, Copies[0], - B.buildConstant(s64, 42)); + auto MIBFSub = B.buildInstr(TargetOpcode::G_FSUB, {s64}, + {Copies[0], B.buildConstant(s64, 42)}); match = mi_match(MIBFSub->getOperand(0).getReg(), MRI, m_GFSub(m_Reg(Src0), m_Reg())); ASSERT_TRUE(match); @@ -249,8 +249,8 @@ TEST(PatternMatchInstr, MatchBinaryOp) { ASSERT_TRUE(match); ASSERT_EQ(Cst, 1); auto MIBCAdd1 = - CFB.buildInstr(TargetOpcode::G_ADD, s32, CFB.buildConstant(s32, 0), - CFB.buildConstant(s32, 1)); + CFB.buildInstr(TargetOpcode::G_ADD, {s32}, + {CFB.buildConstant(s32, 0), CFB.buildConstant(s32, 1)}); // This should be a constant now. match = mi_match(MIBCAdd1->getOperand(0).getReg(), MRI, m_ICst(Cst)); ASSERT_TRUE(match); @@ -261,8 +261,8 @@ TEST(PatternMatchInstr, MatchBinaryOp) { ConstantFoldingMIRBuilder CFB1(*MF); CFB1.setInsertPt(*EntryMBB, EntryMBB->end()); auto MIBCSub = - CFB1.buildInstr(TargetOpcode::G_SUB, s32, CFB1.buildConstant(s32, 1), - CFB1.buildConstant(s32, 1)); + CFB1.buildInstr(TargetOpcode::G_SUB, {s32}, + {CFB1.buildConstant(s32, 1), CFB1.buildConstant(s32, 1)}); // This should be a constant now. match = mi_match(MIBCSub->getOperand(0).getReg(), MRI, m_ICst(Cst)); ASSERT_TRUE(match); @@ -289,12 +289,12 @@ TEST(PatternMatchInstr, MatchFPUnaryOp) { auto Copy0s32 = B.buildFPTrunc(s32, Copies[0]); // Match G_FABS. - auto MIBFabs = B.buildInstr(TargetOpcode::G_FABS, s32, Copy0s32); + auto MIBFabs = B.buildInstr(TargetOpcode::G_FABS, {s32}, {Copy0s32}); bool match = mi_match(MIBFabs->getOperand(0).getReg(), MRI, m_GFabs(m_Reg())); ASSERT_TRUE(match); unsigned Src; - auto MIBFNeg = B.buildInstr(TargetOpcode::G_FNEG, s32, Copy0s32); + auto MIBFNeg = B.buildInstr(TargetOpcode::G_FNEG, {s32}, {Copy0s32}); match = mi_match(MIBFNeg->getOperand(0).getReg(), MRI, m_GFNeg(m_Reg(Src))); ASSERT_TRUE(match); ASSERT_EQ(Src, Copy0s32->getOperand(0).getReg()); |
