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-rw-r--r--llvm/include/llvm/Target/TargetInstrPredicate.td3
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/include/llvm/Target/TargetInstrPredicate.td b/llvm/include/llvm/Target/TargetInstrPredicate.td
index e6e5c06cd03..d38279b0d65 100644
--- a/llvm/include/llvm/Target/TargetInstrPredicate.td
+++ b/llvm/include/llvm/Target/TargetInstrPredicate.td
@@ -111,6 +111,9 @@ class CheckRegOperand<int Index, Register R> : MCOperandPredicate<Index> {
Register Reg = R;
}
+// Check if register operand at index `Index` is the invalid register.
+class CheckInvalidRegOperand<int Index> : MCOperandPredicate<Index>;
+
// Check that the operand at position `Index` is immediate `Imm`.
class CheckImmOperand<int Index, int Imm> : MCOperandPredicate<Index> {
int ImmVal = Imm;
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