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-rw-r--r--llvm/lib/Target/ARM/ARM.td1
-rw-r--r--llvm/test/CodeGen/ARM/cortexr52-misched-basic.ll2
2 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index ecb2ef2351d..477f45fe24b 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -999,6 +999,7 @@ def : ProcNoItin<"kryo", [ARMv8a, ProcKryo,
FeatureCRC]>;
def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52,
+ FeatureUseMISched,
FeatureFPAO]>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/ARM/cortexr52-misched-basic.ll b/llvm/test/CodeGen/ARM/cortexr52-misched-basic.ll
index 0edc6653a03..c6bff0c9d5a 100644
--- a/llvm/test/CodeGen/ARM/cortexr52-misched-basic.ll
+++ b/llvm/test/CodeGen/ARM/cortexr52-misched-basic.ll
@@ -1,5 +1,5 @@
; REQUIRES: asserts
-; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
;
; Check the latency for instructions for both generic and cortex-r52.
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