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-rw-r--r--llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp6
-rw-r--r--llvm/test/CodeGen/Mips/micromips-delay-slot.ll4
2 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
index 2c384b8addb..fe53cad56a7 100644
--- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -562,6 +562,12 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
bool InMicroMipsMode = STI.inMicroMipsMode();
const MipsInstrInfo *TII = STI.getInstrInfo();
+ if (InMicroMipsMode && STI.hasMips32r6()) {
+ // This is microMIPS32r6 or microMIPS64r6 processor. Delay slot for
+ // branching instructions is not needed.
+ return Changed;
+ }
+
for (Iter I = MBB.begin(); I != MBB.end(); ++I) {
if (!hasUnoccupiedSlot(&*I))
continue;
diff --git a/llvm/test/CodeGen/Mips/micromips-delay-slot.ll b/llvm/test/CodeGen/Mips/micromips-delay-slot.ll
index ef654623283..5c6aa36a413 100644
--- a/llvm/test/CodeGen/Mips/micromips-delay-slot.ll
+++ b/llvm/test/CodeGen/Mips/micromips-delay-slot.ll
@@ -1,5 +1,7 @@
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=static -O2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \
+; RUN: -relocation-model=static -O2 < %s | FileCheck %s -check-prefix=CHECK-MMR6
; Function Attrs: nounwind
define i32 @foo(i32 signext %a) #0 {
@@ -16,3 +18,5 @@ declare i32 @bar(i32 signext) #1
; CHECK: jals
; CHECK-NEXT: sll16
+; CHECK-MMR6: jal
+; CHECK-MMR6-NOT: sll16
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