diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/variadic.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/NVPTX/vec-param-load.ll | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/MachineSink-DbgValue.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/bt.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/i64-mem-copy.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/pr16031.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/sse2.ll | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/v2f32.ll | 2 |
10 files changed, 20 insertions, 15 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index e40a7c44ade..6c8e2f83a4f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -892,6 +892,7 @@ void SelectionDAGBuilder::clear() { PendingExports.clear(); CurInst = NULL; HasTailCall = false; + SDNodeOrder = LowestSDNodeOrder; } /// clearDanglingDebugInfo - Clear the dangling debug information diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h index d67c84664eb..d32d13f343d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h @@ -488,6 +488,10 @@ private: private: const TargetMachine &TM; public: + /// Lowest valid SDNodeOrder. The special case 0 is reserved for scheduling + /// nodes without a corresponding SDNode. + static const unsigned LowestSDNodeOrder = 1; + SelectionDAG &DAG; const DataLayout *TD; AliasAnalysis *AA; @@ -534,7 +538,7 @@ public: SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo, CodeGenOpt::Level ol) - : CurInst(NULL), SDNodeOrder(0), TM(dag.getTarget()), + : CurInst(NULL), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()), DAG(dag), FuncInfo(funcinfo), OptLevel(ol), HasTailCall(false) { } diff --git a/llvm/test/CodeGen/AArch64/variadic.ll b/llvm/test/CodeGen/AArch64/variadic.ll index f3d376beeb2..1ceaf5ff516 100644 --- a/llvm/test/CodeGen/AArch64/variadic.ll +++ b/llvm/test/CodeGen/AArch64/variadic.ll @@ -10,14 +10,12 @@ declare void @llvm.va_start(i8*) define void @test_simple(i32 %n, ...) { ; CHECK-LABEL: test_simple: ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]] -; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var ; CHECK: mov x[[FPRBASE:[0-9]+]], sp ; CHECK: str q7, [x[[FPRBASE]], #112] ; CHECK: add x[[GPRBASE:[0-9]+]], sp, #[[GPRFROMSP:[0-9]+]] ; CHECK: str x7, [x[[GPRBASE]], #48] ; CHECK-NOFP: sub sp, sp, #[[STACKSIZE:[0-9]+]] -; CHECK-NOFP: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var ; CHECK-NOFP: add x[[GPRBASE:[0-9]+]], sp, #[[GPRFROMSP:[0-9]+]] ; CHECK-NOFP: str x7, [x[[GPRBASE]], #48] ; CHECK-NOFP-NOT: str q7, @@ -27,8 +25,10 @@ define void @test_simple(i32 %n, ...) { ; CHECK: str q0, [sp] ; CHECK: str x1, [sp, #[[GPRFROMSP]]] +; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var ; CHECK-NOFP-NOT: str q0, [sp] +; CHECK-NOFP: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var %addr = bitcast %va_list* @var to i8* call void @llvm.va_start(i8* %addr) diff --git a/llvm/test/CodeGen/NVPTX/vec-param-load.ll b/llvm/test/CodeGen/NVPTX/vec-param-load.ll index a384348a659..4193ac4085c 100644 --- a/llvm/test/CodeGen/NVPTX/vec-param-load.ll +++ b/llvm/test/CodeGen/NVPTX/vec-param-load.ll @@ -5,9 +5,9 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 define <16 x float> @foo(<16 x float> %a) { ; Make sure we index into vectors properly -; CHECK: ld.param.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}, [foo_param_0]; -; CHECK: ld.param.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}, [foo_param_0+16]; -; CHECK: ld.param.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}, [foo_param_0+32]; ; CHECK: ld.param.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}, [foo_param_0+48]; +; CHECK: ld.param.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}, [foo_param_0+32]; +; CHECK: ld.param.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}, [foo_param_0+16]; +; CHECK: ld.param.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}, [foo_param_0]; ret <16 x float> %a } diff --git a/llvm/test/CodeGen/X86/MachineSink-DbgValue.ll b/llvm/test/CodeGen/X86/MachineSink-DbgValue.ll index 584e644ed51..4ce2fb3dcaf 100644 --- a/llvm/test/CodeGen/X86/MachineSink-DbgValue.ll +++ b/llvm/test/CodeGen/X86/MachineSink-DbgValue.ll @@ -13,8 +13,8 @@ define i32 @foo(i32 %i, i32* nocapture %c) nounwind uwtable readonly ssp { bb1: ; preds = %0 ;CHECK: DEBUG_VALUE: a -;CHECK-NEXT: .loc 1 5 5 -;CHECK-NEXT: addl +;CHECK: .loc 1 5 5 +;CHECK-NEXT: addl %gh = add nsw i32 %ab, 2, !dbg !16 br label %bb2, !dbg !16 diff --git a/llvm/test/CodeGen/X86/bt.ll b/llvm/test/CodeGen/X86/bt.ll index f12a3543b07..036ec0acc6e 100644 --- a/llvm/test/CodeGen/X86/bt.ll +++ b/llvm/test/CodeGen/X86/bt.ll @@ -20,7 +20,7 @@ define void @test2(i32 %x, i32 %n) nounwind { entry: ; CHECK: test2 -; CHECK: btl %eax, %ecx +; CHECK: btl %ecx, %eax ; CHECK: jb %tmp29 = lshr i32 %x, %n ; <i32> [#uses=1] %tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1] diff --git a/llvm/test/CodeGen/X86/i64-mem-copy.ll b/llvm/test/CodeGen/X86/i64-mem-copy.ll index dce12ae1248..edab4e6d3f0 100644 --- a/llvm/test/CodeGen/X86/i64-mem-copy.ll +++ b/llvm/test/CodeGen/X86/i64-mem-copy.ll @@ -3,7 +3,7 @@ ; X64: movq ({{%rsi|%rdx}}), %r ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s -check-prefix=X32 -; X32: movsd (%eax), %xmm +; X32: movsd (%ecx), %xmm ; Uses movsd to load / store i64 values if sse2 is available. diff --git a/llvm/test/CodeGen/X86/pr16031.ll b/llvm/test/CodeGen/X86/pr16031.ll index ecf6218aeb3..dc16fd9671a 100644 --- a/llvm/test/CodeGen/X86/pr16031.ll +++ b/llvm/test/CodeGen/X86/pr16031.ll @@ -2,9 +2,9 @@ ; CHECK-LABEL: main: ; CHECK: pushl %esi +; CHECK-NEXT: testb $1, 8(%esp) ; CHECK-NEXT: movl $-12, %eax ; CHECK-NEXT: movl $-1, %edx -; CHECK-NEXT: testb $1, 8(%esp) ; CHECK-NEXT: cmovel %edx, %eax ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: movl %eax, %esi diff --git a/llvm/test/CodeGen/X86/sse2.ll b/llvm/test/CodeGen/X86/sse2.ll index 9147c22dd37..628dba0b101 100644 --- a/llvm/test/CodeGen/X86/sse2.ll +++ b/llvm/test/CodeGen/X86/sse2.ll @@ -9,10 +9,10 @@ define void @test1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind { ret void ; CHECK-LABEL: test1: -; CHECK: movl 8(%esp), %eax -; CHECK-NEXT: movapd (%eax), %xmm0 +; CHECK: movl 4(%esp), %eax +; CHECK-NEXT: movl 8(%esp), %ecx +; CHECK-NEXT: movapd (%ecx), %xmm0 ; CHECK-NEXT: movlpd 12(%esp), %xmm0 -; CHECK-NEXT: movl 4(%esp), %eax ; CHECK-NEXT: movapd %xmm0, (%eax) ; CHECK-NEXT: ret } diff --git a/llvm/test/CodeGen/X86/v2f32.ll b/llvm/test/CodeGen/X86/v2f32.ll index f2bebf57d4d..dab5e7bc944 100644 --- a/llvm/test/CodeGen/X86/v2f32.ll +++ b/llvm/test/CodeGen/X86/v2f32.ll @@ -24,9 +24,9 @@ define void @test1(<2 x float> %Q, float *%P2) nounwind { ; W64-NEXT: ret ; X32-LABEL: test1: +; X32-NEXT: movl 4(%esp), %eax ; X32-NEXT: pshufd $1, %xmm0, %xmm1 ; X32-NEXT: addss %xmm0, %xmm1 -; X32-NEXT: movl 4(%esp), %eax ; X32-NEXT: movss %xmm1, (%eax) ; X32-NEXT: ret } |
