diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/include/llvm/Target/GenericOpcodes.td | 7 | ||||
| -rw-r--r-- | llvm/include/llvm/Target/TargetOpcodes.def | 3 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll | 11 |
4 files changed, 27 insertions, 0 deletions
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td index 8d01bd2c5bd..09b03bcb20c 100644 --- a/llvm/include/llvm/Target/GenericOpcodes.td +++ b/llvm/include/llvm/Target/GenericOpcodes.td @@ -380,6 +380,13 @@ def G_FREM : Instruction { let hasSideEffects = 0; } +// Floating point exponentiation. +def G_FPOW : Instruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src1, type0:$src2); + let hasSideEffects = 0; +} + //------------------------------------------------------------------------------ // Memory ops //------------------------------------------------------------------------------ diff --git a/llvm/include/llvm/Target/TargetOpcodes.def b/llvm/include/llvm/Target/TargetOpcodes.def index 8f209ecb03b..7987dddc5b2 100644 --- a/llvm/include/llvm/Target/TargetOpcodes.def +++ b/llvm/include/llvm/Target/TargetOpcodes.def @@ -354,6 +354,9 @@ HANDLE_TARGET_OPCODE(G_FDIV) /// Generic FP remainder. HANDLE_TARGET_OPCODE(G_FREM) +/// Generic FP exponentiation. +HANDLE_TARGET_OPCODE(G_FPOW) + /// Generic float to signed-int conversion HANDLE_TARGET_OPCODE(G_FPEXT) diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 8b06f4dc234..361efe6c1d6 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -636,6 +636,12 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder); case Intrinsic::smul_with_overflow: return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder); + case Intrinsic::pow: + MIRBuilder.buildInstr(TargetOpcode::G_FPOW) + .addDef(getOrCreateVReg(CI)) + .addUse(getOrCreateVReg(*CI.getArgOperand(0))) + .addUse(getOrCreateVReg(*CI.getArgOperand(1))); + return true; case Intrinsic::memcpy: case Intrinsic::memmove: case Intrinsic::memset: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index 943a57f55cb..e658a09858d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -1133,3 +1133,14 @@ define void @test_va_end(i8* %list) { call void @llvm.va_end(i8* %list) ret void } + +declare float @llvm.pow.f32(float, float) +define float @test_pow_intrin(float %l, float %r) { +; CHECK-LABEL: name: test_pow_intrin +; CHECK: [[LHS:%[0-9]+]](s32) = COPY %s0 +; CHECK: [[RHS:%[0-9]+]](s32) = COPY %s1 +; CHECK: [[RES:%[0-9]+]](s32) = G_FPOW [[LHS]], [[RHS]] +; CHECK: %s0 = COPY [[RES]] + %res = call float @llvm.pow.f32(float %l, float %r) + ret float %res +} |
