diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 23 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/basic-thumb2-instructions.s | 22 | 
2 files changed, 44 insertions, 1 deletions
| diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index e82e32186dd..10b17f37519 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -35,8 +35,9 @@ def t2_so_reg : Operand<i32>,    // reg imm                                 [shl,srl,sra,rotr]> {    let EncoderMethod = "getT2SORegOpValue";    let PrintMethod = "printT2SOOperand"; -  let MIOperandInfo = (ops rGPR, i32imm);    let DecoderMethod = "DecodeSORegImmOperand"; +  let ParserMatchClass = ShiftedImmAsmOperand; +  let MIOperandInfo = (ops rGPR, i32imm);  }  // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value @@ -3490,3 +3491,23 @@ def : T2Pat<(atomic_store_32 t2addrmode_imm8:$addr, GPR:$val),              (t2STRi8    GPR:$val, t2addrmode_imm8:$addr)>;  def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),              (t2STRs     GPR:$val, t2addrmode_so_reg:$addr)>; + + +//===----------------------------------------------------------------------===// +// Assembler aliases +// + +// Aliases for ADC without the ".w" optional width specifier. +def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm", +                  (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; +def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm", +                  (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, +                           pred:$p, cc_out:$s)>; + +// Aliases for SBC without the ".w" optional width specifier. +def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm", +                  (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; +def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm", +                  (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, +                           pred:$p, cc_out:$s)>; + diff --git a/llvm/test/MC/ARM/basic-thumb2-instructions.s b/llvm/test/MC/ARM/basic-thumb2-instructions.s index 61d651472ee..d00566ae04a 100644 --- a/llvm/test/MC/ARM/basic-thumb2-instructions.s +++ b/llvm/test/MC/ARM/basic-thumb2-instructions.s @@ -38,6 +38,28 @@ _func:  @ CHECK: adc	r4, r2, #1664           @ encoding: [0x42,0xf5,0xd0,0x64]  @------------------------------------------------------------------------------ +@ ADC (register) +@------------------------------------------------------------------------------ +        adc r4, r5, r6 +        adcs r4, r5, r6 +        adc.w r9, r1, r3 +        adcs.w r9, r1, r3 +        adc	r0, r1, r3, ror #4 +        adcs	r0, r1, r3, lsl #7 +        adc.w	r0, r1, r3, lsr #31 +        adcs.w	r0, r1, r3, asr #32 + +@ CHECK: adc.w	r4, r5, r6              @ encoding: [0x45,0xeb,0x06,0x04] +@ CHECK: adcs.w	r4, r5, r6              @ encoding: [0x55,0xeb,0x06,0x04] +@ CHECK: adc.w	r9, r1, r3              @ encoding: [0x41,0xeb,0x03,0x09] +@ CHECK: adcs.w	r9, r1, r3              @ encoding: [0x51,0xeb,0x03,0x09] +@ CHECK: adc.w	r0, r1, r3, ror #4      @ encoding: [0x41,0xeb,0x33,0x10] +@ CHECK: adcs.w	r0, r1, r3, lsl #7      @ encoding: [0x51,0xeb,0xc3,0x10] +@ CHECK: adc.w	r0, r1, r3, lsr #31     @ encoding: [0x41,0xeb,0xd3,0x70] +@ CHECK: adcs.w	r0, r1, r3, asr #32     @ encoding: [0x51,0xeb,0x23,0x00] + + +@------------------------------------------------------------------------------  @ CBZ/CBNZ  @------------------------------------------------------------------------------          cbnz    r7, #6 | 

