diff options
Diffstat (limited to 'llvm')
22 files changed, 13182 insertions, 117 deletions
diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp index 726961a2321..1bd1fe2bea0 100644 --- a/llvm/lib/Support/Host.cpp +++ b/llvm/lib/Support/Host.cpp @@ -682,6 +682,28 @@ StringRef sys::getHostCPUName() { StringRef Str(buffer, CPUInfoSize); SmallVector<StringRef, 32> Lines; Str.split(Lines, "\n"); + + // Look for the CPU features. + SmallVector<StringRef, 32> CPUFeatures; + for (unsigned I = 0, E = Lines.size(); I != E; ++I) + if (Lines[I].startswith("features")) { + size_t Pos = Lines[I].find(":"); + if (Pos != StringRef::npos) { + Lines[I].drop_front(Pos + 1).split(CPUFeatures, " "); + break; + } + } + + // We need to check for the presence of vector support independently of + // the machine type, since we may only use the vector register set when + // supported by the kernel (and hypervisor). + bool HaveVectorSupport = false; + for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { + if (CPUFeatures[I] == "vx") + HaveVectorSupport = true; + } + + // Now check the processor machine type. for (unsigned I = 0, E = Lines.size(); I != E; ++I) { if (Lines[I].startswith("processor ")) { size_t Pos = Lines[I].find("machine = "); @@ -689,6 +711,8 @@ StringRef sys::getHostCPUName() { Pos += sizeof("machine = ") - 1; unsigned int Id; if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { + if (Id >= 2964 && HaveVectorSupport) + return "z13"; if (Id >= 2827) return "zEC12"; if (Id >= 2817) diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp index ec6a57388bc..0d003596be2 100644 --- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp +++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp @@ -39,13 +39,17 @@ enum RegisterKind { ADDR64Reg, FP32Reg, FP64Reg, - FP128Reg + FP128Reg, + VR32Reg, + VR64Reg, + VR128Reg }; enum MemoryKind { BDMem, BDXMem, - BDLMem + BDLMem, + BDVMem }; class SystemZOperand : public MCParsedAsmOperand { @@ -89,10 +93,10 @@ private: // the base register has (ADDR32Reg or ADDR64Reg). Length is the operand // length for D(L,B)-style operands, otherwise it is null. struct MemOp { - unsigned Base : 8; - unsigned Index : 8; - unsigned MemKind : 8; - unsigned RegKind : 8; + unsigned Base : 12; + unsigned Index : 12; + unsigned MemKind : 4; + unsigned RegKind : 4; const MCExpr *Disp; const MCExpr *Length; }; @@ -246,6 +250,13 @@ public: bool isMemDisp12Len8(RegisterKind RegKind) const { return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length, 1, 0x100); } + void addBDVAddrOperands(MCInst &Inst, unsigned N) const { + assert(N == 3 && "Invalid number of operands"); + assert(isMem(BDVMem) && "Invalid operand type"); + Inst.addOperand(MCOperand::CreateReg(Mem.Base)); + addExpr(Inst, Mem.Disp); + Inst.addOperand(MCOperand::CreateReg(Mem.Index)); + } // Override MCParsedAsmOperand. SMLoc getStartLoc() const override { return StartLoc; } @@ -307,6 +318,10 @@ public: bool isFP32() const { return isReg(FP32Reg); } bool isFP64() const { return isReg(FP64Reg); } bool isFP128() const { return isReg(FP128Reg); } + bool isVR32() const { return isReg(VR32Reg); } + bool isVR64() const { return isReg(VR64Reg); } + bool isVF128() const { return false; } + bool isVR128() const { return isReg(VR128Reg); } bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); } bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); } bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); } @@ -314,10 +329,15 @@ public: bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); } bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); } bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); } + bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); } + bool isU1Imm() const { return isImm(0, 1); } + bool isU2Imm() const { return isImm(0, 3); } + bool isU3Imm() const { return isImm(0, 7); } bool isU4Imm() const { return isImm(0, 15); } bool isU6Imm() const { return isImm(0, 63); } bool isU8Imm() const { return isImm(0, 255); } bool isS8Imm() const { return isImm(-128, 127); } + bool isU12Imm() const { return isImm(0, 4095); } bool isU16Imm() const { return isImm(0, 65535); } bool isS16Imm() const { return isImm(-32768, 32767); } bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); } @@ -334,6 +354,7 @@ private: enum RegisterGroup { RegGR, RegFP, + RegV, RegAccess }; struct Register { @@ -352,7 +373,7 @@ private: RegisterKind Kind); bool parseAddress(unsigned &Base, const MCExpr *&Disp, - unsigned &Index, const MCExpr *&Length, + unsigned &Index, bool &IsVector, const MCExpr *&Length, const unsigned *Regs, RegisterKind RegKind); OperandMatchResultTy parseAddress(OperandVector &Operands, @@ -419,6 +440,18 @@ public: OperandMatchResultTy parseFP128(OperandVector &Operands) { return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg); } + OperandMatchResultTy parseVR32(OperandVector &Operands) { + return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg); + } + OperandMatchResultTy parseVR64(OperandVector &Operands) { + return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg); + } + OperandMatchResultTy parseVF128(OperandVector &Operands) { + llvm_unreachable("Shouldn't be used as an operand"); + } + OperandMatchResultTy parseVR128(OperandVector &Operands) { + return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg); + } OperandMatchResultTy parseBDAddr32(OperandVector &Operands) { return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg); } @@ -431,6 +464,9 @@ public: OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) { return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg); } + OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) { + return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg); + } OperandMatchResultTy parseAccessReg(OperandVector &Operands); OperandMatchResultTy parsePCRel16(OperandVector &Operands) { return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false); @@ -484,6 +520,8 @@ bool SystemZAsmParser::parseRegister(Register &Reg) { Reg.Group = RegGR; else if (Prefix == 'f' && Reg.Num < 16) Reg.Group = RegFP; + else if (Prefix == 'v' && Reg.Num < 32) + Reg.Group = RegV; else if (Prefix == 'a' && Reg.Num < 16) Reg.Group = RegAccess; else @@ -534,8 +572,8 @@ SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group, // Regs maps asm register numbers to LLVM register numbers and RegKind // says what kind of address register we're using (ADDR32Reg or ADDR64Reg). bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp, - unsigned &Index, const MCExpr *&Length, - const unsigned *Regs, + unsigned &Index, bool &IsVector, + const MCExpr *&Length, const unsigned *Regs, RegisterKind RegKind) { // Parse the displacement, which must always be present. if (getParser().parseExpression(Disp)) @@ -544,6 +582,7 @@ bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp, // Parse the optional base and index. Index = 0; Base = 0; + IsVector = false; Length = nullptr; if (getLexer().is(AsmToken::LParen)) { Parser.Lex(); @@ -551,12 +590,23 @@ bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp, if (getLexer().is(AsmToken::Percent)) { // Parse the first register and decide whether it's a base or an index. Register Reg; - if (parseRegister(Reg, RegGR, Regs, RegKind)) + if (parseRegister(Reg)) return true; - if (getLexer().is(AsmToken::Comma)) - Index = Reg.Num; - else - Base = Reg.Num; + if (Reg.Group == RegV) { + // A vector index register. The base register is optional. + IsVector = true; + Index = SystemZMC::VR128Regs[Reg.Num]; + } else if (Reg.Group == RegGR) { + if (Reg.Num == 0) + return Error(Reg.StartLoc, "%r0 used in an address"); + // If the are two registers, the first one is the index and the + // second is the base. + if (getLexer().is(AsmToken::Comma)) + Index = Regs[Reg.Num]; + else + Base = Regs[Reg.Num]; + } else + return Error(Reg.StartLoc, "invalid address register"); } else { // Parse the length. if (getParser().parseExpression(Length)) @@ -587,28 +637,36 @@ SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind, const unsigned *Regs, RegisterKind RegKind) { SMLoc StartLoc = Parser.getTok().getLoc(); unsigned Base, Index; + bool IsVector; const MCExpr *Disp; const MCExpr *Length; - if (parseAddress(Base, Disp, Index, Length, Regs, RegKind)) + if (parseAddress(Base, Disp, Index, IsVector, Length, Regs, RegKind)) return MatchOperand_ParseFail; - if (Index && MemKind != BDXMem) - { - Error(StartLoc, "invalid use of indexed addressing"); - return MatchOperand_ParseFail; - } + if (IsVector && MemKind != BDVMem) { + Error(StartLoc, "invalid use of vector addressing"); + return MatchOperand_ParseFail; + } - if (Length && MemKind != BDLMem) - { - Error(StartLoc, "invalid use of length addressing"); - return MatchOperand_ParseFail; - } + if (!IsVector && MemKind == BDVMem) { + Error(StartLoc, "vector index required in address"); + return MatchOperand_ParseFail; + } - if (!Length && MemKind == BDLMem) - { - Error(StartLoc, "missing length in address"); - return MatchOperand_ParseFail; - } + if (Index && MemKind != BDXMem && MemKind != BDVMem) { + Error(StartLoc, "invalid use of indexed addressing"); + return MatchOperand_ParseFail; + } + + if (Length && MemKind != BDLMem) { + Error(StartLoc, "invalid use of length addressing"); + return MatchOperand_ParseFail; + } + + if (!Length && MemKind == BDLMem) { + Error(StartLoc, "missing length in address"); + return MatchOperand_ParseFail; + } SMLoc EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); @@ -631,6 +689,8 @@ bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, RegNo = SystemZMC::GR64Regs[Reg.Num]; else if (Reg.Group == RegFP) RegNo = SystemZMC::FP64Regs[Reg.Num]; + else if (Reg.Group == RegV) + RegNo = SystemZMC::VR128Regs[Reg.Num]; else // FIXME: Access registers aren't modelled as LLVM registers yet. return Error(Reg.StartLoc, "invalid operand for instruction"); @@ -703,8 +763,10 @@ bool SystemZAsmParser::parseOperand(OperandVector &Operands, // so we treat any plain expression as an immediate. SMLoc StartLoc = Parser.getTok().getLoc(); unsigned Base, Index; + bool IsVector; const MCExpr *Expr, *Length; - if (parseAddress(Base, Expr, Index, Length, SystemZMC::GR64Regs, ADDR64Reg)) + if (parseAddress(Base, Expr, Index, IsVector, Length, SystemZMC::GR64Regs, + ADDR64Reg)) return true; SMLoc EndLoc = diff --git a/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp b/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp index 84400f828cb..c898e9d5ecf 100644 --- a/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp +++ b/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp @@ -47,8 +47,8 @@ extern "C" void LLVMInitializeSystemZDisassembler() { } static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, - const unsigned *Regs) { - assert(RegNo < 16 && "Invalid register"); + const unsigned *Regs, unsigned Size) { + assert(RegNo < Size && "Invalid register"); RegNo = Regs[RegNo]; if (RegNo == 0) return MCDisassembler::Fail; @@ -59,61 +59,81 @@ static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16); } static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16); } static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16); } static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16); } static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16); } static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs, 16); } static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC::FP64Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC::FP64Regs, 16); } static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC::FP128Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC::FP128Regs, 16); +} + +static DecodeStatus DecodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC::VR32Regs, 32); +} + +static DecodeStatus DecodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC::VR64Regs, 32); +} + +static DecodeStatus DecodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC::VR128Regs, 32); } template<unsigned N> static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { - assert(isUInt<N>(Imm) && "Invalid immediate"); + if (!isUInt<N>(Imm)) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(Imm)); return MCDisassembler::Success; } template<unsigned N> static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) { - assert(isUInt<N>(Imm) && "Invalid immediate"); + if (!isUInt<N>(Imm)) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm))); return MCDisassembler::Success; } @@ -124,6 +144,21 @@ static DecodeStatus decodeAccessRegOperand(MCInst &Inst, uint64_t Imm, return decodeUImmOperand<4>(Inst, Imm); } +static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) { + return decodeUImmOperand<1>(Inst, Imm); +} + +static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) { + return decodeUImmOperand<2>(Inst, Imm); +} + +static DecodeStatus decodeU3ImmOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) { + return decodeUImmOperand<3>(Inst, Imm); +} + static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodeUImmOperand<4>(Inst, Imm); @@ -139,6 +174,11 @@ static DecodeStatus decodeU8ImmOperand(MCInst &Inst, uint64_t Imm, return decodeUImmOperand<8>(Inst, Imm); } +static DecodeStatus decodeU12ImmOperand(MCInst &Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) { + return decodeUImmOperand<12>(Inst, Imm); +} + static DecodeStatus decodeU16ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodeUImmOperand<16>(Inst, Imm); @@ -240,6 +280,18 @@ static DecodeStatus decodeBDLAddr12Len8Operand(MCInst &Inst, uint64_t Field, return MCDisassembler::Success; } +static DecodeStatus decodeBDVAddr12Operand(MCInst &Inst, uint64_t Field, + const unsigned *Regs) { + uint64_t Index = Field >> 16; + uint64_t Base = (Field >> 12) & 0xf; + uint64_t Disp = Field & 0xfff; + assert(Index < 32 && "Invalid BDVAddr12"); + Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); + Inst.addOperand(MCOperand::CreateImm(Disp)); + Inst.addOperand(MCOperand::CreateReg(SystemZMC::VR128Regs[Index])); + return MCDisassembler::Success; +} + static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder) { @@ -283,6 +335,12 @@ static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst &Inst, return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC::GR64Regs); } +static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst &Inst, uint64_t Field, + uint64_t Address, + const void *Decoder) { + return decodeBDVAddr12Operand(Inst, Field, SystemZMC::GR64Regs); +} + #include "SystemZGenDisassemblerTables.inc" DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size, diff --git a/llvm/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp b/llvm/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp index cf1ee54df38..02bd47d07f7 100644 --- a/llvm/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp +++ b/llvm/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp @@ -22,13 +22,17 @@ using namespace llvm; void SystemZInstPrinter::printAddress(unsigned Base, int64_t Disp, unsigned Index, raw_ostream &O) { O << Disp; - if (Base) { + if (Base || Index) { O << '('; - if (Index) - O << '%' << getRegisterName(Index) << ','; - O << '%' << getRegisterName(Base) << ')'; - } else - assert(!Index && "Shouldn't have an index without a base"); + if (Index) { + O << '%' << getRegisterName(Index); + if (Base) + O << ','; + } + if (Base) + O << '%' << getRegisterName(Base); + O << ')'; + } } void SystemZInstPrinter::printOperand(const MCOperand &MO, raw_ostream &O) { @@ -53,60 +57,78 @@ void SystemZInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const { O << '%' << getRegisterName(RegNo); } -void SystemZInstPrinter::printU4ImmOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { +template<unsigned N> +void printUImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { int64_t Value = MI->getOperand(OpNum).getImm(); - assert(isUInt<4>(Value) && "Invalid u4imm argument"); + assert(isUInt<N>(Value) && "Invalid uimm argument"); O << Value; } -void SystemZInstPrinter::printU6ImmOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { +template<unsigned N> +void printSImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { int64_t Value = MI->getOperand(OpNum).getImm(); - assert(isUInt<6>(Value) && "Invalid u6imm argument"); + assert(isInt<N>(Value) && "Invalid simm argument"); O << Value; } +void SystemZInstPrinter::printU1ImmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + printUImmOperand<1>(MI, OpNum, O); +} + +void SystemZInstPrinter::printU2ImmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + printUImmOperand<2>(MI, OpNum, O); +} + +void SystemZInstPrinter::printU3ImmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + printUImmOperand<3>(MI, OpNum, O); +} + +void SystemZInstPrinter::printU4ImmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + printUImmOperand<4>(MI, OpNum, O); +} + +void SystemZInstPrinter::printU6ImmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + printUImmOperand<6>(MI, OpNum, O); +} + void SystemZInstPrinter::printS8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { - int64_t Value = MI->getOperand(OpNum).getImm(); - assert(isInt<8>(Value) && "Invalid s8imm argument"); - O << Value; + printSImmOperand<8>(MI, OpNum, O); } void SystemZInstPrinter::printU8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { - int64_t Value = MI->getOperand(OpNum).getImm(); - assert(isUInt<8>(Value) && "Invalid u8imm argument"); - O << Value; + printUImmOperand<8>(MI, OpNum, O); +} + +void SystemZInstPrinter::printU12ImmOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + printUImmOperand<12>(MI, OpNum, O); } void SystemZInstPrinter::printS16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { - int64_t Value = MI->getOperand(OpNum).getImm(); - assert(isInt<16>(Value) && "Invalid s16imm argument"); - O << Value; + printSImmOperand<16>(MI, OpNum, O); } void SystemZInstPrinter::printU16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { - int64_t Value = MI->getOperand(OpNum).getImm(); - assert(isUInt<16>(Value) && "Invalid u16imm argument"); - O << Value; + printUImmOperand<16>(MI, OpNum, O); } void SystemZInstPrinter::printS32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { - int64_t Value = MI->getOperand(OpNum).getImm(); - assert(isInt<32>(Value) && "Invalid s32imm argument"); - O << Value; + printSImmOperand<32>(MI, OpNum, O); } void SystemZInstPrinter::printU32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { - int64_t Value = MI->getOperand(OpNum).getImm(); - assert(isUInt<32>(Value) && "Invalid u32imm argument"); - O << Value; + printUImmOperand<32>(MI, OpNum, O); } void SystemZInstPrinter::printAccessRegOperand(const MCInst *MI, int OpNum, @@ -178,6 +200,13 @@ void SystemZInstPrinter::printBDLAddrOperand(const MCInst *MI, int OpNum, O << ')'; } +void SystemZInstPrinter::printBDVAddrOperand(const MCInst *MI, int OpNum, + raw_ostream &O) { + printAddress(MI->getOperand(OpNum).getReg(), + MI->getOperand(OpNum + 1).getImm(), + MI->getOperand(OpNum + 2).getReg(), O); +} + void SystemZInstPrinter::printCond4Operand(const MCInst *MI, int OpNum, raw_ostream &O) { static const char *const CondNames[] = { diff --git a/llvm/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.h b/llvm/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.h index 6f56c7be3c3..847b6962e6f 100644 --- a/llvm/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.h +++ b/llvm/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.h @@ -48,10 +48,15 @@ private: void printBDAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printBDXAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printBDLAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printBDVAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printU1ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printU2ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printU3ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printU4ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printU6ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printS8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printU8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); + void printU12ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printS16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printU16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); void printS32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp index 8dd70b93351..003e8b235e1 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp @@ -70,6 +70,9 @@ private: uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; + uint64_t getBDVAddr12Encoding(const MCInst &MI, unsigned OpNum, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; // Operand OpNum of MI needs a PC-relative fixup of kind Kind at // Offset bytes from the start of MI. Add the fixup to Fixups @@ -193,6 +196,17 @@ getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, return (Len << 16) | (Base << 12) | Disp; } +uint64_t SystemZMCCodeEmitter:: +getBDVAddr12Encoding(const MCInst &MI, unsigned OpNum, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); + uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); + uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); + assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<5>(Index)); + return (Index << 16) | (Base << 12) | Disp; +} + uint64_t SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp index ea56fb18d49..8476348bb01 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -76,6 +76,39 @@ const unsigned SystemZMC::FP128Regs[16] = { SystemZ::F12Q, SystemZ::F13Q, 0, 0 }; +const unsigned SystemZMC::VR32Regs[32] = { + SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, + SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, + SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, + SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S, + SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, + SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, + SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, + SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S +}; + +const unsigned SystemZMC::VR64Regs[32] = { + SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, + SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, + SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, + SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, + SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, + SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, + SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, + SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D +}; + +const unsigned SystemZMC::VR128Regs[32] = { + SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, + SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, + SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, + SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, + SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, + SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, + SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, + SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31 +}; + unsigned SystemZMC::getFirstReg(unsigned Reg) { static unsigned Map[SystemZ::NUM_TARGET_REGS]; static bool Initialized = false; @@ -85,10 +118,13 @@ unsigned SystemZMC::getFirstReg(unsigned Reg) { Map[GRH32Regs[I]] = I; Map[GR64Regs[I]] = I; Map[GR128Regs[I]] = I; - Map[FP32Regs[I]] = I; - Map[FP64Regs[I]] = I; Map[FP128Regs[I]] = I; } + for (unsigned I = 0; I < 32; ++I) { + Map[VR32Regs[I]] = I; + Map[VR64Regs[I]] = I; + Map[VR128Regs[I]] = I; + } } assert(Reg < SystemZ::NUM_TARGET_REGS); return Map[Reg]; diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h index 2b2647bae94..4c0661608be 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h @@ -49,6 +49,9 @@ extern const unsigned GR128Regs[16]; extern const unsigned FP32Regs[16]; extern const unsigned FP64Regs[16]; extern const unsigned FP128Regs[16]; +extern const unsigned VR32Regs[32]; +extern const unsigned VR64Regs[32]; +extern const unsigned VR128Regs[32]; // Return the 0-based number of the first architectural register that // contains the given LLVM register. E.g. R1D -> 1. diff --git a/llvm/lib/Target/SystemZ/SystemZ.td b/llvm/lib/Target/SystemZ/SystemZ.td index 5f829034902..4f3f18ed499 100644 --- a/llvm/lib/Target/SystemZ/SystemZ.td +++ b/llvm/lib/Target/SystemZ/SystemZ.td @@ -41,6 +41,7 @@ include "SystemZPatterns.td" include "SystemZInstrFormats.td" include "SystemZInstrInfo.td" include "SystemZInstrFP.td" +include "SystemZInstrVector.td" def SystemZInstrInfo : InstrInfo {} diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td index 2d3c9e27e73..2c87871cdca 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td @@ -142,10 +142,13 @@ def getThreeOperandOpcode : InstrMapping { // Formats are specified using operand field declarations of the form: // // bits<4> Rn : register input or output for operand n +// bits<5> Vn : vector register input or output for operand n // bits<m> In : immediate value of width m for operand n // bits<4> BDn : address operand n, which has a base and a displacement // bits<m> XBDn : address operand n, which has an index, a base and a // displacement +// bits<m> VBDn : address operand n, which has a vector index, a base and a +// displacement // bits<4> Xn : index register for address operand n // bits<4> Mn : mode value for operand n // @@ -339,11 +342,13 @@ class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> bits<4> R1; bits<20> XBD2; + bits<4> M3; let Inst{47-40} = op{15-8}; let Inst{39-36} = R1; let Inst{35-16} = XBD2; - let Inst{15-8} = 0; + let Inst{15-12} = M3; + let Inst{11-8} = 0; let Inst{7-0} = op{7-0}; let HasIndex = 1; @@ -484,6 +489,382 @@ class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> let Inst{15-0} = BD2; } +class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<16> I2; + bits<4> M3; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-32} = 0; + let Inst{31-16} = I2; + let Inst{15-12} = M3; + let Inst{11} = V1{4}; + let Inst{10-8} = 0; + let Inst{7-0} = op{7-0}; +} + +class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<8> I2; + bits<8> I3; + bits<4> M4; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-32} = 0; + let Inst{31-24} = I2; + let Inst{23-16} = I3; + let Inst{15-12} = M4; + let Inst{11} = V1{4}; + let Inst{10-8} = 0; + let Inst{7-0} = op{7-0}; +} + +class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<5> V3; + bits<16> I2; + bits<4> M4; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-32} = V3{3-0}; + let Inst{31-16} = I2; + let Inst{15-12} = M4; + let Inst{11} = V1{4}; + let Inst{10} = V3{4}; + let Inst{9-8} = 0; + let Inst{7-0} = op{7-0}; +} + +class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<5> V2; + bits<5> V3; + bits<8> I4; + bits<4> M5; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-32} = V2{3-0}; + let Inst{31-28} = V3{3-0}; + let Inst{27-24} = 0; + let Inst{23-16} = I4; + let Inst{15-12} = M5; + let Inst{11} = V1{4}; + let Inst{10} = V2{4}; + let Inst{9} = V3{4}; + let Inst{8} = 0; + let Inst{7-0} = op{7-0}; +} + +class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<5> V2; + bits<12> I3; + bits<4> M4; + bits<4> M5; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-32} = V2{3-0}; + let Inst{31-20} = I3; + let Inst{19-16} = M5; + let Inst{15-12} = M4; + let Inst{11} = V1{4}; + let Inst{10} = V2{4}; + let Inst{9-8} = 0; + let Inst{7-0} = op{7-0}; +} + +// Depending on the instruction mnemonic, certain bits may be or-ed into +// the M4 value provided as explicit operand. These are passed as m4or. +class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, + bits<4> m4or = 0> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<5> V2; + bits<4> M3; + bits<4> M4; + bits<4> M5; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-32} = V2{3-0}; + let Inst{31-24} = 0; + let Inst{23-20} = M5; + let Inst{19} = !if (!eq (m4or{3}, 1), 1, M4{3}); + let Inst{18} = !if (!eq (m4or{2}, 1), 1, M4{2}); + let Inst{17} = !if (!eq (m4or{1}, 1), 1, M4{1}); + let Inst{16} = !if (!eq (m4or{0}, 1), 1, M4{0}); + let Inst{15-12} = M3; + let Inst{11} = V1{4}; + let Inst{10} = V2{4}; + let Inst{9-8} = 0; + let Inst{7-0} = op{7-0}; +} + +// Depending on the instruction mnemonic, certain bits may be or-ed into +// the M5 value provided as explicit operand. These are passed as m5or. +class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, + bits<4> m5or = 0> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<5> V2; + bits<5> V3; + bits<4> M4; + bits<4> M5; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-32} = V2{3-0}; + let Inst{31-28} = V3{3-0}; + let Inst{27-24} = 0; + let Inst{23} = !if (!eq (m5or{3}, 1), 1, M5{3}); + let Inst{22} = !if (!eq (m5or{2}, 1), 1, M5{2}); + let Inst{21} = !if (!eq (m5or{1}, 1), 1, M5{1}); + let Inst{20} = !if (!eq (m5or{0}, 1), 1, M5{0}); + let Inst{19-16} = 0; + let Inst{15-12} = M4; + let Inst{11} = V1{4}; + let Inst{10} = V2{4}; + let Inst{9} = V3{4}; + let Inst{8} = 0; + let Inst{7-0} = op{7-0}; +} + +class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<5> V2; + bits<5> V3; + bits<4> M4; + bits<4> M5; + bits<4> M6; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-32} = V2{3-0}; + let Inst{31-28} = V3{3-0}; + let Inst{27-24} = 0; + let Inst{23-20} = M6; + let Inst{19-16} = M5; + let Inst{15-12} = M4; + let Inst{11} = V1{4}; + let Inst{10} = V2{4}; + let Inst{9} = V3{4}; + let Inst{8} = 0; + let Inst{7-0} = op{7-0}; +} + +// Depending on the instruction mnemonic, certain bits may be or-ed into +// the M6 value provided as explicit operand. These are passed as m6or. +class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, + bits<4> m6or = 0> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<5> V2; + bits<5> V3; + bits<5> V4; + bits<4> M5; + bits<4> M6; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-32} = V2{3-0}; + let Inst{31-28} = V3{3-0}; + let Inst{27-24} = M5; + let Inst{23} = !if (!eq (m6or{3}, 1), 1, M6{3}); + let Inst{22} = !if (!eq (m6or{2}, 1), 1, M6{2}); + let Inst{21} = !if (!eq (m6or{1}, 1), 1, M6{1}); + let Inst{20} = !if (!eq (m6or{0}, 1), 1, M6{0}); + let Inst{19-16} = 0; + let Inst{15-12} = V4{3-0}; + let Inst{11} = V1{4}; + let Inst{10} = V2{4}; + let Inst{9} = V3{4}; + let Inst{8} = V4{4}; + let Inst{7-0} = op{7-0}; +} + +class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<5> V2; + bits<5> V3; + bits<5> V4; + bits<4> M5; + bits<4> M6; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-32} = V2{3-0}; + let Inst{31-28} = V3{3-0}; + let Inst{27-24} = M6; + let Inst{23-20} = 0; + let Inst{19-16} = M5; + let Inst{15-12} = V4{3-0}; + let Inst{11} = V1{4}; + let Inst{10} = V2{4}; + let Inst{9} = V3{4}; + let Inst{8} = V4{4}; + let Inst{7-0} = op{7-0}; +} + +class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<4> R2; + bits<4> R3; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-32} = R2; + let Inst{31-28} = R3; + let Inst{27-12} = 0; + let Inst{11} = V1{4}; + let Inst{10-8} = 0; + let Inst{7-0} = op{7-0}; +} + +class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<16> BD2; + bits<5> V3; + bits<4> M4; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-32} = V3{3-0}; + let Inst{31-16} = BD2; + let Inst{15-12} = M4; + let Inst{11} = V1{4}; + let Inst{10} = V3{4}; + let Inst{9-8} = 0; + let Inst{7-0} = op{7-0}; +} + +class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<16> BD2; + bits<4> R3; + bits<4> M4; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-32} = R3; + let Inst{31-16} = BD2; + let Inst{15-12} = M4; + let Inst{11} = V1{4}; + let Inst{10-8} = 0; + let Inst{7-0} = op{7-0}; +} + +class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<4> R1; + bits<16> BD2; + bits<5> V3; + bits<4> M4; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = R1; + let Inst{35-32} = V3{3-0}; + let Inst{31-16} = BD2; + let Inst{15-12} = M4; + let Inst{11} = 0; + let Inst{10} = V3{4}; + let Inst{9-8} = 0; + let Inst{7-0} = op{7-0}; +} + +class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<21> VBD2; + bits<4> M3; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-16} = VBD2{19-0}; + let Inst{15-12} = M3; + let Inst{11} = V1{4}; + let Inst{10} = VBD2{20}; + let Inst{9-8} = 0; + let Inst{7-0} = op{7-0}; +} + +class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<20> XBD2; + bits<4> M3; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-16} = XBD2; + let Inst{15-12} = M3; + let Inst{11} = V1{4}; + let Inst{10-8} = 0; + let Inst{7-0} = op{7-0}; +} + //===----------------------------------------------------------------------===// // Instruction definitions with semantics //===----------------------------------------------------------------------===// @@ -503,12 +884,6 @@ class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> // form of the source register in the destination register and // branches on the result. // -// Store: -// One register or immediate input operand and one address input operand. -// The instruction stores the first operand to the address. -// -// This category is used for both pure and truncating stores. -// // LoadMultiple: // One address input operand and two explicit output operands. // The instruction loads a range of registers from the address, @@ -521,18 +896,35 @@ class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> // with the explicit operands giving the first and last register // to store. Other stored registers are added as implicit uses. // +// StoreLength: +// One value operand, one length operand and one address operand. +// The instruction stores the value operand to the address but +// doesn't write more than the number of bytes specified by the +// length operand. +// // Unary: // One register output operand and one input operand. // +// Store: +// One address operand and one other input operand. The instruction +// stores to the address. +// // Binary: // One register output operand and two input operands. // +// StoreBinary: +// One address operand and two other input operands. The instruction +// stores to the address. +// // Compare: // Two input operands and an implicit CC output operand. // // Ternary: // One register output operand and three input operands. // +// Quaternary: +// One register output operand and four input operands. +// // LoadAndOp: // One output operand and two input operands, one of which is an address. // The instruction both reads from and writes to the address. @@ -567,6 +959,12 @@ class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls, let R2 = 0; } +class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value> + : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> { + let I2 = value; + let M3 = 0; +} + class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls> : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$I2), mnemonic##"\t$R1, $I2", []> { @@ -582,6 +980,13 @@ class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls> let mayLoad = 1; } +class LoadMultipleVRSa<string mnemonic, bits<16> opcode> + : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2), + mnemonic#"\t$V1, $V3, $BD2", []> { + let M4 = 0; + let mayLoad = 1; +} + class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, RegisterOperand cls> : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2), @@ -630,12 +1035,39 @@ multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, } } +class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr, bits<5> bytes, bits<4> type = 0> + : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2), + mnemonic#"\t$V1, $XBD2", + [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> { + let M3 = type; + let mayStore = 1; + let AccessBytes = bytes; +} + +class StoreLengthVRSb<string mnemonic, bits<16> opcode, + SDPatternOperator operator, bits<5> bytes> + : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2), + mnemonic#"\t$V1, $R3, $BD2", + [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> { + let M4 = 0; + let mayStore = 1; + let AccessBytes = bytes; +} + class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls> : InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, bdaddr20only:$BD2), mnemonic#"\t$R1, $R3, $BD2", []> { let mayStore = 1; } +class StoreMultipleVRSa<string mnemonic, bits<16> opcode> + : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2), + mnemonic#"\t$V1, $V3, $BD2", []> { + let M4 = 0; + let mayStore = 1; +} + // StoreSI* instructions are used to store an integer to memory, but the // addresses are more restricted than for normal stores. If we are in the // situation of having to force either the address into a register or the @@ -868,6 +1300,7 @@ class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, let OpType = "mem"; let mayLoad = 1; let AccessBytes = bytes; + let M3 = 0; } class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, @@ -894,6 +1327,46 @@ multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, } } +class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr, Immediate imm, bits<4> type = 0> + : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2), + mnemonic#"\t$V1, $I2", + [(set tr.op:$V1, (tr.vt (operator imm:$I2)))]> { + let M3 = type; +} + +class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0, + bits<4> m5 = 0> + : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2), + mnemonic#"\t$V1, $V2", + [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> { + let M3 = type; + let M4 = m4; + let M5 = m5; +} + +multiclass UnaryVRRaSPair<string mnemonic, bits<16> opcode, + SDPatternOperator operator, + SDPatternOperator operator_cc, TypedReg tr1, + TypedReg tr2, bits<4> type, bits<4> modifier = 0, + bits<4> modifier_cc = 1> { + def "" : UnaryVRRa<mnemonic, opcode, operator, tr1, tr2, type, 0, modifier>; + let Defs = [CC] in + def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 0, + modifier_cc>; +} + +class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr, bits<5> bytes, bits<4> type = 0> + : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2), + mnemonic#"\t$V1, $XBD2", + [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> { + let M3 = type; + let mayLoad = 1; + let AccessBytes = bytes; +} + class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, RegisterOperand cls1, RegisterOperand cls2> : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), @@ -1047,6 +1520,7 @@ class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, let DisableEncoding = "$R1src"; let mayLoad = 1; let AccessBytes = bytes; + let M3 = 0; } class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, @@ -1105,6 +1579,148 @@ multiclass BinarySIPair<string mnemonic, bits<8> siOpcode, } } +class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr, bits<4> type> + : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3), + mnemonic#"\t$V1, $I2, $I3", + [(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> { + let M4 = type; +} + +class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr1, TypedReg tr2, bits<4> type> + : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2), + mnemonic#"\t$V1, $V3, $I2", + [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3), + imm32zx16:$I2)))]> { + let M4 = type; +} + +class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5> + : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3), + mnemonic#"\t$V1, $V2, $I3", + [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), + imm32zx12:$I3)))]> { + let M4 = type; + let M5 = m5; +} + +class BinaryVRRa<string mnemonic, bits<16> opcode> + : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3), + mnemonic#"\t$V1, $V2, $M3", []> { + let M4 = 0; + let M5 = 0; +} + +class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr1, TypedReg tr2, bits<4> type = 0, + bits<4> modifier = 0> + : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3), + mnemonic#"\t$V1, $V2, $V3", + [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), + (tr2.vt tr2.op:$V3))))]> { + let M4 = type; + let M5 = modifier; +} + +// Declare a pair of instructions, one which sets CC and one which doesn't. +// The CC-setting form ends with "S" and sets the low bit of M5. +multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode, + SDPatternOperator operator, + SDPatternOperator operator_cc, TypedReg tr1, + TypedReg tr2, bits<4> type, + bits<4> modifier = 0, bits<4> modifier_cc = 1> { + def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, modifier>; + let Defs = [CC] in + def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, + modifier_cc>; +} + +class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0, + bits<4> m6 = 0> + : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3), + mnemonic#"\t$V1, $V2, $V3", + [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), + (tr2.vt tr2.op:$V3))))]> { + let M4 = type; + let M5 = m5; + let M6 = m6; +} + +multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode, + SDPatternOperator operator, + SDPatternOperator operator_cc, TypedReg tr1, + TypedReg tr2, bits<4> type, bits<4> m5, + bits<4> modifier = 0, bits<4> modifier_cc = 1> { + def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type, m5, modifier>; + let Defs = [CC] in + def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, + m5, modifier_cc>; +} + +class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr> + : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3), + mnemonic#"\t$V1, $R2, $R3", + [(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>; + +class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr1, TypedReg tr2, bits<4> type> + : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2), + mnemonic#"\t$V1, $V3, $BD2", + [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3), + shift12only:$BD2)))]> { + let M4 = type; +} + +class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator, + bits<5> bytes> + : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2), + mnemonic#"\t$V1, $R3, $BD2", + [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> { + let M4 = 0; + let mayLoad = 1; + let AccessBytes = bytes; +} + +class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr, bits<4> type> + : InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2), + mnemonic#"\t$R1, $V3, $BD2", + [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> { + let M4 = type; +} + +class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr, bits<5> bytes> + : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3), + mnemonic#"\t$V1, $XBD2, $M3", + [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2, + imm32zx4:$M3)))]> { + let mayLoad = 1; + let AccessBytes = bytes; +} + +class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes, + Immediate index> + : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3), + mnemonic#"\t$V1, $VBD2, $M3", []> { + let mayStore = 1; + let AccessBytes = bytes; +} + +class StoreBinaryVRX<string mnemonic, bits<16> opcode, + SDPatternOperator operator, TypedReg tr, bits<5> bytes, + Immediate index> + : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3), + mnemonic#"\t$V1, $XBD2, $M3", + [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> { + let mayStore = 1; + let AccessBytes = bytes; +} + class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, RegisterOperand cls1, RegisterOperand cls2> : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2), @@ -1177,6 +1793,7 @@ class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, let isCompare = 1; let mayLoad = 1; let AccessBytes = bytes; + let M3 = 0; } class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, @@ -1246,6 +1863,17 @@ multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode, } } +class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr, bits<4> type> + : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2), + mnemonic#"\t$V1, $V2", + [(operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2))]> { + let isCompare = 1; + let M3 = type; + let M4 = 0; + let M5 = 0; +} + class TernaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator, RegisterOperand cls> : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2), @@ -1272,6 +1900,188 @@ class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator, let AccessBytes = bytes; } +class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr1, TypedReg tr2, Immediate imm, Immediate index> + : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3), + mnemonic#"\t$V1, $I2, $M3", + [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src), + imm:$I2, index:$M3)))]> { + let Constraints = "$V1 = $V1src"; + let DisableEncoding = "$V1src"; +} + +class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr1, TypedReg tr2, bits<4> type> + : InstVRId<opcode, (outs tr1.op:$V1), + (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4), + mnemonic#"\t$V1, $V2, $V3, $I4", + [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), + (tr2.vt tr2.op:$V3), + imm32zx8:$I4)))]> { + let M5 = type; +} + +class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or> + : InstVRRa<opcode, (outs tr1.op:$V1), + (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5), + mnemonic#"\t$V1, $V2, $M4, $M5", + [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), + imm32zx4:$M4, + imm32zx4:$M5)))], + m4or> { + let M3 = type; +} + +class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr1, TypedReg tr2, bits<4> type, + SDPatternOperator m5mask, bits<4> m5or> + : InstVRRb<opcode, (outs tr1.op:$V1), + (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5), + mnemonic#"\t$V1, $V2, $V3, $M5", + [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), + (tr2.vt tr2.op:$V3), + m5mask:$M5)))], + m5or> { + let M4 = type; +} + +multiclass TernaryVRRbSPair<string mnemonic, bits<16> opcode, + SDPatternOperator operator, + SDPatternOperator operator_cc, TypedReg tr1, + TypedReg tr2, bits<4> type, bits<4> m5or> { + def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, + imm32zx4even, !and (m5or, 14)>; + def : InstAlias<mnemonic#"\t$V1, $V2, $V3", + (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, + tr2.op:$V3, 0)>; + let Defs = [CC] in + def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, + imm32zx4even, !add(!and (m5or, 14), 1)>; + def : InstAlias<mnemonic#"s\t$V1, $V2, $V3", + (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2, + tr2.op:$V3, 0)>; +} + +class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr1, TypedReg tr2> + : InstVRRc<opcode, (outs tr1.op:$V1), + (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4), + mnemonic#"\t$V1, $V2, $V3, $M4", + [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), + (tr2.vt tr2.op:$V3), + imm32zx4:$M4)))]> { + let M5 = 0; + let M6 = 0; +} + +class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr1, TypedReg tr2, bits<4> type = 0> + : InstVRRd<opcode, (outs tr1.op:$V1), + (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4), + mnemonic#"\t$V1, $V2, $V3, $V4", + [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), + (tr2.vt tr2.op:$V3), + (tr1.vt tr1.op:$V4))))]> { + let M5 = type; + let M6 = 0; +} + +class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0> + : InstVRRe<opcode, (outs tr1.op:$V1), + (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4), + mnemonic#"\t$V1, $V2, $V3, $V4", + [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), + (tr2.vt tr2.op:$V3), + (tr1.vt tr1.op:$V4))))]> { + let M5 = m5; + let M6 = type; +} + +class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type> + : InstVRSb<opcode, (outs tr1.op:$V1), + (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2), + mnemonic#"\t$V1, $R3, $BD2", + [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src), + cls:$R3, + shift12only:$BD2)))]> { + let Constraints = "$V1 = $V1src"; + let DisableEncoding = "$V1src"; + let M4 = type; +} + +class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes, + Immediate index> + : InstVRV<opcode, (outs VR128:$V1), + (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3), + mnemonic#"\t$V1, $VBD2, $M3", []> { + let Constraints = "$V1 = $V1src"; + let DisableEncoding = "$V1src"; + let mayLoad = 1; + let AccessBytes = bytes; +} + +class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr1, TypedReg tr2, bits<5> bytes, Immediate index> + : InstVRX<opcode, (outs tr1.op:$V1), + (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3), + mnemonic#"\t$V1, $XBD2, $M3", + [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src), + bdxaddr12only:$XBD2, + index:$M3)))]> { + let Constraints = "$V1 = $V1src"; + let DisableEncoding = "$V1src"; + let mayLoad = 1; + let AccessBytes = bytes; +} + +class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator, + TypedReg tr1, TypedReg tr2, bits<4> type> + : InstVRId<opcode, (outs tr1.op:$V1), + (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4), + mnemonic#"\t$V1, $V2, $V3, $I4", + [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src), + (tr2.vt tr2.op:$V2), + (tr2.vt tr2.op:$V3), + imm32zx8:$I4)))]> { + let Constraints = "$V1 = $V1src"; + let DisableEncoding = "$V1src"; + let M5 = type; +} + +class QuaternaryVRRd<string mnemonic, bits<16> opcode, + SDPatternOperator operator, TypedReg tr1, TypedReg tr2, + bits<4> type, SDPatternOperator m6mask, bits<4> m6or> + : InstVRRd<opcode, (outs tr1.op:$V1), + (ins tr2.op:$V2, tr2.op:$V3, tr2.op:$V4, m6mask:$M6), + mnemonic#"\t$V1, $V2, $V3, $V4, $M6", + [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), + (tr2.vt tr2.op:$V3), + (tr2.vt tr2.op:$V4), + m6mask:$M6)))], + m6or> { + let M5 = type; +} + +multiclass QuaternaryVRRdSPair<string mnemonic, bits<16> opcode, + SDPatternOperator operator, + SDPatternOperator operator_cc, TypedReg tr1, + TypedReg tr2, bits<4> type, bits<4> m6or> { + def "" : QuaternaryVRRd<mnemonic, opcode, operator, tr1, tr2, type, + imm32zx4even, !and (m6or, 14)>; + def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4", + (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, + tr2.op:$V3, tr2.op:$V4, 0)>; + let Defs = [CC] in + def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, + imm32zx4even, !add (!and (m6or, 14), 1)>; + def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4", + (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2, + tr2.op:$V3, tr2.op:$V4, 0)>; +} + class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, RegisterOperand cls, AddressingMode mode = bdaddr20only> : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2), diff --git a/llvm/lib/Target/SystemZ/SystemZInstrVector.td b/llvm/lib/Target/SystemZ/SystemZInstrVector.td new file mode 100644 index 00000000000..650cae0b35d --- /dev/null +++ b/llvm/lib/Target/SystemZ/SystemZInstrVector.td @@ -0,0 +1,751 @@ +//==- SystemZInstrVector.td - SystemZ Vector instructions ------*- tblgen-*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Move instructions +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureVector] in { + // Register move. + def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>; + + // Load GR from VR element. + def VLGVB : BinaryVRSc<"vlgvb", 0xE721, null_frag, v128b, 0>; + def VLGVH : BinaryVRSc<"vlgvh", 0xE721, null_frag, v128h, 1>; + def VLGVF : BinaryVRSc<"vlgvf", 0xE721, null_frag, v128f, 2>; + def VLGVG : BinaryVRSc<"vlgvg", 0xE721, null_frag, v128g, 3>; + + // Load VR element from GR. + def VLVGB : TernaryVRSb<"vlvgb", 0xE722, null_frag, v128b, v128b, GR32, 0>; + def VLVGH : TernaryVRSb<"vlvgh", 0xE722, null_frag, v128h, v128h, GR32, 1>; + def VLVGF : TernaryVRSb<"vlvgf", 0xE722, null_frag, v128f, v128f, GR32, 2>; + def VLVGG : TernaryVRSb<"vlvgg", 0xE722, null_frag, v128g, v128g, GR64, 3>; + + // Load VR from GRs disjoint. + def VLVGP : BinaryVRRf<"vlvgp", 0xE762, null_frag, v128g>; +} + +//===----------------------------------------------------------------------===// +// Immediate instructions +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureVector] in { + // Generate byte mask. + def VZERO : InherentVRIa<"vzero", 0xE744, 0>; + def VONE : InherentVRIa<"vone", 0xE744, 0xffff>; + def VGBM : UnaryVRIa<"vgbm", 0xE744, null_frag, v128b, imm32zx16>; + + // Generate mask. + def VGMB : BinaryVRIb<"vgmb", 0xE746, null_frag, v128b, 0>; + def VGMH : BinaryVRIb<"vgmh", 0xE746, null_frag, v128h, 1>; + def VGMF : BinaryVRIb<"vgmf", 0xE746, null_frag, v128f, 2>; + def VGMG : BinaryVRIb<"vgmg", 0xE746, null_frag, v128g, 3>; + + // Load element immediate. + def VLEIB : TernaryVRIa<"vleib", 0xE740, null_frag, + v128b, v128b, imm32sx16trunc, imm32zx4>; + def VLEIH : TernaryVRIa<"vleih", 0xE741, null_frag, + v128h, v128h, imm32sx16trunc, imm32zx3>; + def VLEIF : TernaryVRIa<"vleif", 0xE743, null_frag, + v128f, v128f, imm32sx16, imm32zx2>; + def VLEIG : TernaryVRIa<"vleig", 0xE742, null_frag, + v128g, v128g, imm64sx16, imm32zx1>; + + // Replicate immediate. + def VREPIB : UnaryVRIa<"vrepib", 0xE745, null_frag, v128b, imm32sx16, 0>; + def VREPIH : UnaryVRIa<"vrepih", 0xE745, null_frag, v128h, imm32sx16, 1>; + def VREPIF : UnaryVRIa<"vrepif", 0xE745, null_frag, v128f, imm32sx16, 2>; + def VREPIG : UnaryVRIa<"vrepig", 0xE745, null_frag, v128g, imm32sx16, 3>; +} + +//===----------------------------------------------------------------------===// +// Loads +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureVector] in { + // Load. + def VL : UnaryVRX<"vl", 0xE706, null_frag, v128any, 16>; + + // Load to block boundary. The number of loaded bytes is only known + // at run time. + def VLBB : BinaryVRX<"vlbb", 0xE707, null_frag, v128any, 0>; + + // Load count to block boundary. + let Defs = [CC] in + def LCBB : InstRXE<0xE727, (outs GR32:$R1), + (ins bdxaddr12only:$XBD2, imm32zx4:$M3), + "lcbb\t$R1, $XBD2, $M3", []>; + + // Load with length. The number of loaded bytes is only known at run time. + def VLL : BinaryVRSb<"vll", 0xE737, null_frag, 0>; + + // Load multiple. + def VLM : LoadMultipleVRSa<"vlm", 0xE736>; + + // Load and replicate + def VLREPB : UnaryVRX<"vlrepb", 0xE705, null_frag, v128b, 1, 0>; + def VLREPH : UnaryVRX<"vlreph", 0xE705, null_frag, v128h, 2, 1>; + def VLREPF : UnaryVRX<"vlrepf", 0xE705, null_frag, v128f, 4, 2>; + def VLREPG : UnaryVRX<"vlrepg", 0xE705, null_frag, v128g, 8, 3>; + + // Load logical element and zero. + def VLLEZB : UnaryVRX<"vllezb", 0xE704, null_frag, v128b, 1, 0>; + def VLLEZH : UnaryVRX<"vllezh", 0xE704, null_frag, v128h, 2, 1>; + def VLLEZF : UnaryVRX<"vllezf", 0xE704, null_frag, v128f, 4, 2>; + def VLLEZG : UnaryVRX<"vllezg", 0xE704, null_frag, v128g, 8, 3>; + + // Load element. + def VLEB : TernaryVRX<"vleb", 0xE700, null_frag, v128b, v128b, 1, imm32zx4>; + def VLEH : TernaryVRX<"vleh", 0xE701, null_frag, v128h, v128h, 2, imm32zx3>; + def VLEF : TernaryVRX<"vlef", 0xE703, null_frag, v128f, v128f, 4, imm32zx2>; + def VLEG : TernaryVRX<"vleg", 0xE702, null_frag, v128g, v128g, 8, imm32zx1>; + + // Gather element. + def VGEF : TernaryVRV<"vgef", 0xE713, 4, imm32zx2>; + def VGEG : TernaryVRV<"vgeg", 0xE712, 8, imm32zx1>; +} + +//===----------------------------------------------------------------------===// +// Stores +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureVector] in { + // Store. + def VST : StoreVRX<"vst", 0xE70E, null_frag, v128any, 16>; + + // Store with length. The number of stored bytes is only known at run time. + def VSTL : StoreLengthVRSb<"vstl", 0xE73F, null_frag, 0>; + + // Store multiple. + def VSTM : StoreMultipleVRSa<"vstm", 0xE73E>; + + // Store element. + def VSTEB : StoreBinaryVRX<"vsteb", 0xE708, null_frag, v128b, 1, imm32zx4>; + def VSTEH : StoreBinaryVRX<"vsteh", 0xE709, null_frag, v128h, 2, imm32zx3>; + def VSTEF : StoreBinaryVRX<"vstef", 0xE70B, null_frag, v128f, 4, imm32zx2>; + def VSTEG : StoreBinaryVRX<"vsteg", 0xE70A, null_frag, v128g, 8, imm32zx1>; + + // Scatter element. + def VSCEF : StoreBinaryVRV<"vscef", 0xE71B, 4, imm32zx2>; + def VSCEG : StoreBinaryVRV<"vsceg", 0xE71A, 8, imm32zx1>; +} + +//===----------------------------------------------------------------------===// +// Selects and permutes +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureVector] in { + // Merge high. + def VMRHB : BinaryVRRc<"vmrhb", 0xE761, null_frag, v128b, v128b, 0>; + def VMRHH : BinaryVRRc<"vmrhh", 0xE761, null_frag, v128h, v128h, 1>; + def VMRHF : BinaryVRRc<"vmrhf", 0xE761, null_frag, v128f, v128f, 2>; + def VMRHG : BinaryVRRc<"vmrhg", 0xE761, null_frag, v128g, v128g, 3>; + + // Merge low. + def VMRLB : BinaryVRRc<"vmrlb", 0xE760, null_frag, v128b, v128b, 0>; + def VMRLH : BinaryVRRc<"vmrlh", 0xE760, null_frag, v128h, v128h, 1>; + def VMRLF : BinaryVRRc<"vmrlf", 0xE760, null_frag, v128f, v128f, 2>; + def VMRLG : BinaryVRRc<"vmrlg", 0xE760, null_frag, v128g, v128g, 3>; + + // Permute. + def VPERM : TernaryVRRe<"vperm", 0xE78C, null_frag, v128b, v128b>; + + // Permute doubleword immediate. + def VPDI : TernaryVRRc<"vpdi", 0xE784, null_frag, v128b, v128b>; + + // Replicate. + def VREPB : BinaryVRIc<"vrepb", 0xE74D, null_frag, v128b, v128b, 0>; + def VREPH : BinaryVRIc<"vreph", 0xE74D, null_frag, v128h, v128h, 1>; + def VREPF : BinaryVRIc<"vrepf", 0xE74D, null_frag, v128f, v128f, 2>; + def VREPG : BinaryVRIc<"vrepg", 0xE74D, null_frag, v128g, v128g, 3>; + + // Select. + def VSEL : TernaryVRRe<"vsel", 0xE78D, null_frag, v128any, v128any>; +} + +//===----------------------------------------------------------------------===// +// Widening and narrowing +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureVector] in { + // Pack + def VPKH : BinaryVRRc<"vpkh", 0xE794, null_frag, v128b, v128h, 1>; + def VPKF : BinaryVRRc<"vpkf", 0xE794, null_frag, v128h, v128f, 2>; + def VPKG : BinaryVRRc<"vpkg", 0xE794, null_frag, v128f, v128g, 3>; + + // Pack saturate. + defm VPKSH : BinaryVRRbSPair<"vpksh", 0xE797, null_frag, null_frag, + v128b, v128h, 1>; + defm VPKSF : BinaryVRRbSPair<"vpksf", 0xE797, null_frag, null_frag, + v128h, v128f, 2>; + defm VPKSG : BinaryVRRbSPair<"vpksg", 0xE797, null_frag, null_frag, + v128f, v128g, 3>; + + // Pack saturate logical. + defm VPKLSH : BinaryVRRbSPair<"vpklsh", 0xE795, null_frag, null_frag, + v128b, v128h, 1>; + defm VPKLSF : BinaryVRRbSPair<"vpklsf", 0xE795, null_frag, null_frag, + v128h, v128f, 2>; + defm VPKLSG : BinaryVRRbSPair<"vpklsg", 0xE795, null_frag, null_frag, + v128f, v128g, 3>; + + // Sign-extend to doubleword. + def VSEGB : UnaryVRRa<"vsegb", 0xE75F, null_frag, v128g, v128b, 0>; + def VSEGH : UnaryVRRa<"vsegh", 0xE75F, null_frag, v128g, v128h, 1>; + def VSEGF : UnaryVRRa<"vsegf", 0xE75F, null_frag, v128g, v128f, 2>; + + // Unpack high. + def VUPHB : UnaryVRRa<"vuphb", 0xE7D7, null_frag, v128h, v128b, 0>; + def VUPHH : UnaryVRRa<"vuphh", 0xE7D7, null_frag, v128f, v128h, 1>; + def VUPHF : UnaryVRRa<"vuphf", 0xE7D7, null_frag, v128g, v128f, 2>; + + // Unpack logical high. + def VUPLHB : UnaryVRRa<"vuplhb", 0xE7D5, null_frag, v128h, v128b, 0>; + def VUPLHH : UnaryVRRa<"vuplhh", 0xE7D5, null_frag, v128f, v128h, 1>; + def VUPLHF : UnaryVRRa<"vuplhf", 0xE7D5, null_frag, v128g, v128f, 2>; + + // Unpack low. + def VUPLB : UnaryVRRa<"vuplb", 0xE7D6, null_frag, v128h, v128b, 0>; + def VUPLHW : UnaryVRRa<"vuplhw", 0xE7D6, null_frag, v128f, v128h, 1>; + def VUPLF : UnaryVRRa<"vuplf", 0xE7D6, null_frag, v128g, v128f, 2>; + + // Unpack logical low. + def VUPLLB : UnaryVRRa<"vupllb", 0xE7D4, null_frag, v128h, v128b, 0>; + def VUPLLH : UnaryVRRa<"vupllh", 0xE7D4, null_frag, v128f, v128h, 1>; + def VUPLLF : UnaryVRRa<"vupllf", 0xE7D4, null_frag, v128g, v128f, 2>; +} + +//===----------------------------------------------------------------------===// +// Integer arithmetic +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureVector] in { + // Add. + def VAB : BinaryVRRc<"vab", 0xE7F3, null_frag, v128b, v128b, 0>; + def VAH : BinaryVRRc<"vah", 0xE7F3, null_frag, v128h, v128h, 1>; + def VAF : BinaryVRRc<"vaf", 0xE7F3, null_frag, v128f, v128f, 2>; + def VAG : BinaryVRRc<"vag", 0xE7F3, null_frag, v128g, v128g, 3>; + def VAQ : BinaryVRRc<"vaq", 0xE7F3, null_frag, v128q, v128q, 4>; + + // Add compute carry. + def VACCB : BinaryVRRc<"vaccb", 0xE7F1, null_frag, v128b, v128b, 0>; + def VACCH : BinaryVRRc<"vacch", 0xE7F1, null_frag, v128h, v128h, 1>; + def VACCF : BinaryVRRc<"vaccf", 0xE7F1, null_frag, v128f, v128f, 2>; + def VACCG : BinaryVRRc<"vaccg", 0xE7F1, null_frag, v128g, v128g, 3>; + def VACCQ : BinaryVRRc<"vaccq", 0xE7F1, null_frag, v128q, v128q, 4>; + + // Add with carry. + def VACQ : TernaryVRRd<"vacq", 0xE7BB, null_frag, v128q, v128q, 4>; + + // Add with carry compute carry. + def VACCCQ : TernaryVRRd<"vacccq", 0xE7B9, null_frag, v128q, v128q, 4>; + + // And. + def VN : BinaryVRRc<"vn", 0xE768, null_frag, v128any, v128any>; + + // And with complement. + def VNC : BinaryVRRc<"vnc", 0xE769, null_frag, v128any, v128any>; + + // Average. + def VAVGB : BinaryVRRc<"vavgb", 0xE7F2, null_frag, v128b, v128b, 0>; + def VAVGH : BinaryVRRc<"vavgh", 0xE7F2, null_frag, v128h, v128h, 1>; + def VAVGF : BinaryVRRc<"vavgf", 0xE7F2, null_frag, v128f, v128f, 2>; + def VAVGG : BinaryVRRc<"vavgg", 0xE7F2, null_frag, v128g, v128g, 3>; + + // Average logical. + def VAVGLB : BinaryVRRc<"vavglb", 0xE7F0, null_frag, v128b, v128b, 0>; + def VAVGLH : BinaryVRRc<"vavglh", 0xE7F0, null_frag, v128h, v128h, 1>; + def VAVGLF : BinaryVRRc<"vavglf", 0xE7F0, null_frag, v128f, v128f, 2>; + def VAVGLG : BinaryVRRc<"vavglg", 0xE7F0, null_frag, v128g, v128g, 3>; + + // Checksum. + def VCKSM : BinaryVRRc<"vcksm", 0xE766, null_frag, v128any, v128any>; + + // Count leading zeros. + def VCLZB : UnaryVRRa<"vclzb", 0xE753, null_frag, v128b, v128b, 0>; + def VCLZH : UnaryVRRa<"vclzh", 0xE753, null_frag, v128h, v128h, 1>; + def VCLZF : UnaryVRRa<"vclzf", 0xE753, null_frag, v128f, v128f, 2>; + def VCLZG : UnaryVRRa<"vclzg", 0xE753, null_frag, v128g, v128g, 3>; + + // Count trailing zeros. + def VCTZB : UnaryVRRa<"vctzb", 0xE752, null_frag, v128b, v128b, 0>; + def VCTZH : UnaryVRRa<"vctzh", 0xE752, null_frag, v128h, v128h, 1>; + def VCTZF : UnaryVRRa<"vctzf", 0xE752, null_frag, v128f, v128f, 2>; + def VCTZG : UnaryVRRa<"vctzg", 0xE752, null_frag, v128g, v128g, 3>; + + // Exclusive or. + def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>; + + // Galois field multiply sum. + def VGFMB : BinaryVRRc<"vgfmb", 0xE7B4, null_frag, v128b, v128b, 0>; + def VGFMH : BinaryVRRc<"vgfmh", 0xE7B4, null_frag, v128h, v128h, 1>; + def VGFMF : BinaryVRRc<"vgfmf", 0xE7B4, null_frag, v128f, v128f, 2>; + def VGFMG : BinaryVRRc<"vgfmg", 0xE7B4, null_frag, v128g, v128g, 3>; + + // Galois field multiply sum and accumulate. + def VGFMAB : TernaryVRRd<"vgfmab", 0xE7BC, null_frag, v128b, v128b, 0>; + def VGFMAH : TernaryVRRd<"vgfmah", 0xE7BC, null_frag, v128h, v128h, 1>; + def VGFMAF : TernaryVRRd<"vgfmaf", 0xE7BC, null_frag, v128f, v128f, 2>; + def VGFMAG : TernaryVRRd<"vgfmag", 0xE7BC, null_frag, v128g, v128g, 3>; + + // Load complement. + def VLCB : UnaryVRRa<"vlcb", 0xE7DE, null_frag, v128b, v128b, 0>; + def VLCH : UnaryVRRa<"vlch", 0xE7DE, null_frag, v128h, v128h, 1>; + def VLCF : UnaryVRRa<"vlcf", 0xE7DE, null_frag, v128f, v128f, 2>; + def VLCG : UnaryVRRa<"vlcg", 0xE7DE, null_frag, v128g, v128g, 3>; + + // Load positive. + def VLPB : UnaryVRRa<"vlpb", 0xE7DF, null_frag, v128b, v128b, 0>; + def VLPH : UnaryVRRa<"vlph", 0xE7DF, null_frag, v128h, v128h, 1>; + def VLPF : UnaryVRRa<"vlpf", 0xE7DF, null_frag, v128f, v128f, 2>; + def VLPG : UnaryVRRa<"vlpg", 0xE7DF, null_frag, v128g, v128g, 3>; + + // Maximum. + def VMXB : BinaryVRRc<"vmxb", 0xE7FF, null_frag, v128b, v128b, 0>; + def VMXH : BinaryVRRc<"vmxh", 0xE7FF, null_frag, v128h, v128h, 1>; + def VMXF : BinaryVRRc<"vmxf", 0xE7FF, null_frag, v128f, v128f, 2>; + def VMXG : BinaryVRRc<"vmxg", 0xE7FF, null_frag, v128g, v128g, 3>; + + // Maximum logical. + def VMXLB : BinaryVRRc<"vmxlb", 0xE7FD, null_frag, v128b, v128b, 0>; + def VMXLH : BinaryVRRc<"vmxlh", 0xE7FD, null_frag, v128h, v128h, 1>; + def VMXLF : BinaryVRRc<"vmxlf", 0xE7FD, null_frag, v128f, v128f, 2>; + def VMXLG : BinaryVRRc<"vmxlg", 0xE7FD, null_frag, v128g, v128g, 3>; + + // Minimum. + def VMNB : BinaryVRRc<"vmnb", 0xE7FE, null_frag, v128b, v128b, 0>; + def VMNH : BinaryVRRc<"vmnh", 0xE7FE, null_frag, v128h, v128h, 1>; + def VMNF : BinaryVRRc<"vmnf", 0xE7FE, null_frag, v128f, v128f, 2>; + def VMNG : BinaryVRRc<"vmng", 0xE7FE, null_frag, v128g, v128g, 3>; + + // Minimum logical. + def VMNLB : BinaryVRRc<"vmnlb", 0xE7FC, null_frag, v128b, v128b, 0>; + def VMNLH : BinaryVRRc<"vmnlh", 0xE7FC, null_frag, v128h, v128h, 1>; + def VMNLF : BinaryVRRc<"vmnlf", 0xE7FC, null_frag, v128f, v128f, 2>; + def VMNLG : BinaryVRRc<"vmnlg", 0xE7FC, null_frag, v128g, v128g, 3>; + + // Multiply and add low. + def VMALB : TernaryVRRd<"vmalb", 0xE7AA, null_frag, v128b, v128b, 0>; + def VMALHW : TernaryVRRd<"vmalhw", 0xE7AA, null_frag, v128h, v128h, 1>; + def VMALF : TernaryVRRd<"vmalf", 0xE7AA, null_frag, v128f, v128f, 2>; + + // Multiply and add high. + def VMAHB : TernaryVRRd<"vmahb", 0xE7AB, null_frag, v128b, v128b, 0>; + def VMAHH : TernaryVRRd<"vmahh", 0xE7AB, null_frag, v128h, v128h, 1>; + def VMAHF : TernaryVRRd<"vmahf", 0xE7AB, null_frag, v128f, v128f, 2>; + + // Multiply and add logical high. + def VMALHB : TernaryVRRd<"vmalhb", 0xE7A9, null_frag, v128b, v128b, 0>; + def VMALHH : TernaryVRRd<"vmalhh", 0xE7A9, null_frag, v128h, v128h, 1>; + def VMALHF : TernaryVRRd<"vmalhf", 0xE7A9, null_frag, v128f, v128f, 2>; + + // Multiply and add even. + def VMAEB : TernaryVRRd<"vmaeb", 0xE7AE, null_frag, v128h, v128b, 0>; + def VMAEH : TernaryVRRd<"vmaeh", 0xE7AE, null_frag, v128f, v128h, 1>; + def VMAEF : TernaryVRRd<"vmaef", 0xE7AE, null_frag, v128g, v128f, 2>; + + // Multiply and add logical even. + def VMALEB : TernaryVRRd<"vmaleb", 0xE7AC, null_frag, v128h, v128b, 0>; + def VMALEH : TernaryVRRd<"vmaleh", 0xE7AC, null_frag, v128f, v128h, 1>; + def VMALEF : TernaryVRRd<"vmalef", 0xE7AC, null_frag, v128g, v128f, 2>; + + // Multiply and add odd. + def VMAOB : TernaryVRRd<"vmaob", 0xE7AF, null_frag, v128h, v128b, 0>; + def VMAOH : TernaryVRRd<"vmaoh", 0xE7AF, null_frag, v128f, v128h, 1>; + def VMAOF : TernaryVRRd<"vmaof", 0xE7AF, null_frag, v128g, v128f, 2>; + + // Multiply and add logical odd. + def VMALOB : TernaryVRRd<"vmalob", 0xE7AD, null_frag, v128h, v128b, 0>; + def VMALOH : TernaryVRRd<"vmaloh", 0xE7AD, null_frag, v128f, v128h, 1>; + def VMALOF : TernaryVRRd<"vmalof", 0xE7AD, null_frag, v128g, v128f, 2>; + + // Multiply high. + def VMHB : BinaryVRRc<"vmhb", 0xE7A3, null_frag, v128b, v128b, 0>; + def VMHH : BinaryVRRc<"vmhh", 0xE7A3, null_frag, v128h, v128h, 1>; + def VMHF : BinaryVRRc<"vmhf", 0xE7A3, null_frag, v128f, v128f, 2>; + + // Multiply logical high. + def VMLHB : BinaryVRRc<"vmlhb", 0xE7A1, null_frag, v128b, v128b, 0>; + def VMLHH : BinaryVRRc<"vmlhh", 0xE7A1, null_frag, v128h, v128h, 1>; + def VMLHF : BinaryVRRc<"vmlhf", 0xE7A1, null_frag, v128f, v128f, 2>; + + // Multiply low. + def VMLB : BinaryVRRc<"vmlb", 0xE7A2, null_frag, v128b, v128b, 0>; + def VMLHW : BinaryVRRc<"vmlhw", 0xE7A2, null_frag, v128h, v128h, 1>; + def VMLF : BinaryVRRc<"vmlf", 0xE7A2, null_frag, v128f, v128f, 2>; + + // Multiply even. + def VMEB : BinaryVRRc<"vmeb", 0xE7A6, null_frag, v128h, v128b, 0>; + def VMEH : BinaryVRRc<"vmeh", 0xE7A6, null_frag, v128f, v128h, 1>; + def VMEF : BinaryVRRc<"vmef", 0xE7A6, null_frag, v128g, v128f, 2>; + + // Multiply logical even. + def VMLEB : BinaryVRRc<"vmleb", 0xE7A4, null_frag, v128h, v128b, 0>; + def VMLEH : BinaryVRRc<"vmleh", 0xE7A4, null_frag, v128f, v128h, 1>; + def VMLEF : BinaryVRRc<"vmlef", 0xE7A4, null_frag, v128g, v128f, 2>; + + // Multiply odd. + def VMOB : BinaryVRRc<"vmob", 0xE7A7, null_frag, v128h, v128b, 0>; + def VMOH : BinaryVRRc<"vmoh", 0xE7A7, null_frag, v128f, v128h, 1>; + def VMOF : BinaryVRRc<"vmof", 0xE7A7, null_frag, v128g, v128f, 2>; + + // Multiply logical odd. + def VMLOB : BinaryVRRc<"vmlob", 0xE7A5, null_frag, v128h, v128b, 0>; + def VMLOH : BinaryVRRc<"vmloh", 0xE7A5, null_frag, v128f, v128h, 1>; + def VMLOF : BinaryVRRc<"vmlof", 0xE7A5, null_frag, v128g, v128f, 2>; + + // Nor. + def VNO : BinaryVRRc<"vno", 0xE76B, null_frag, v128any, v128any>; + + // Or. + def VO : BinaryVRRc<"vo", 0xE76A, null_frag, v128any, v128any>; + + // Population count. + def VPOPCT : BinaryVRRa<"vpopct", 0xE750>; + + // Element rotate left logical (with vector shift amount). + def VERLLVB : BinaryVRRc<"verllvb", 0xE773, null_frag, v128b, v128b, 0>; + def VERLLVH : BinaryVRRc<"verllvh", 0xE773, null_frag, v128h, v128h, 1>; + def VERLLVF : BinaryVRRc<"verllvf", 0xE773, null_frag, v128f, v128f, 2>; + def VERLLVG : BinaryVRRc<"verllvg", 0xE773, null_frag, v128g, v128g, 3>; + + // Element rotate left logical (with scalar shift amount). + def VERLLB : BinaryVRSa<"verllb", 0xE733, null_frag, v128b, v128b, 0>; + def VERLLH : BinaryVRSa<"verllh", 0xE733, null_frag, v128h, v128h, 1>; + def VERLLF : BinaryVRSa<"verllf", 0xE733, null_frag, v128f, v128f, 2>; + def VERLLG : BinaryVRSa<"verllg", 0xE733, null_frag, v128g, v128g, 3>; + + // Element rotate and insert under mask. + def VERIMB : QuaternaryVRId<"verimb", 0xE772, null_frag, v128b, v128b, 0>; + def VERIMH : QuaternaryVRId<"verimh", 0xE772, null_frag, v128h, v128h, 1>; + def VERIMF : QuaternaryVRId<"verimf", 0xE772, null_frag, v128f, v128f, 2>; + def VERIMG : QuaternaryVRId<"verimg", 0xE772, null_frag, v128g, v128g, 3>; + + // Element shift left (with vector shift amount). + def VESLVB : BinaryVRRc<"veslvb", 0xE770, null_frag, v128b, v128b, 0>; + def VESLVH : BinaryVRRc<"veslvh", 0xE770, null_frag, v128h, v128h, 1>; + def VESLVF : BinaryVRRc<"veslvf", 0xE770, null_frag, v128f, v128f, 2>; + def VESLVG : BinaryVRRc<"veslvg", 0xE770, null_frag, v128g, v128g, 3>; + + // Element shift left (with scalar shift amount). + def VESLB : BinaryVRSa<"veslb", 0xE730, null_frag, v128b, v128b, 0>; + def VESLH : BinaryVRSa<"veslh", 0xE730, null_frag, v128h, v128h, 1>; + def VESLF : BinaryVRSa<"veslf", 0xE730, null_frag, v128f, v128f, 2>; + def VESLG : BinaryVRSa<"veslg", 0xE730, null_frag, v128g, v128g, 3>; + + // Element shift right arithmetic (with vector shift amount). + def VESRAVB : BinaryVRRc<"vesravb", 0xE77A, null_frag, v128b, v128b, 0>; + def VESRAVH : BinaryVRRc<"vesravh", 0xE77A, null_frag, v128h, v128h, 1>; + def VESRAVF : BinaryVRRc<"vesravf", 0xE77A, null_frag, v128f, v128f, 2>; + def VESRAVG : BinaryVRRc<"vesravg", 0xE77A, null_frag, v128g, v128g, 3>; + + // Element shift right arithmetic (with scalar shift amount). + def VESRAB : BinaryVRSa<"vesrab", 0xE73A, null_frag, v128b, v128b, 0>; + def VESRAH : BinaryVRSa<"vesrah", 0xE73A, null_frag, v128h, v128h, 1>; + def VESRAF : BinaryVRSa<"vesraf", 0xE73A, null_frag, v128f, v128f, 2>; + def VESRAG : BinaryVRSa<"vesrag", 0xE73A, null_frag, v128g, v128g, 3>; + + // Element shift right logical (with vector shift amount). + def VESRLVB : BinaryVRRc<"vesrlvb", 0xE778, null_frag, v128b, v128b, 0>; + def VESRLVH : BinaryVRRc<"vesrlvh", 0xE778, null_frag, v128h, v128h, 1>; + def VESRLVF : BinaryVRRc<"vesrlvf", 0xE778, null_frag, v128f, v128f, 2>; + def VESRLVG : BinaryVRRc<"vesrlvg", 0xE778, null_frag, v128g, v128g, 3>; + + // Element shift right logical (with scalar shift amount). + def VESRLB : BinaryVRSa<"vesrlb", 0xE738, null_frag, v128b, v128b, 0>; + def VESRLH : BinaryVRSa<"vesrlh", 0xE738, null_frag, v128h, v128h, 1>; + def VESRLF : BinaryVRSa<"vesrlf", 0xE738, null_frag, v128f, v128f, 2>; + def VESRLG : BinaryVRSa<"vesrlg", 0xE738, null_frag, v128g, v128g, 3>; + + // Shift left. + def VSL : BinaryVRRc<"vsl", 0xE774, null_frag, v128b, v128b>; + + // Shift left by byte. + def VSLB : BinaryVRRc<"vslb", 0xE775, null_frag, v128b, v128b>; + + // Shift left double by byte. + def VSLDB : TernaryVRId<"vsldb", 0xE777, null_frag, v128b, v128b, 0>; + + // Shift right arithmetic. + def VSRA : BinaryVRRc<"vsra", 0xE77E, null_frag, v128b, v128b>; + + // Shift right arithmetic by byte. + def VSRAB : BinaryVRRc<"vsrab", 0xE77F, null_frag, v128b, v128b>; + + // Shift right logical. + def VSRL : BinaryVRRc<"vsrl", 0xE77C, null_frag, v128b, v128b>; + + // Shift right logical by byte. + def VSRLB : BinaryVRRc<"vsrlb", 0xE77D, null_frag, v128b, v128b>; + + // Subtract. + def VSB : BinaryVRRc<"vsb", 0xE7F7, null_frag, v128b, v128b, 0>; + def VSH : BinaryVRRc<"vsh", 0xE7F7, null_frag, v128h, v128h, 1>; + def VSF : BinaryVRRc<"vsf", 0xE7F7, null_frag, v128f, v128f, 2>; + def VSG : BinaryVRRc<"vsg", 0xE7F7, null_frag, v128g, v128g, 3>; + def VSQ : BinaryVRRc<"vsq", 0xE7F7, null_frag, v128q, v128q, 4>; + + // Subtract compute borrow indication. + def VSCBIB : BinaryVRRc<"vscbib", 0xE7F5, null_frag, v128b, v128b, 0>; + def VSCBIH : BinaryVRRc<"vscbih", 0xE7F5, null_frag, v128h, v128h, 1>; + def VSCBIF : BinaryVRRc<"vscbif", 0xE7F5, null_frag, v128f, v128f, 2>; + def VSCBIG : BinaryVRRc<"vscbig", 0xE7F5, null_frag, v128g, v128g, 3>; + def VSCBIQ : BinaryVRRc<"vscbiq", 0xE7F5, null_frag, v128q, v128q, 4>; + + // Subtract with borrow indication. + def VSBIQ : TernaryVRRd<"vsbiq", 0xE7BF, null_frag, v128q, v128q, 4>; + + // Subtract with borrow compute borrow indication. + def VSBCBIQ : TernaryVRRd<"vsbcbiq", 0xE7BD, null_frag, v128q, v128q, 4>; + + // Sum across doubleword. + def VSUMGH : BinaryVRRc<"vsumgh", 0xE765, null_frag, v128g, v128h, 1>; + def VSUMGF : BinaryVRRc<"vsumgf", 0xE765, null_frag, v128g, v128f, 2>; + + // Sum across quadword. + def VSUMQF : BinaryVRRc<"vsumqf", 0xE767, null_frag, v128q, v128f, 2>; + def VSUMQG : BinaryVRRc<"vsumqg", 0xE767, null_frag, v128q, v128g, 3>; + + // Sum across word. + def VSUMB : BinaryVRRc<"vsumb", 0xE764, null_frag, v128f, v128b, 0>; + def VSUMH : BinaryVRRc<"vsumh", 0xE764, null_frag, v128f, v128h, 1>; +} + +//===----------------------------------------------------------------------===// +// Integer comparison +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureVector] in { + // Element compare. + let Defs = [CC] in { + def VECB : CompareVRRa<"vecb", 0xE7DB, null_frag, v128b, 0>; + def VECH : CompareVRRa<"vech", 0xE7DB, null_frag, v128h, 1>; + def VECF : CompareVRRa<"vecf", 0xE7DB, null_frag, v128f, 2>; + def VECG : CompareVRRa<"vecg", 0xE7DB, null_frag, v128g, 3>; + } + + // Element compare logical. + let Defs = [CC] in { + def VECLB : CompareVRRa<"veclb", 0xE7D9, null_frag, v128b, 0>; + def VECLH : CompareVRRa<"veclh", 0xE7D9, null_frag, v128h, 1>; + def VECLF : CompareVRRa<"veclf", 0xE7D9, null_frag, v128f, 2>; + def VECLG : CompareVRRa<"veclg", 0xE7D9, null_frag, v128g, 3>; + } + + // Compare equal. + defm VCEQB : BinaryVRRbSPair<"vceqb", 0xE7F8, null_frag, null_frag, + v128b, v128b, 0>; + defm VCEQH : BinaryVRRbSPair<"vceqh", 0xE7F8, null_frag, null_frag, + v128h, v128h, 1>; + defm VCEQF : BinaryVRRbSPair<"vceqf", 0xE7F8, null_frag, null_frag, + v128f, v128f, 2>; + defm VCEQG : BinaryVRRbSPair<"vceqg", 0xE7F8, null_frag, null_frag, + v128g, v128g, 3>; + + // Compare high. + defm VCHB : BinaryVRRbSPair<"vchb", 0xE7FB, null_frag, null_frag, + v128b, v128b, 0>; + defm VCHH : BinaryVRRbSPair<"vchh", 0xE7FB, null_frag, null_frag, + v128h, v128h, 1>; + defm VCHF : BinaryVRRbSPair<"vchf", 0xE7FB, null_frag, null_frag, + v128f, v128f, 2>; + defm VCHG : BinaryVRRbSPair<"vchg", 0xE7FB, null_frag, null_frag, + v128g, v128g, 3>; + + // Compare high logical. + defm VCHLB : BinaryVRRbSPair<"vchlb", 0xE7F9, null_frag, null_frag, + v128b, v128b, 0>; + defm VCHLH : BinaryVRRbSPair<"vchlh", 0xE7F9, null_frag, null_frag, + v128h, v128h, 1>; + defm VCHLF : BinaryVRRbSPair<"vchlf", 0xE7F9, null_frag, null_frag, + v128f, v128f, 2>; + defm VCHLG : BinaryVRRbSPair<"vchlg", 0xE7F9, null_frag, null_frag, + v128g, v128g, 3>; + + // Test under mask. + let Defs = [CC] in + def VTM : CompareVRRa<"vtm", 0xE7D8, null_frag, v128any, 0>; +} + +//===----------------------------------------------------------------------===// +// Floating-point arithmetic +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureVector] in { + // Add. + def VFADB : BinaryVRRc<"vfadb", 0xE7E3, null_frag, v128db, v128db, 3, 0>; + def WFADB : BinaryVRRc<"wfadb", 0xE7E3, null_frag, v64db, v64db, 3, 8>; + + // Convert from fixed 64-bit. + def VCDGB : TernaryVRRa<"vcdgb", 0xE7C3, null_frag, v128db, v128g, 3, 0>; + def WCDGB : TernaryVRRa<"wcdgb", 0xE7C3, null_frag, v64db, v64g, 3, 8>; + + // Convert from logical 64-bit. + def VCDLGB : TernaryVRRa<"vcdlgb", 0xE7C1, null_frag, v128db, v128g, 3, 0>; + def WCDLGB : TernaryVRRa<"wcdlgb", 0xE7C1, null_frag, v64db, v64g, 3, 8>; + + // Convert to fixed 64-bit. + def VCGDB : TernaryVRRa<"vcgdb", 0xE7C2, null_frag, v128g, v128db, 3, 0>; + def WCGDB : TernaryVRRa<"wcgdb", 0xE7C2, null_frag, v64g, v64db, 3, 8>; + + // Convert to logical 64-bit. + def VCLGDB : TernaryVRRa<"vclgdb", 0xE7C0, null_frag, v128g, v128db, 3, 0>; + def WCLGDB : TernaryVRRa<"wclgdb", 0xE7C0, null_frag, v64g, v64db, 3, 8>; + + // Divide. + def VFDDB : BinaryVRRc<"vfddb", 0xE7E5, null_frag, v128db, v128db, 3, 0>; + def WFDDB : BinaryVRRc<"wfddb", 0xE7E5, null_frag, v64db, v64db, 3, 8>; + + // Load FP integer. + def VFIDB : TernaryVRRa<"vfidb", 0xE7C7, null_frag, v128db, v128db, 3, 0>; + def WFIDB : TernaryVRRa<"wfidb", 0xE7C7, null_frag, v64db, v64db, 3, 8>; + + // Load lengthened. + def VLDEB : UnaryVRRa<"vldeb", 0xE7C4, null_frag, v128db, v128eb, 2, 0>; + def WLDEB : UnaryVRRa<"wldeb", 0xE7C4, null_frag, v64db, v32eb, 2, 8>; + + // Load rounded, + def VLEDB : TernaryVRRa<"vledb", 0xE7C5, null_frag, v128eb, v128db, 3, 0>; + def WLEDB : TernaryVRRa<"wledb", 0xE7C5, null_frag, v32eb, v64db, 3, 8>; + + // Multiply. + def VFMDB : BinaryVRRc<"vfmdb", 0xE7E7, null_frag, v128db, v128db, 3, 0>; + def WFMDB : BinaryVRRc<"wfmdb", 0xE7E7, null_frag, v64db, v64db, 3, 8>; + + // Multiply and add. + def VFMADB : TernaryVRRe<"vfmadb", 0xE78F, null_frag, v128db, v128db, 0, 3>; + def WFMADB : TernaryVRRe<"wfmadb", 0xE78F, null_frag, v64db, v64db, 8, 3>; + + // Multiply and subtract. + def VFMSDB : TernaryVRRe<"vfmsdb", 0xE78E, null_frag, v128db, v128db, 0, 3>; + def WFMSDB : TernaryVRRe<"wfmsdb", 0xE78E, null_frag, v64db, v64db, 8, 3>; + + // Load complement, + def VFLCDB : UnaryVRRa<"vflcdb", 0xE7CC, null_frag, v128db, v128db, 3, 0, 0>; + def WFLCDB : UnaryVRRa<"wflcdb", 0xE7CC, null_frag, v64db, v64db, 3, 8, 0>; + + // Load negative. + def VFLNDB : UnaryVRRa<"vflndb", 0xE7CC, null_frag, v128db, v128db, 3, 0, 1>; + def WFLNDB : UnaryVRRa<"wflndb", 0xE7CC, null_frag, v64db, v64db, 3, 8, 1>; + + // Load positive. + def VFLPDB : UnaryVRRa<"vflpdb", 0xE7CC, null_frag, v128db, v128db, 3, 0, 2>; + def WFLPDB : UnaryVRRa<"wflpdb", 0xE7CC, null_frag, v64db, v64db, 3, 8, 2>; + + // Square root. + def VFSQDB : UnaryVRRa<"vfsqdb", 0xE7CE, null_frag, v128db, v128db, 3, 0>; + def WFSQDB : UnaryVRRa<"wfsqdb", 0xE7CE, null_frag, v64db, v64db, 3, 8>; + + // Subtract. + def VFSDB : BinaryVRRc<"vfsdb", 0xE7E2, null_frag, v128db, v128db, 3, 0>; + def WFSDB : BinaryVRRc<"wfsdb", 0xE7E2, null_frag, v64db, v64db, 3, 8>; + + // Test data class immediate. + let Defs = [CC] in { + def VFTCIDB : BinaryVRIe<"vftcidb", 0xE74A, null_frag, v128g, v128db, 3, 0>; + def WFTCIDB : BinaryVRIe<"wftcidb", 0xE74A, null_frag, v64g, v64db, 3, 8>; + } +} + +//===----------------------------------------------------------------------===// +// Floating-point comparison +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureVector] in { + // Compare scalar. + let Defs = [CC] in + def WFCDB : CompareVRRa<"wfcdb", 0xE7CB, null_frag, v64db, 3>; + + // Compare and signal scalar. + let Defs = [CC] in + def WFKDB : CompareVRRa<"wfkdb", 0xE7CA, null_frag, v64db, 3>; + + // Compare equal. + defm VFCEDB : BinaryVRRcSPair<"vfcedb", 0xE7E8, null_frag, null_frag, + v128g, v128db, 3, 0>; + defm WFCEDB : BinaryVRRcSPair<"wfcedb", 0xE7E8, null_frag, null_frag, + v64g, v64db, 3, 8>; + + // Compare high. + defm VFCHDB : BinaryVRRcSPair<"vfchdb", 0xE7EB, null_frag, null_frag, + v128g, v128db, 3, 0>; + defm WFCHDB : BinaryVRRcSPair<"wfchdb", 0xE7EB, null_frag, null_frag, + v64g, v64db, 3, 8>; + + // Compare high or equal. + defm VFCHEDB : BinaryVRRcSPair<"vfchedb", 0xE7EA, null_frag, null_frag, + v128g, v128db, 3, 0>; + defm WFCHEDB : BinaryVRRcSPair<"wfchedb", 0xE7EA, null_frag, null_frag, + v64g, v64db, 3, 8>; +} + +//===----------------------------------------------------------------------===// +// String instructions +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureVector] in { + defm VFAEB : TernaryVRRbSPair<"vfaeb", 0xE782, null_frag, null_frag, + v128b, v128b, 0, 0>; + defm VFAEH : TernaryVRRbSPair<"vfaeh", 0xE782, null_frag, null_frag, + v128h, v128h, 1, 0>; + defm VFAEF : TernaryVRRbSPair<"vfaef", 0xE782, null_frag, null_frag, + v128f, v128f, 2, 0>; + defm VFAEZB : TernaryVRRbSPair<"vfaezb", 0xE782, null_frag, null_frag, + v128b, v128b, 0, 2>; + defm VFAEZH : TernaryVRRbSPair<"vfaezh", 0xE782, null_frag, null_frag, + v128h, v128h, 1, 2>; + defm VFAEZF : TernaryVRRbSPair<"vfaezf", 0xE782, null_frag, null_frag, + v128f, v128f, 2, 2>; + + defm VFEEB : BinaryVRRbSPair<"vfeeb", 0xE780, null_frag, null_frag, + v128b, v128b, 0, 0, 1>; + defm VFEEH : BinaryVRRbSPair<"vfeeh", 0xE780, null_frag, null_frag, + v128h, v128h, 1, 0, 1>; + defm VFEEF : BinaryVRRbSPair<"vfeef", 0xE780, null_frag, null_frag, + v128f, v128f, 2, 0, 1>; + defm VFEEZB : BinaryVRRbSPair<"vfeezb", 0xE780, null_frag, null_frag, + v128b, v128b, 0, 2, 3>; + defm VFEEZH : BinaryVRRbSPair<"vfeezh", 0xE780, null_frag, null_frag, + v128h, v128h, 1, 2, 3>; + defm VFEEZF : BinaryVRRbSPair<"vfeezf", 0xE780, null_frag, null_frag, + v128f, v128f, 2, 2, 3>; + + defm VFENEB : BinaryVRRbSPair<"vfeneb", 0xE781, null_frag, null_frag, + v128b, v128b, 0, 0, 1>; + defm VFENEH : BinaryVRRbSPair<"vfeneh", 0xE781, null_frag, null_frag, + v128h, v128h, 1, 0, 1>; + defm VFENEF : BinaryVRRbSPair<"vfenef", 0xE781, null_frag, null_frag, + v128f, v128f, 2, 0, 1>; + defm VFENEZB : BinaryVRRbSPair<"vfenezb", 0xE781, null_frag, null_frag, + v128b, v128b, 0, 2, 3>; + defm VFENEZH : BinaryVRRbSPair<"vfenezh", 0xE781, null_frag, null_frag, + v128h, v128h, 1, 2, 3>; + defm VFENEZF : BinaryVRRbSPair<"vfenezf", 0xE781, null_frag, null_frag, + v128f, v128f, 2, 2, 3>; + + defm VISTRB : UnaryVRRaSPair<"vistrb", 0xE75C, null_frag, null_frag, + v128b, v128b, 0>; + defm VISTRH : UnaryVRRaSPair<"vistrh", 0xE75C, null_frag, null_frag, + v128h, v128h, 1>; + defm VISTRF : UnaryVRRaSPair<"vistrf", 0xE75C, null_frag, null_frag, + v128f, v128f, 2>; + + defm VSTRCB : QuaternaryVRRdSPair<"vstrcb", 0xE78A, null_frag, null_frag, + v128b, v128b, 0, 0>; + defm VSTRCH : QuaternaryVRRdSPair<"vstrch", 0xE78A, null_frag, null_frag, + v128h, v128h, 1, 0>; + defm VSTRCF : QuaternaryVRRdSPair<"vstrcf", 0xE78A, null_frag, null_frag, + v128f, v128f, 2, 0>; + defm VSTRCZB : QuaternaryVRRdSPair<"vstrczb", 0xE78A, null_frag, null_frag, + v128b, v128b, 0, 2>; + defm VSTRCZH : QuaternaryVRRdSPair<"vstrczh", 0xE78A, null_frag, null_frag, + v128h, v128h, 1, 2>; + defm VSTRCZF : QuaternaryVRRdSPair<"vstrczf", 0xE78A, null_frag, null_frag, + v128f, v128f, 2, 2>; +} diff --git a/llvm/lib/Target/SystemZ/SystemZOperands.td b/llvm/lib/Target/SystemZ/SystemZOperands.td index 94a682d1465..9af90d492cf 100644 --- a/llvm/lib/Target/SystemZ/SystemZOperands.td +++ b/llvm/lib/Target/SystemZ/SystemZOperands.td @@ -78,6 +78,22 @@ class AddressAsmOperand<string format, string bitsize, string dispsize, let RenderMethod = "add"##format##"Operands"; } +// Constructs an instruction operand for an addressing mode. FORMAT, +// BITSIZE, DISPSIZE and LENGTH are the parameters to an associated +// AddressAsmOperand. OPERANDS is a list of individual operands +// (base register, displacement, etc.). +class AddressOperand<string bitsize, string dispsize, string length, + string format, dag operands> + : Operand<!cast<ValueType>("i"##bitsize)> { + let PrintMethod = "print"##format##"Operand"; + let EncoderMethod = "get"##format##dispsize##length##"Encoding"; + let DecoderMethod = + "decode"##format##bitsize##"Disp"##dispsize##length##"Operand"; + let MIOperandInfo = operands; + let ParserMatchClass = + !cast<AddressAsmOperand>(format##bitsize##"Disp"##dispsize##length); +} + // Constructs both a DAG pattern and instruction operand for an addressing mode. // FORMAT, BITSIZE, DISPSIZE and LENGTH are the parameters to an associated // AddressAsmOperand. OPERANDS is a list of NUMOPS individual operands @@ -93,15 +109,7 @@ class AddressingMode<string seltype, string bitsize, string dispsize, : ComplexPattern<!cast<ValueType>("i"##bitsize), numops, "select"##seltype##dispsize##suffix##length, [add, sub, or, frameindex, z_adjdynalloc]>, - Operand<!cast<ValueType>("i"##bitsize)> { - let PrintMethod = "print"##format##"Operand"; - let EncoderMethod = "get"##format##dispsize##length##"Encoding"; - let DecoderMethod = - "decode"##format##bitsize##"Disp"##dispsize##length##"Operand"; - let MIOperandInfo = operands; - let ParserMatchClass = - !cast<AddressAsmOperand>(format##bitsize##"Disp"##dispsize##length); -} + AddressOperand<bitsize, dispsize, length, format, operands>; // An addressing mode with a base and displacement but no index. class BDMode<string type, string bitsize, string dispsize, string suffix> @@ -125,6 +133,13 @@ class BDLMode<string type, string bitsize, string dispsize, string suffix, !cast<Immediate>("disp"##dispsize##"imm"##bitsize), !cast<Immediate>("imm"##bitsize))>; +// An addressing mode with a base, displacement and a vector index. +class BDVMode<string bitsize, string dispsize> + : AddressOperand<bitsize, dispsize, "", "BDVAddr", + (ops !cast<RegisterOperand>("ADDR"##bitsize), + !cast<Immediate>("disp"##dispsize##"imm"##bitsize), + !cast<RegisterOperand>("VR128"))>; + //===----------------------------------------------------------------------===// // Extracting immediate operands from nodes // These all create MVT::i64 nodes to ensure the value is not sign-extended @@ -179,6 +194,18 @@ def UIMM8 : SDNodeXForm<imm, [{ MVT::i64); }]>; +// Truncate an immediate to a 8-bit unsigned quantity and mask off low bit. +def UIMM8EVEN : SDNodeXForm<imm, [{ + return CurDAG->getTargetConstant(N->getZExtValue() & 0xfe, SDLoc(N), + MVT::i64); +}]>; + +// Truncate an immediate to a 12-bit unsigned quantity. +def UIMM12 : SDNodeXForm<imm, [{ + return CurDAG->getTargetConstant(N->getZExtValue() & 0xfff, SDLoc(N), + MVT::i64); +}]>; + // Truncate an immediate to a 16-bit signed quantity. def SIMM16 : SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), SDLoc(N), @@ -213,10 +240,14 @@ def NEGIMM32 : SDNodeXForm<imm, [{ // Immediate asm operands. //===----------------------------------------------------------------------===// +def U1Imm : ImmediateAsmOperand<"U1Imm">; +def U2Imm : ImmediateAsmOperand<"U2Imm">; +def U3Imm : ImmediateAsmOperand<"U3Imm">; def U4Imm : ImmediateAsmOperand<"U4Imm">; def U6Imm : ImmediateAsmOperand<"U6Imm">; def S8Imm : ImmediateAsmOperand<"S8Imm">; def U8Imm : ImmediateAsmOperand<"U8Imm">; +def U12Imm : ImmediateAsmOperand<"U12Imm">; def S16Imm : ImmediateAsmOperand<"S16Imm">; def U16Imm : ImmediateAsmOperand<"U16Imm">; def S32Imm : ImmediateAsmOperand<"S32Imm">; @@ -247,10 +278,28 @@ def imm32lh16c : Immediate<i32, [{ }], LH16, "U16Imm">; // Short immediates +def imm32zx1 : Immediate<i32, [{ + return isUInt<1>(N->getZExtValue()); +}], NOOP_SDNodeXForm, "U1Imm">; + +def imm32zx2 : Immediate<i32, [{ + return isUInt<2>(N->getZExtValue()); +}], NOOP_SDNodeXForm, "U2Imm">; + +def imm32zx3 : Immediate<i32, [{ + return isUInt<3>(N->getZExtValue()); +}], NOOP_SDNodeXForm, "U3Imm">; + def imm32zx4 : Immediate<i32, [{ return isUInt<4>(N->getZExtValue()); }], NOOP_SDNodeXForm, "U4Imm">; +// Note: this enforces an even value during code generation only. +// When used from the assembler, any 4-bit value is allowed. +def imm32zx4even : Immediate<i32, [{ + return isUInt<4>(N->getZExtValue()); +}], UIMM8EVEN, "U4Imm">; + def imm32zx6 : Immediate<i32, [{ return isUInt<6>(N->getZExtValue()); }], NOOP_SDNodeXForm, "U6Imm">; @@ -265,6 +314,10 @@ def imm32zx8 : Immediate<i32, [{ def imm32zx8trunc : Immediate<i32, [{}], UIMM8, "U8Imm">; +def imm32zx12 : Immediate<i32, [{ + return isUInt<12>(N->getZExtValue()); +}], UIMM12, "U12Imm">; + def imm32sx16 : Immediate<i32, [{ return isInt<16>(N->getSExtValue()); }], SIMM16, "S16Imm">; @@ -445,6 +498,7 @@ def BDAddr64Disp20 : AddressAsmOperand<"BDAddr", "64", "20">; def BDXAddr64Disp12 : AddressAsmOperand<"BDXAddr", "64", "12">; def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">; def BDLAddr64Disp12Len8 : AddressAsmOperand<"BDLAddr", "64", "12", "Len8">; +def BDVAddr64Disp12 : AddressAsmOperand<"BDVAddr", "64", "12">; // DAG patterns and operands for addressing modes. Each mode has // the form <type><range><group>[<len>] where: @@ -457,6 +511,7 @@ def BDLAddr64Disp12Len8 : AddressAsmOperand<"BDLAddr", "64", "12", "Len8">; // laaddr : like bdxaddr, but used for Load Address operations // dynalloc : base + displacement + index + ADJDYNALLOC // bdladdr : base + displacement with a length field +// bdvaddr : base + displacement with a vector index // // <range> is one of: // 12 : the displacement is an unsigned 12-bit value @@ -489,6 +544,7 @@ def dynalloc12only : BDXMode<"DynAlloc", "64", "12", "Only">; def laaddr12pair : BDXMode<"LAAddr", "64", "12", "Pair">; def laaddr20pair : BDXMode<"LAAddr", "64", "20", "Pair">; def bdladdr12onlylen8 : BDLMode<"BDLAddr", "64", "12", "Only", "8">; +def bdvaddr12only : BDVMode< "64", "12">; //===----------------------------------------------------------------------===// // Miscellaneous diff --git a/llvm/lib/Target/SystemZ/SystemZProcessors.td b/llvm/lib/Target/SystemZ/SystemZProcessors.td index 15614c970cd..32fbe5ae9ef 100644 --- a/llvm/lib/Target/SystemZ/SystemZProcessors.td +++ b/llvm/lib/Target/SystemZ/SystemZProcessors.td @@ -70,6 +70,12 @@ def FeatureProcessorAssist : SystemZFeature< "Assume that the processor-assist facility is installed" >; +def FeatureVector : SystemZFeature< + "vector", "Vector", + "Assume that the vectory facility is installed" +>; +def FeatureNoVector : SystemZMissingFeature<"Vector">; + def : Processor<"generic", NoItineraries, []>; def : Processor<"z10", NoItineraries, []>; def : Processor<"z196", NoItineraries, @@ -82,3 +88,9 @@ def : Processor<"zEC12", NoItineraries, FeatureFastSerialization, FeatureInterlockedAccess1, FeatureMiscellaneousExtensions, FeatureTransactionalExecution, FeatureProcessorAssist]>; +def : Processor<"z13", NoItineraries, + [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord, + FeatureFPExtension, FeaturePopulationCount, + FeatureFastSerialization, FeatureInterlockedAccess1, + FeatureTransactionalExecution, FeatureProcessorAssist, + FeatureVector]>; diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td index c980ea50930..85aa0a62cc7 100644 --- a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td +++ b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td @@ -26,21 +26,23 @@ def subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_lh32. def subreg_l64 : SubRegIndex<64, 0>; def subreg_h64 : SubRegIndex<64, 64>; def subreg_r32 : SubRegIndex<32, 32>; // Reinterpret a wider reg as 32 bits. +def subreg_r64 : SubRegIndex<64, 64>; // Reinterpret a wider reg as 64 bits. def subreg_hh32 : ComposedSubRegIndex<subreg_h64, subreg_h32>; def subreg_hl32 : ComposedSubRegIndex<subreg_h64, subreg_l32>; def subreg_hr32 : ComposedSubRegIndex<subreg_h64, subreg_r32>; } -// Define a register class that contains values of type TYPE and an +// Define a register class that contains values of types TYPES and an // associated operand called NAME. SIZE is the size and alignment // of the registers and REGLIST is the list of individual registers. -multiclass SystemZRegClass<string name, ValueType type, int size, dag regList> { +multiclass SystemZRegClass<string name, list<ValueType> types, int size, + dag regList> { def AsmOperand : AsmOperandClass { let Name = name; let ParserMethod = "parse"##name; let RenderMethod = "addRegOperands"; } - def Bit : RegisterClass<"SystemZ", [type], size, regList> { + def Bit : RegisterClass<"SystemZ", types, size, regList> { let Size = size; } def "" : RegisterOperand<!cast<RegisterClass>(name##"Bit")> { @@ -86,16 +88,19 @@ foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in { /// Allocate the callee-saved R6-R13 backwards. That way they can be saved /// together with R14 and R15 in one prolog instruction. -defm GR32 : SystemZRegClass<"GR32", i32, 32, (add (sequence "R%uL", 0, 5), - (sequence "R%uL", 15, 6))>; -defm GRH32 : SystemZRegClass<"GRH32", i32, 32, (add (sequence "R%uH", 0, 5), - (sequence "R%uH", 15, 6))>; -defm GR64 : SystemZRegClass<"GR64", i64, 64, (add (sequence "R%uD", 0, 5), - (sequence "R%uD", 15, 6))>; +defm GR32 : SystemZRegClass<"GR32", [i32], 32, + (add (sequence "R%uL", 0, 5), + (sequence "R%uL", 15, 6))>; +defm GRH32 : SystemZRegClass<"GRH32", [i32], 32, + (add (sequence "R%uH", 0, 5), + (sequence "R%uH", 15, 6))>; +defm GR64 : SystemZRegClass<"GR64", [i64], 64, + (add (sequence "R%uD", 0, 5), + (sequence "R%uD", 15, 6))>; // Combine the low and high GR32s into a single class. This can only be // used for virtual registers if the high-word facility is available. -defm GRX32 : SystemZRegClass<"GRX32", i32, 32, +defm GRX32 : SystemZRegClass<"GRX32", [i32], 32, (add (sequence "R%uL", 0, 5), (sequence "R%uH", 0, 5), R15L, R15H, R14L, R14H, R13L, R13H, @@ -104,18 +109,17 @@ defm GRX32 : SystemZRegClass<"GRX32", i32, 32, // The architecture doesn't really have any i128 support, so model the // register pairs as untyped instead. -defm GR128 : SystemZRegClass<"GR128", untyped, 128, (add R0Q, R2Q, R4Q, - R12Q, R10Q, R8Q, R6Q, - R14Q)>; +defm GR128 : SystemZRegClass<"GR128", [untyped], 128, + (add R0Q, R2Q, R4Q, R12Q, R10Q, R8Q, R6Q, R14Q)>; // Base and index registers. Everything except R0, which in an address // context evaluates as 0. -defm ADDR32 : SystemZRegClass<"ADDR32", i32, 32, (sub GR32Bit, R0L)>; -defm ADDR64 : SystemZRegClass<"ADDR64", i64, 64, (sub GR64Bit, R0D)>; +defm ADDR32 : SystemZRegClass<"ADDR32", [i32], 32, (sub GR32Bit, R0L)>; +defm ADDR64 : SystemZRegClass<"ADDR64", [i64], 64, (sub GR64Bit, R0D)>; // Not used directly, but needs to exist for ADDR32 and ADDR64 subregs // of a GR128. -defm ADDR128 : SystemZRegClass<"ADDR128", untyped, 128, (sub GR128Bit, R0Q)>; +defm ADDR128 : SystemZRegClass<"ADDR128", [untyped], 128, (sub GR128Bit, R0Q)>; //===----------------------------------------------------------------------===// // Floating-point registers @@ -144,14 +148,34 @@ def F11Dwarf : DwarfMapping<29>; def F13Dwarf : DwarfMapping<30>; def F15Dwarf : DwarfMapping<31>; -// Lower 32 bits of one of the 16 64-bit floating-point registers +def F16Dwarf : DwarfMapping<68>; +def F18Dwarf : DwarfMapping<69>; +def F20Dwarf : DwarfMapping<70>; +def F22Dwarf : DwarfMapping<71>; + +def F17Dwarf : DwarfMapping<72>; +def F19Dwarf : DwarfMapping<73>; +def F21Dwarf : DwarfMapping<74>; +def F23Dwarf : DwarfMapping<75>; + +def F24Dwarf : DwarfMapping<76>; +def F26Dwarf : DwarfMapping<77>; +def F28Dwarf : DwarfMapping<78>; +def F30Dwarf : DwarfMapping<79>; + +def F25Dwarf : DwarfMapping<80>; +def F27Dwarf : DwarfMapping<81>; +def F29Dwarf : DwarfMapping<82>; +def F31Dwarf : DwarfMapping<83>; + +// Upper 32 bits of one of the floating-point registers class FPR32<bits<16> num, string n> : SystemZReg<n> { let HWEncoding = num; } -// One of the 16 64-bit floating-point registers -class FPR64<bits<16> num, string n, FPR32 low> - : SystemZRegWithSubregs<n, [low]> { +// One of the floating-point registers. +class FPR64<bits<16> num, string n, FPR32 high> + : SystemZRegWithSubregs<n, [high]> { let HWEncoding = num; let SubRegIndices = [subreg_r32]; } @@ -163,12 +187,17 @@ class FPR128<bits<16> num, string n, FPR64 low, FPR64 high> let SubRegIndices = [subreg_l64, subreg_h64]; } -// Floating-point registers +// Floating-point registers. Registers 16-31 require the vector facility. foreach I = 0-15 in { def F#I#S : FPR32<I, "f"#I>; def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>, DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>; } +foreach I = 16-31 in { + def F#I#S : FPR32<I, "v"#I>; + def F#I#D : FPR64<I, "v"#I, !cast<FPR32>("F"#I#"S")>, + DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>; +} foreach I = [0, 1, 4, 5, 8, 9, 12, 13] in { def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"), @@ -177,10 +206,74 @@ foreach I = [0, 1, 4, 5, 8, 9, 12, 13] in { // There's no store-multiple instruction for FPRs, so we're not fussy // about the order in which call-saved registers are allocated. -defm FP32 : SystemZRegClass<"FP32", f32, 32, (sequence "F%uS", 0, 15)>; -defm FP64 : SystemZRegClass<"FP64", f64, 64, (sequence "F%uD", 0, 15)>; -defm FP128 : SystemZRegClass<"FP128", f128, 128, (add F0Q, F1Q, F4Q, F5Q, - F8Q, F9Q, F12Q, F13Q)>; +defm FP32 : SystemZRegClass<"FP32", [f32], 32, (sequence "F%uS", 0, 15)>; +defm FP64 : SystemZRegClass<"FP64", [f64], 64, (sequence "F%uD", 0, 15)>; +defm FP128 : SystemZRegClass<"FP128", [f128], 128, + (add F0Q, F1Q, F4Q, F5Q, F8Q, F9Q, F12Q, F13Q)>; + +//===----------------------------------------------------------------------===// +// Vector registers +//===----------------------------------------------------------------------===// + +// A full 128-bit vector register, with an FPR64 as its high part. +class VR128<bits<16> num, string n, FPR64 high> + : SystemZRegWithSubregs<n, [high]> { + let HWEncoding = num; + let SubRegIndices = [subreg_r64]; +} + +// Full vector registers. +foreach I = 0-31 in { + def V#I : VR128<I, "v"#I, !cast<FPR64>("F"#I#"D")>, + DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>; +} + +// Class used to store 32-bit values in the first element of a vector +// register. f32 scalars are used for the WLEDB and WLDEB instructions. +defm VR32 : SystemZRegClass<"VR32", [f32, v4i8, v2i16], 32, + (add (sequence "F%uS", 0, 7), + (sequence "F%uS", 16, 31), + (sequence "F%uS", 8, 15))>; + +// Class used to store 64-bit values in the upper half of a vector register. +// The vector facility also includes scalar f64 instructions that operate +// on the full vector register set. +defm VR64 : SystemZRegClass<"VR64", [f64, v8i8, v4i16, v2i32, v2f32], 64, + (add (sequence "F%uD", 0, 7), + (sequence "F%uD", 16, 31), + (sequence "F%uD", 8, 15))>; + +// The subset of vector registers that can be used for floating-point +// operations too. +defm VF128 : SystemZRegClass<"VF128", + [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128, + (sequence "V%u", 0, 15)>; + +// All vector registers. +defm VR128 : SystemZRegClass<"VR128", + [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128, + (add (sequence "V%u", 0, 7), + (sequence "V%u", 16, 31), + (sequence "V%u", 8, 15))>; + +// Attaches a ValueType to a register operand, to make the instruction +// definitions easier. +class TypedReg<ValueType vtin, RegisterOperand opin> { + ValueType vt = vtin; + RegisterOperand op = opin; +} + +def v32eb : TypedReg<f32, VR32>; +def v64g : TypedReg<i64, VR64>; +def v64db : TypedReg<f64, VR64>; +def v128b : TypedReg<v16i8, VR128>; +def v128h : TypedReg<v8i16, VR128>; +def v128f : TypedReg<v4i32, VR128>; +def v128g : TypedReg<v2i64, VR128>; +def v128q : TypedReg<v16i8, VR128>; +def v128eb : TypedReg<v4f32, VR128>; +def v128db : TypedReg<v2f64, VR128>; +def v128any : TypedReg<untyped, VR128>; //===----------------------------------------------------------------------===// // Other registers diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp index de725ae6123..05aede3deb4 100644 --- a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp +++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -41,6 +41,7 @@ SystemZSubtarget::SystemZSubtarget(const std::string &TT, HasPopulationCount(false), HasFastSerialization(false), HasInterlockedAccess1(false), HasMiscellaneousExtensions(false), HasTransactionalExecution(false), HasProcessorAssist(false), + HasVector(false), TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), TSInfo(*TM.getDataLayout()), FrameLowering() {} diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.h b/llvm/lib/Target/SystemZ/SystemZSubtarget.h index c99e552abb1..9a1f593f526 100644 --- a/llvm/lib/Target/SystemZ/SystemZSubtarget.h +++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.h @@ -44,6 +44,7 @@ protected: bool HasMiscellaneousExtensions; bool HasTransactionalExecution; bool HasProcessorAssist; + bool HasVector; private: Triple TargetTriple; @@ -110,6 +111,9 @@ public: // Return true if the target has the processor-assist facility. bool hasProcessorAssist() const { return HasProcessorAssist; } + // Return true if the target has the vector facility. + bool hasVector() const { return HasVector; } + // Return true if GV can be accessed using LARL for reloc model RM // and code model CM. bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM, diff --git a/llvm/test/MC/Disassembler/SystemZ/insns-z13-bad.txt b/llvm/test/MC/Disassembler/SystemZ/insns-z13-bad.txt new file mode 100644 index 00000000000..e1cf033f4b7 --- /dev/null +++ b/llvm/test/MC/Disassembler/SystemZ/insns-z13-bad.txt @@ -0,0 +1,39 @@ +# Test z13 instructions that don't have PC-relative operands. +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=z13 2>&1 \ +# RUN: | FileCheck %s + +# This would be "vlef %v0, 0, 4", but element 4 is invalid. +# +#CHECK: warning: invalid instruction encoding +#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0x40 0x03 +0xe7 0x00 0x00 0x00 0x40 0x03 + +# ...and again with element 15 +# +#CHECK: warning: invalid instruction encoding +#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0xf0 0x03 +0xe7 0x00 0x00 0x00 0xf0 0x03 + +# This would be "vleg %v0, 0, 2", but element 2 is invalid. +# +#CHECK: warning: invalid instruction encoding +#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0x20 0x02 +0xe7 0x00 0x00 0x00 0x20 0x02 + +# ...and again with element 15 +# +#CHECK: warning: invalid instruction encoding +#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0xf0 0x02 +0xe7 0x00 0x00 0x00 0xf0 0x02 + +# This would be "vleh %v0, 0, 8", but element 8 is invalid. +# +#CHECK: warning: invalid instruction encoding +#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0x80 0x01 +0xe7 0x00 0x00 0x00 0x80 0x01 + +# ...and again with element 15 +# +#CHECK: warning: invalid instruction encoding +#CHECK-NEXT: 0xe7 0x00 0x00 0x00 0xf0 0x01 +0xe7 0x00 0x00 0x00 0xf0 0x01 diff --git a/llvm/test/MC/Disassembler/SystemZ/insns-z13.txt b/llvm/test/MC/Disassembler/SystemZ/insns-z13.txt new file mode 100644 index 00000000000..71e77664abb --- /dev/null +++ b/llvm/test/MC/Disassembler/SystemZ/insns-z13.txt @@ -0,0 +1,3315 @@ +# Test z13 instructions that don't have PC-relative operands. +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=z13 \ +# RUN: | FileCheck %s + +#CHECK: lcbb %r0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x27 + +#CHECK: lcbb %r1, 2475(%r7,%r8), 12 +0xe7 0x17 0x89 0xab 0xc0 0x27 + +#CHECK: lcbb %r15, 4095(%r15,%r15), 15 +0xe7 0xff 0xff 0xff 0xf0 0x27 + +#CHECK: vab %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xf3 + +#CHECK: vab %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xf3 + +#CHECK: vab %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xf3 + +#CHECK: vaccb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xf1 + +#CHECK: vaccb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xf1 + +#CHECK: vaccb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xf1 + +#CHECK: vacccq %v0, %v0, %v0, %v0 +0xe7 0x00 0x04 0x00 0x00 0xb9 + +#CHECK: vacccq %v3, %v20, %v5, %v22 +0xe7 0x34 0x54 0x00 0x65 0xb9 + +#CHECK: vacccq %v31, %v31, %v31, %v31 +0xe7 0xff 0xf4 0x00 0xff 0xb9 + +#CHECK: vaccf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xf1 + +#CHECK: vaccf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xf1 + +#CHECK: vaccf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xf1 + +#CHECK: vaccg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xf1 + +#CHECK: vaccg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xf1 + +#CHECK: vaccg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xf1 + +#CHECK: vacch %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xf1 + +#CHECK: vacch %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xf1 + +#CHECK: vacch %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xf1 + +#CHECK: vaccq %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x40 0xf1 + +#CHECK: vaccq %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x4a 0xf1 + +#CHECK: vaccq %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x4e 0xf1 + +#CHECK: vacq %v0, %v0, %v0, %v0 +0xe7 0x00 0x04 0x00 0x00 0xbb + +#CHECK: vacq %v3, %v20, %v5, %v22 +0xe7 0x34 0x54 0x00 0x65 0xbb + +#CHECK: vacq %v31, %v31, %v31, %v31 +0xe7 0xff 0xf4 0x00 0xff 0xbb + +#CHECK: vaf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xf3 + +#CHECK: vaf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xf3 + +#CHECK: vaf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xf3 + +#CHECK: vag %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xf3 + +#CHECK: vag %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xf3 + +#CHECK: vag %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xf3 + +#CHECK: vah %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xf3 + +#CHECK: vah %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xf3 + +#CHECK: vah %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xf3 + +#CHECK: vaq %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x40 0xf3 + +#CHECK: vaq %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x4a 0xf3 + +#CHECK: vaq %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x4e 0xf3 + +#CHECK: vavgb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xf2 + +#CHECK: vavgb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xf2 + +#CHECK: vavgb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xf2 + +#CHECK: vavgf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xf2 + +#CHECK: vavgf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xf2 + +#CHECK: vavgf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xf2 + +#CHECK: vavgg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xf2 + +#CHECK: vavgg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xf2 + +#CHECK: vavgg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xf2 + +#CHECK: vavgh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xf2 + +#CHECK: vavgh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xf2 + +#CHECK: vavgh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xf2 + +#CHECK: vavglb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xf0 + +#CHECK: vavglb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xf0 + +#CHECK: vavglb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xf0 + +#CHECK: vavglf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xf0 + +#CHECK: vavglf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xf0 + +#CHECK: vavglf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xf0 + +#CHECK: vavglg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xf0 + +#CHECK: vavglg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xf0 + +#CHECK: vavglg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xf0 + +#CHECK: vavglh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xf0 + +#CHECK: vavglh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xf0 + +#CHECK: vavglh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xf0 + +#CHECK: vcdgb %v0, %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x30 0xc3 + +#CHECK: vcdgb %v19, %v14, 4, 10 +0xe7 0x3e 0x00 0xa4 0x38 0xc3 + +#CHECK: vcdgb %v31, %v31, 7, 15 +0xe7 0xff 0x00 0xf7 0x3c 0xc3 + +#CHECK: vcdlgb %v0, %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x30 0xc1 + +#CHECK: vcdlgb %v19, %v14, 4, 10 +0xe7 0x3e 0x00 0xa4 0x38 0xc1 + +#CHECK: vcdlgb %v31, %v31, 7, 15 +0xe7 0xff 0x00 0xf7 0x3c 0xc1 + +#CHECK: vceqb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xf8 + +#CHECK: vceqb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xf8 + +#CHECK: vceqbs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x04 0xf8 + +#CHECK: vceqb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xf8 + +#CHECK: vceqf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xf8 + +#CHECK: vceqf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xf8 + +#CHECK: vceqfs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x24 0xf8 + +#CHECK: vceqf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xf8 + +#CHECK: vceqg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xf8 + +#CHECK: vceqg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xf8 + +#CHECK: vceqgs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x34 0xf8 + +#CHECK: vceqg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xf8 + +#CHECK: vceqh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xf8 + +#CHECK: vceqh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xf8 + +#CHECK: vceqhs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x14 0xf8 + +#CHECK: vceqh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xf8 + +#CHECK: vcgdb %v0, %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x30 0xc2 + +#CHECK: vcgdb %v19, %v14, 4, 10 +0xe7 0x3e 0x00 0xa4 0x38 0xc2 + +#CHECK: vcgdb %v31, %v31, 7, 15 +0xe7 0xff 0x00 0xf7 0x3c 0xc2 + +#CHECK: vchb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xfb + +#CHECK: vchb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xfb + +#CHECK: vchbs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x04 0xfb + +#CHECK: vchb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xfb + +#CHECK: vchf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xfb + +#CHECK: vchf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xfb + +#CHECK: vchfs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x24 0xfb + +#CHECK: vchf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xfb + +#CHECK: vchg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xfb + +#CHECK: vchg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xfb + +#CHECK: vchgs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x34 0xfb + +#CHECK: vchg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xfb + +#CHECK: vchh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xfb + +#CHECK: vchh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xfb + +#CHECK: vchhs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x14 0xfb + +#CHECK: vchh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xfb + +#CHECK: vchlb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xf9 + +#CHECK: vchlb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xf9 + +#CHECK: vchlbs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x04 0xf9 + +#CHECK: vchlb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xf9 + +#CHECK: vchlf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xf9 + +#CHECK: vchlf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xf9 + +#CHECK: vchlfs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x24 0xf9 + +#CHECK: vchlf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xf9 + +#CHECK: vchlg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xf9 + +#CHECK: vchlg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xf9 + +#CHECK: vchlgs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x34 0xf9 + +#CHECK: vchlg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xf9 + +#CHECK: vchlh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xf9 + +#CHECK: vchlh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xf9 + +#CHECK: vchlhs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x14 0xf9 + +#CHECK: vchlh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xf9 + +#CHECK: vcksm %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x66 + +#CHECK: vcksm %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x66 + +#CHECK: vcksm %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x66 + +#CHECK: vclgdb %v0, %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x30 0xc0 + +#CHECK: vclgdb %v19, %v14, 4, 10 +0xe7 0x3e 0x00 0xa4 0x38 0xc0 + +#CHECK: vclgdb %v31, %v31, 7, 15 +0xe7 0xff 0x00 0xf7 0x3c 0xc0 + +#CHECK: vclzb %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x53 + +#CHECK: vclzb %v19, %v14 +0xe7 0x3e 0x00 0x00 0x08 0x53 + +#CHECK: vclzb %v31, %v31 +0xe7 0xff 0x00 0x00 0x0c 0x53 + +#CHECK: vclzf %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x53 + +#CHECK: vclzf %v19, %v14 +0xe7 0x3e 0x00 0x00 0x28 0x53 + +#CHECK: vclzf %v31, %v31 +0xe7 0xff 0x00 0x00 0x2c 0x53 + +#CHECK: vclzg %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0x53 + +#CHECK: vclzg %v19, %v14 +0xe7 0x3e 0x00 0x00 0x38 0x53 + +#CHECK: vclzg %v31, %v31 +0xe7 0xff 0x00 0x00 0x3c 0x53 + +#CHECK: vclzh %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x53 + +#CHECK: vclzh %v19, %v14 +0xe7 0x3e 0x00 0x00 0x18 0x53 + +#CHECK: vclzh %v31, %v31 +0xe7 0xff 0x00 0x00 0x1c 0x53 + +#CHECK: vctzb %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x52 + +#CHECK: vctzb %v19, %v14 +0xe7 0x3e 0x00 0x00 0x08 0x52 + +#CHECK: vctzb %v31, %v31 +0xe7 0xff 0x00 0x00 0x0c 0x52 + +#CHECK: vctzf %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x52 + +#CHECK: vctzf %v19, %v14 +0xe7 0x3e 0x00 0x00 0x28 0x52 + +#CHECK: vctzf %v31, %v31 +0xe7 0xff 0x00 0x00 0x2c 0x52 + +#CHECK: vctzg %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0x52 + +#CHECK: vctzg %v19, %v14 +0xe7 0x3e 0x00 0x00 0x38 0x52 + +#CHECK: vctzg %v31, %v31 +0xe7 0xff 0x00 0x00 0x3c 0x52 + +#CHECK: vctzh %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x52 + +#CHECK: vctzh %v19, %v14 +0xe7 0x3e 0x00 0x00 0x18 0x52 + +#CHECK: vctzh %v31, %v31 +0xe7 0xff 0x00 0x00 0x1c 0x52 + +#CHECK: vecb %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xdb + +#CHECK: vecb %v19, %v14 +0xe7 0x3e 0x00 0x00 0x08 0xdb + +#CHECK: vecb %v31, %v31 +0xe7 0xff 0x00 0x00 0x0c 0xdb + +#CHECK: vecf %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xdb + +#CHECK: vecf %v19, %v14 +0xe7 0x3e 0x00 0x00 0x28 0xdb + +#CHECK: vecf %v31, %v31 +0xe7 0xff 0x00 0x00 0x2c 0xdb + +#CHECK: vecg %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xdb + +#CHECK: vecg %v19, %v14 +0xe7 0x3e 0x00 0x00 0x38 0xdb + +#CHECK: vecg %v31, %v31 +0xe7 0xff 0x00 0x00 0x3c 0xdb + +#CHECK: vech %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xdb + +#CHECK: vech %v19, %v14 +0xe7 0x3e 0x00 0x00 0x18 0xdb + +#CHECK: vech %v31, %v31 +0xe7 0xff 0x00 0x00 0x1c 0xdb + +#CHECK: veclb %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xd9 + +#CHECK: veclb %v19, %v14 +0xe7 0x3e 0x00 0x00 0x08 0xd9 + +#CHECK: veclb %v31, %v31 +0xe7 0xff 0x00 0x00 0x0c 0xd9 + +#CHECK: veclf %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xd9 + +#CHECK: veclf %v19, %v14 +0xe7 0x3e 0x00 0x00 0x28 0xd9 + +#CHECK: veclf %v31, %v31 +0xe7 0xff 0x00 0x00 0x2c 0xd9 + +#CHECK: veclg %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xd9 + +#CHECK: veclg %v19, %v14 +0xe7 0x3e 0x00 0x00 0x38 0xd9 + +#CHECK: veclg %v31, %v31 +0xe7 0xff 0x00 0x00 0x3c 0xd9 + +#CHECK: veclh %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xd9 + +#CHECK: veclh %v19, %v14 +0xe7 0x3e 0x00 0x00 0x18 0xd9 + +#CHECK: veclh %v31, %v31 +0xe7 0xff 0x00 0x00 0x1c 0xd9 + +#CHECK: verimb %v0, %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x72 + +#CHECK: verimb %v3, %v20, %v5, 103 +0xe7 0x34 0x50 0x67 0x04 0x72 + +#CHECK: verimb %v31, %v31, %v31, 255 +0xe7 0xff 0xf0 0xff 0x0e 0x72 + +#CHECK: verimf %v0, %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x20 0x72 + +#CHECK: verimf %v3, %v20, %v5, 103 +0xe7 0x34 0x50 0x67 0x24 0x72 + +#CHECK: verimf %v31, %v31, %v31, 255 +0xe7 0xff 0xf0 0xff 0x2e 0x72 + +#CHECK: verimg %v0, %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x30 0x72 + +#CHECK: verimg %v3, %v20, %v5, 103 +0xe7 0x34 0x50 0x67 0x34 0x72 + +#CHECK: verimg %v31, %v31, %v31, 255 +0xe7 0xff 0xf0 0xff 0x3e 0x72 + +#CHECK: verimh %v0, %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x10 0x72 + +#CHECK: verimh %v3, %v20, %v5, 103 +0xe7 0x34 0x50 0x67 0x14 0x72 + +#CHECK: verimh %v31, %v31, %v31, 255 +0xe7 0xff 0xf0 0xff 0x1e 0x72 + +#CHECK: verllvb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x73 + +#CHECK: verllvb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x73 + +#CHECK: verllvb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x73 + +#CHECK: verllvf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x73 + +#CHECK: verllvf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0x73 + +#CHECK: verllvf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0x73 + +#CHECK: verllvg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0x73 + +#CHECK: verllvg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0x73 + +#CHECK: verllvg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0x73 + +#CHECK: verllvh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x73 + +#CHECK: verllvh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0x73 + +#CHECK: verllvh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0x73 + +#CHECK: verllb %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x33 + +#CHECK: verllb %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x04 0x33 + +#CHECK: verllb %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x0c 0x33 + +#CHECK: verllf %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x20 0x33 + +#CHECK: verllf %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x24 0x33 + +#CHECK: verllf %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x2c 0x33 + +#CHECK: verllg %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x30 0x33 + +#CHECK: verllg %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x34 0x33 + +#CHECK: verllg %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x3c 0x33 + +#CHECK: verllh %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x10 0x33 + +#CHECK: verllh %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x14 0x33 + +#CHECK: verllh %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x1c 0x33 + +#CHECK: veslvb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x70 + +#CHECK: veslvb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x70 + +#CHECK: veslvb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x70 + +#CHECK: veslvf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x70 + +#CHECK: veslvf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0x70 + +#CHECK: veslvf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0x70 + +#CHECK: veslvg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0x70 + +#CHECK: veslvg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0x70 + +#CHECK: veslvg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0x70 + +#CHECK: veslvh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x70 + +#CHECK: veslvh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0x70 + +#CHECK: veslvh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0x70 + +#CHECK: veslb %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x30 + +#CHECK: veslb %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x04 0x30 + +#CHECK: veslb %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x0c 0x30 + +#CHECK: veslf %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x20 0x30 + +#CHECK: veslf %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x24 0x30 + +#CHECK: veslf %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x2c 0x30 + +#CHECK: veslg %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x30 0x30 + +#CHECK: veslg %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x34 0x30 + +#CHECK: veslg %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x3c 0x30 + +#CHECK: veslh %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x10 0x30 + +#CHECK: veslh %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x14 0x30 + +#CHECK: veslh %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x1c 0x30 + +#CHECK: vesravb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x7a + +#CHECK: vesravb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x7a + +#CHECK: vesravb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x7a + +#CHECK: vesravf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x7a + +#CHECK: vesravf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0x7a + +#CHECK: vesravf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0x7a + +#CHECK: vesravg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0x7a + +#CHECK: vesravg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0x7a + +#CHECK: vesravg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0x7a + +#CHECK: vesravh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x7a + +#CHECK: vesravh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0x7a + +#CHECK: vesravh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0x7a + +#CHECK: vesrab %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x3a + +#CHECK: vesrab %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x04 0x3a + +#CHECK: vesrab %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x0c 0x3a + +#CHECK: vesraf %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x20 0x3a + +#CHECK: vesraf %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x24 0x3a + +#CHECK: vesraf %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x2c 0x3a + +#CHECK: vesrag %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x30 0x3a + +#CHECK: vesrag %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x34 0x3a + +#CHECK: vesrag %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x3c 0x3a + +#CHECK: vesrah %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x10 0x3a + +#CHECK: vesrah %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x14 0x3a + +#CHECK: vesrah %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x1c 0x3a + +#CHECK: vesrlvb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x78 + +#CHECK: vesrlvb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x78 + +#CHECK: vesrlvb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x78 + +#CHECK: vesrlvf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x78 + +#CHECK: vesrlvf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0x78 + +#CHECK: vesrlvf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0x78 + +#CHECK: vesrlvg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0x78 + +#CHECK: vesrlvg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0x78 + +#CHECK: vesrlvg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0x78 + +#CHECK: vesrlvh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x78 + +#CHECK: vesrlvh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0x78 + +#CHECK: vesrlvh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0x78 + +#CHECK: vesrlb %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x38 + +#CHECK: vesrlb %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x04 0x38 + +#CHECK: vesrlb %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x0c 0x38 + +#CHECK: vesrlf %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x20 0x38 + +#CHECK: vesrlf %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x24 0x38 + +#CHECK: vesrlf %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x2c 0x38 + +#CHECK: vesrlg %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x30 0x38 + +#CHECK: vesrlg %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x34 0x38 + +#CHECK: vesrlg %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x3c 0x38 + +#CHECK: vesrlh %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x10 0x38 + +#CHECK: vesrlh %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x14 0x38 + +#CHECK: vesrlh %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x1c 0x38 + +#CHECK: vfadb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xe3 + +#CHECK: vfadb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xe3 + +#CHECK: vfadb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xe3 + +#CHECK: vfaeb %v0, %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x82 + +#CHECK: vfaeb %v0, %v0, %v0, 12 +0xe7 0x00 0x00 0xc0 0x00 0x82 + +#CHECK: vfaeb %v18, %v3, %v20, 0 +0xe7 0x23 0x40 0x00 0x0a 0x82 + +#CHECK: vfaeb %v31, %v31, %v31, 4 +0xe7 0xff 0xf0 0x40 0x0e 0x82 + +#CHECK: vfaebs %v31, %v31, %v31, 8 +0xe7 0xff 0xf0 0x90 0x0e 0x82 + +#CHECK: vfaezb %v31, %v31, %v31, 4 +0xe7 0xff 0xf0 0x60 0x0e 0x82 + +#CHECK: vfaezbs %v31, %v31, %v31, 8 +0xe7 0xff 0xf0 0xb0 0x0e 0x82 + +#CHECK: vfaef %v0, %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x20 0x82 + +#CHECK: vfaef %v0, %v0, %v0, 12 +0xe7 0x00 0x00 0xc0 0x20 0x82 + +#CHECK: vfaef %v18, %v3, %v20, 0 +0xe7 0x23 0x40 0x00 0x2a 0x82 + +#CHECK: vfaef %v31, %v31, %v31, 4 +0xe7 0xff 0xf0 0x40 0x2e 0x82 + +#CHECK: vfaefs %v31, %v31, %v31, 8 +0xe7 0xff 0xf0 0x90 0x2e 0x82 + +#CHECK: vfaezf %v31, %v31, %v31, 4 +0xe7 0xff 0xf0 0x60 0x2e 0x82 + +#CHECK: vfaezfs %v31, %v31, %v31, 8 +0xe7 0xff 0xf0 0xb0 0x2e 0x82 + +#CHECK: vfaeh %v0, %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x10 0x82 + +#CHECK: vfaeh %v0, %v0, %v0, 12 +0xe7 0x00 0x00 0xc0 0x10 0x82 + +#CHECK: vfaeh %v18, %v3, %v20, 0 +0xe7 0x23 0x40 0x00 0x1a 0x82 + +#CHECK: vfaeh %v31, %v31, %v31, 4 +0xe7 0xff 0xf0 0x40 0x1e 0x82 + +#CHECK: vfaehs %v31, %v31, %v31, 8 +0xe7 0xff 0xf0 0x90 0x1e 0x82 + +#CHECK: vfaezh %v31, %v31, %v31, 4 +0xe7 0xff 0xf0 0x60 0x1e 0x82 + +#CHECK: vfaezhs %v31, %v31, %v31, 8 +0xe7 0xff 0xf0 0xb0 0x1e 0x82 + +#CHECK: vfcedb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xe8 + +#CHECK: vfcedb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xe8 + +#CHECK: vfcedb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xe8 + +#CHECK: vfcedbs %v0, %v0, %v0 +0xe7 0x00 0x00 0x10 0x30 0xe8 + +#CHECK: vfcedbs %v18, %v3, %v20 +0xe7 0x23 0x40 0x10 0x3a 0xe8 + +#CHECK: vfcedbs %v31, %v31, %v31 +0xe7 0xff 0xf0 0x10 0x3e 0xe8 + +#CHECK: vfchdb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xeb + +#CHECK: vfchdb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xeb + +#CHECK: vfchdb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xeb + +#CHECK: vfchdbs %v0, %v0, %v0 +0xe7 0x00 0x00 0x10 0x30 0xeb + +#CHECK: vfchdbs %v18, %v3, %v20 +0xe7 0x23 0x40 0x10 0x3a 0xeb + +#CHECK: vfchdbs %v31, %v31, %v31 +0xe7 0xff 0xf0 0x10 0x3e 0xeb + +#CHECK: vfchedb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xea + +#CHECK: vfchedb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xea + +#CHECK: vfchedb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xea + +#CHECK: vfchedbs %v0, %v0, %v0 +0xe7 0x00 0x00 0x10 0x30 0xea + +#CHECK: vfchedbs %v18, %v3, %v20 +0xe7 0x23 0x40 0x10 0x3a 0xea + +#CHECK: vfchedbs %v31, %v31, %v31 +0xe7 0xff 0xf0 0x10 0x3e 0xea + +#CHECK: vfddb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xe5 + +#CHECK: vfddb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xe5 + +#CHECK: vfddb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xe5 + +#CHECK: vfeeb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x80 + +#CHECK: vfeeb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x80 + +#CHECK: vfeebs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x04 0x80 + +#CHECK: vfeezb %v18, %v3, %v20 +0xe7 0x23 0x40 0x20 0x0a 0x80 + +#CHECK: vfeezbs %v7, %v24, %v9 +0xe7 0x78 0x90 0x30 0x04 0x80 + +#CHECK: vfeeb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x80 + +#CHECK: vfeef %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x80 + +#CHECK: vfeef %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0x80 + +#CHECK: vfeefs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x24 0x80 + +#CHECK: vfeezf %v18, %v3, %v20 +0xe7 0x23 0x40 0x20 0x2a 0x80 + +#CHECK: vfeezfs %v7, %v24, %v9 +0xe7 0x78 0x90 0x30 0x24 0x80 + +#CHECK: vfeef %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0x80 + +#CHECK: vfeeh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x80 + +#CHECK: vfeeh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0x80 + +#CHECK: vfeehs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x14 0x80 + +#CHECK: vfeezh %v18, %v3, %v20 +0xe7 0x23 0x40 0x20 0x1a 0x80 + +#CHECK: vfeezhs %v7, %v24, %v9 +0xe7 0x78 0x90 0x30 0x14 0x80 + +#CHECK: vfeeh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0x80 + +#CHECK: vfeneb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x81 + +#CHECK: vfeneb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x81 + +#CHECK: vfenebs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x04 0x81 + +#CHECK: vfenezb %v18, %v3, %v20 +0xe7 0x23 0x40 0x20 0x0a 0x81 + +#CHECK: vfenezbs %v7, %v24, %v9 +0xe7 0x78 0x90 0x30 0x04 0x81 + +#CHECK: vfeneb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x81 + +#CHECK: vfenef %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x81 + +#CHECK: vfenef %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0x81 + +#CHECK: vfenefs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x24 0x81 + +#CHECK: vfenezf %v18, %v3, %v20 +0xe7 0x23 0x40 0x20 0x2a 0x81 + +#CHECK: vfenezfs %v7, %v24, %v9 +0xe7 0x78 0x90 0x30 0x24 0x81 + +#CHECK: vfenef %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0x81 + +#CHECK: vfeneh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x81 + +#CHECK: vfeneh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0x81 + +#CHECK: vfenehs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x14 0x81 + +#CHECK: vfenezh %v18, %v3, %v20 +0xe7 0x23 0x40 0x20 0x1a 0x81 + +#CHECK: vfenezhs %v7, %v24, %v9 +0xe7 0x78 0x90 0x30 0x14 0x81 + +#CHECK: vfeneh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0x81 + +#CHECK: vfidb %v0, %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x30 0xc7 + +#CHECK: vfidb %v19, %v14, 4, 10 +0xe7 0x3e 0x00 0xa4 0x38 0xc7 + +#CHECK: vfidb %v31, %v31, 7, 15 +0xe7 0xff 0x00 0xf7 0x3c 0xc7 + +#CHECK: vistrb %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x5c + +#CHECK: vistrb %v18, %v3 +0xe7 0x23 0x00 0x00 0x08 0x5c + +#CHECK: vistrbs %v7, %v24 +0xe7 0x78 0x00 0x10 0x04 0x5c + +#CHECK: vistrb %v31, %v31 +0xe7 0xff 0x00 0x00 0x0c 0x5c + +#CHECK: vistrf %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x5c + +#CHECK: vistrf %v18, %v3 +0xe7 0x23 0x00 0x00 0x28 0x5c + +#CHECK: vistrfs %v7, %v24 +0xe7 0x78 0x00 0x10 0x24 0x5c + +#CHECK: vistrf %v31, %v31 +0xe7 0xff 0x00 0x00 0x2c 0x5c + +#CHECK: vistrh %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x5c + +#CHECK: vistrh %v18, %v3 +0xe7 0x23 0x00 0x00 0x18 0x5c + +#CHECK: vistrhs %v7, %v24 +0xe7 0x78 0x00 0x10 0x14 0x5c + +#CHECK: vistrh %v31, %v31 +0xe7 0xff 0x00 0x00 0x1c 0x5c + +#CHECK: vfmadb %v0, %v0, %v0, %v0 +0xe7 0x00 0x03 0x00 0x00 0x8f + +#CHECK: vfmadb %v3, %v20, %v5, %v22 +0xe7 0x34 0x53 0x00 0x65 0x8f + +#CHECK: vfmadb %v31, %v31, %v31, %v31 +0xe7 0xff 0xf3 0x00 0xff 0x8f + +#CHECK: vfmdb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xe7 + +#CHECK: vfmdb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xe7 + +#CHECK: vfmdb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xe7 + +#CHECK: vfmsdb %v0, %v0, %v0, %v0 +0xe7 0x00 0x03 0x00 0x00 0x8e + +#CHECK: vfmsdb %v3, %v20, %v5, %v22 +0xe7 0x34 0x53 0x00 0x65 0x8e + +#CHECK: vfmsdb %v31, %v31, %v31, %v31 +0xe7 0xff 0xf3 0x00 0xff 0x8e + +#CHECK: vfsdb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xe2 + +#CHECK: vfsdb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xe2 + +#CHECK: vfsdb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xe2 + +#CHECK: vzero %v0 +0xe7 0x00 0x00 0x00 0x00 0x44 + +#CHECK: vgbm %v0, 1 +0xe7 0x00 0x00 0x01 0x00 0x44 + +#CHECK: vgbm %v0, 65534 +0xe7 0x00 0xff 0xfe 0x00 0x44 + +#CHECK: vone %v0 +0xe7 0x00 0xff 0xff 0x00 0x44 + +#CHECK: vgbm %v17, 4660 +0xe7 0x10 0x12 0x34 0x08 0x44 + +#CHECK: vone %v31 +0xe7 0xf0 0xff 0xff 0x08 0x44 + +#CHECK: vgef %v0, 0(%v0), 0 +0xe7 0x00 0x00 0x00 0x00 0x13 + +#CHECK: vgef %v10, 1000(%v19,%r7), 2 +0xe7 0xa3 0x73 0xe8 0x24 0x13 + +#CHECK: vgef %v31, 4095(%v31,%r15), 3 +0xe7 0xff 0xff 0xff 0x3c 0x13 + +#CHECK: vgeg %v0, 0(%v0), 0 +0xe7 0x00 0x00 0x00 0x00 0x12 + +#CHECK: vgeg %v10, 1000(%v19,%r7), 1 +0xe7 0xa3 0x73 0xe8 0x14 0x12 + +#CHECK: vgeg %v31, 4095(%v31,%r15), 1 +0xe7 0xff 0xff 0xff 0x1c 0x12 + +#CHECK: vgfmab %v0, %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xbc + +#CHECK: vgfmab %v3, %v20, %v5, %v22 +0xe7 0x34 0x50 0x00 0x65 0xbc + +#CHECK: vgfmab %v31, %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0xff 0xbc + +#CHECK: vgfmaf %v0, %v0, %v0, %v0 +0xe7 0x00 0x02 0x00 0x00 0xbc + +#CHECK: vgfmaf %v3, %v20, %v5, %v22 +0xe7 0x34 0x52 0x00 0x65 0xbc + +#CHECK: vgfmaf %v31, %v31, %v31, %v31 +0xe7 0xff 0xf2 0x00 0xff 0xbc + +#CHECK: vgfmag %v0, %v0, %v0, %v0 +0xe7 0x00 0x03 0x00 0x00 0xbc + +#CHECK: vgfmag %v3, %v20, %v5, %v22 +0xe7 0x34 0x53 0x00 0x65 0xbc + +#CHECK: vgfmag %v31, %v31, %v31, %v31 +0xe7 0xff 0xf3 0x00 0xff 0xbc + +#CHECK: vgfmah %v0, %v0, %v0, %v0 +0xe7 0x00 0x01 0x00 0x00 0xbc + +#CHECK: vgfmah %v3, %v20, %v5, %v22 +0xe7 0x34 0x51 0x00 0x65 0xbc + +#CHECK: vgfmah %v31, %v31, %v31, %v31 +0xe7 0xff 0xf1 0x00 0xff 0xbc + +#CHECK: vgfmb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xb4 + +#CHECK: vgfmb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xb4 + +#CHECK: vgfmb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xb4 + +#CHECK: vgfmf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xb4 + +#CHECK: vgfmf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xb4 + +#CHECK: vgfmf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xb4 + +#CHECK: vgfmg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xb4 + +#CHECK: vgfmg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xb4 + +#CHECK: vgfmg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xb4 + +#CHECK: vgfmh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xb4 + +#CHECK: vgfmh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xb4 + +#CHECK: vgfmh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xb4 + +#CHECK: vgmb %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x46 + +#CHECK: vgmb %v22, 55, 66 +0xe7 0x60 0x37 0x42 0x08 0x46 + +#CHECK: vgmb %v31, 255, 255 +0xe7 0xf0 0xff 0xff 0x08 0x46 + +#CHECK: vgmf %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x20 0x46 + +#CHECK: vgmf %v22, 55, 66 +0xe7 0x60 0x37 0x42 0x28 0x46 + +#CHECK: vgmf %v31, 255, 255 +0xe7 0xf0 0xff 0xff 0x28 0x46 + +#CHECK: vgmg %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x30 0x46 + +#CHECK: vgmg %v22, 55, 66 +0xe7 0x60 0x37 0x42 0x38 0x46 + +#CHECK: vgmg %v31, 255, 255 +0xe7 0xf0 0xff 0xff 0x38 0x46 + +#CHECK: vgmh %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x10 0x46 + +#CHECK: vgmh %v22, 55, 66 +0xe7 0x60 0x37 0x42 0x18 0x46 + +#CHECK: vgmh %v31, 255, 255 +0xe7 0xf0 0xff 0xff 0x18 0x46 + +#CHECK: vl %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x06 + +#CHECK: vl %v17, 2475(%r7,%r8) +0xe7 0x17 0x89 0xab 0x08 0x06 + +#CHECK: vl %v31, 4095(%r15,%r15) +0xe7 0xff 0xff 0xff 0x08 0x06 + +#CHECK: vlbb %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x07 + +#CHECK: vlbb %v17, 2475(%r7,%r8), 12 +0xe7 0x17 0x89 0xab 0xc8 0x07 + +#CHECK: vlbb %v31, 4095(%r15,%r15), 15 +0xe7 0xff 0xff 0xff 0xf8 0x07 + +#CHECK: vlcb %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xde + +#CHECK: vlcb %v19, %v14 +0xe7 0x3e 0x00 0x00 0x08 0xde + +#CHECK: vlcb %v31, %v31 +0xe7 0xff 0x00 0x00 0x0c 0xde + +#CHECK: vlcf %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xde + +#CHECK: vlcf %v19, %v14 +0xe7 0x3e 0x00 0x00 0x28 0xde + +#CHECK: vlcf %v31, %v31 +0xe7 0xff 0x00 0x00 0x2c 0xde + +#CHECK: vlcg %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xde + +#CHECK: vlcg %v19, %v14 +0xe7 0x3e 0x00 0x00 0x38 0xde + +#CHECK: vlcg %v31, %v31 +0xe7 0xff 0x00 0x00 0x3c 0xde + +#CHECK: vlch %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xde + +#CHECK: vlch %v19, %v14 +0xe7 0x3e 0x00 0x00 0x18 0xde + +#CHECK: vlch %v31, %v31 +0xe7 0xff 0x00 0x00 0x1c 0xde + +#CHECK: vldeb %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xc4 + +#CHECK: vldeb %v19, %v14 +0xe7 0x3e 0x00 0x00 0x28 0xc4 + +#CHECK: vldeb %v31, %v31 +0xe7 0xff 0x00 0x00 0x2c 0xc4 + +#CHECK: vleb %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x00 + +#CHECK: vleb %v17, 2475(%r7,%r8), 12 +0xe7 0x17 0x89 0xab 0xc8 0x00 + +#CHECK: vleb %v31, 4095(%r15,%r15), 15 +0xe7 0xff 0xff 0xff 0xf8 0x00 + +#CHECK: vledb %v0, %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x30 0xc5 + +#CHECK: vledb %v19, %v14, 4, 10 +0xe7 0x3e 0x00 0xa4 0x38 0xc5 + +#CHECK: vledb %v31, %v31, 7, 15 +0xe7 0xff 0x00 0xf7 0x3c 0xc5 + +#CHECK: vlef %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x03 + +#CHECK: vlef %v17, 2475(%r7,%r8), 2 +0xe7 0x17 0x89 0xab 0x28 0x03 + +#CHECK: vlef %v31, 4095(%r15,%r15), 3 +0xe7 0xff 0xff 0xff 0x38 0x03 + +#CHECK: vleg %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x02 + +#CHECK: vleg %v17, 2475(%r7,%r8), 1 +0xe7 0x17 0x89 0xab 0x18 0x02 + +#CHECK: vleg %v31, 4095(%r15,%r15), 1 +0xe7 0xff 0xff 0xff 0x18 0x02 + +#CHECK: vleh %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x01 + +#CHECK: vleh %v17, 2475(%r7,%r8), 5 +0xe7 0x17 0x89 0xab 0x58 0x01 + +#CHECK: vleh %v31, 4095(%r15,%r15), 7 +0xe7 0xff 0xff 0xff 0x78 0x01 + +#CHECK: vleib %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x40 + +#CHECK: vleib %v23, -30293, 12 +0xe7 0x70 0x89 0xab 0xc8 0x40 + +#CHECK: vleib %v31, -1, 15 +0xe7 0xf0 0xff 0xff 0xf8 0x40 + +#CHECK: vleif %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x43 + +#CHECK: vleif %v23, -30293, 2 +0xe7 0x70 0x89 0xab 0x28 0x43 + +#CHECK: vleif %v31, -1, 3 +0xe7 0xf0 0xff 0xff 0x38 0x43 + +#CHECK: vleig %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x42 + +#CHECK: vleig %v23, -30293, 1 +0xe7 0x70 0x89 0xab 0x18 0x42 + +#CHECK: vleig %v31, -1, 1 +0xe7 0xf0 0xff 0xff 0x18 0x42 + +#CHECK: vleih %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x41 + +#CHECK: vleih %v23, -30293, 5 +0xe7 0x70 0x89 0xab 0x58 0x41 + +#CHECK: vleih %v31, -1, 7 +0xe7 0xf0 0xff 0xff 0x78 0x41 + +#CHECK: vflcdb %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xcc + +#CHECK: vflcdb %v19, %v14 +0xe7 0x3e 0x00 0x00 0x38 0xcc + +#CHECK: vflcdb %v31, %v31 +0xe7 0xff 0x00 0x00 0x3c 0xcc + +#CHECK: vflndb %v0, %v0 +0xe7 0x00 0x00 0x10 0x30 0xcc + +#CHECK: vflndb %v19, %v14 +0xe7 0x3e 0x00 0x10 0x38 0xcc + +#CHECK: vflndb %v31, %v31 +0xe7 0xff 0x00 0x10 0x3c 0xcc + +#CHECK: vflpdb %v0, %v0 +0xe7 0x00 0x00 0x20 0x30 0xcc + +#CHECK: vflpdb %v19, %v14 +0xe7 0x3e 0x00 0x20 0x38 0xcc + +#CHECK: vflpdb %v31, %v31 +0xe7 0xff 0x00 0x20 0x3c 0xcc + +#CHECK: vlgvb %r0, %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x21 + +#CHECK: vlgvb %r2, %v19, 1383(%r4) +0xe7 0x23 0x45 0x67 0x04 0x21 + +#CHECK: vlgvb %r15, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x04 0x21 + +#CHECK: vlgvf %r0, %v0, 0 +0xe7 0x00 0x00 0x00 0x20 0x21 + +#CHECK: vlgvf %r2, %v19, 1383(%r4) +0xe7 0x23 0x45 0x67 0x24 0x21 + +#CHECK: vlgvf %r15, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x24 0x21 + +#CHECK: vlgvg %r0, %v0, 0 +0xe7 0x00 0x00 0x00 0x30 0x21 + +#CHECK: vlgvg %r2, %v19, 1383(%r4) +0xe7 0x23 0x45 0x67 0x34 0x21 + +#CHECK: vlgvg %r15, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x34 0x21 + +#CHECK: vlgvh %r0, %v0, 0 +0xe7 0x00 0x00 0x00 0x10 0x21 + +#CHECK: vlgvh %r2, %v19, 1383(%r4) +0xe7 0x23 0x45 0x67 0x14 0x21 + +#CHECK: vlgvh %r15, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x14 0x21 + +#CHECK: vfsqdb %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xce + +#CHECK: vfsqdb %v19, %v14 +0xe7 0x3e 0x00 0x00 0x38 0xce + +#CHECK: vfsqdb %v31, %v31 +0xe7 0xff 0x00 0x00 0x3c 0xce + +#CHECK: vftcidb %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x30 0x4a + +#CHECK: vftcidb %v19, %v4, 1383 +0xe7 0x34 0x56 0x70 0x38 0x4a + +#CHECK: vftcidb %v31, %v31, 4095 +0xe7 0xff 0xff 0xf0 0x3c 0x4a + +#CHECK: vll %v0, %r0, 0 +0xe7 0x00 0x00 0x00 0x00 0x37 + +#CHECK: vll %v18, %r3, 1383(%r4) +0xe7 0x23 0x45 0x67 0x08 0x37 + +#CHECK: vll %v31, %r15, 4095(%r15) +0xe7 0xff 0xff 0xff 0x08 0x37 + +#CHECK: vllezb %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x04 + +#CHECK: vllezb %v17, 2475(%r7,%r8) +0xe7 0x17 0x89 0xab 0x08 0x04 + +#CHECK: vllezb %v31, 4095(%r15,%r15) +0xe7 0xff 0xff 0xff 0x08 0x04 + +#CHECK: vllezf %v0, 0 +0xe7 0x00 0x00 0x00 0x20 0x04 + +#CHECK: vllezf %v17, 2475(%r7,%r8) +0xe7 0x17 0x89 0xab 0x28 0x04 + +#CHECK: vllezf %v31, 4095(%r15,%r15) +0xe7 0xff 0xff 0xff 0x28 0x04 + +#CHECK: vllezg %v0, 0 +0xe7 0x00 0x00 0x00 0x30 0x04 + +#CHECK: vllezg %v17, 2475(%r7,%r8) +0xe7 0x17 0x89 0xab 0x38 0x04 + +#CHECK: vllezg %v31, 4095(%r15,%r15) +0xe7 0xff 0xff 0xff 0x38 0x04 + +#CHECK: vllezh %v0, 0 +0xe7 0x00 0x00 0x00 0x10 0x04 + +#CHECK: vllezh %v17, 2475(%r7,%r8) +0xe7 0x17 0x89 0xab 0x18 0x04 + +#CHECK: vllezh %v31, 4095(%r15,%r15) +0xe7 0xff 0xff 0xff 0x18 0x04 + +#CHECK: vlm %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x36 + +#CHECK: vlm %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x04 0x36 + +#CHECK: vlm %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x0c 0x36 + +#CHECK: vlpb %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xdf + +#CHECK: vlpb %v19, %v14 +0xe7 0x3e 0x00 0x00 0x08 0xdf + +#CHECK: vlpb %v31, %v31 +0xe7 0xff 0x00 0x00 0x0c 0xdf + +#CHECK: vlpf %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xdf + +#CHECK: vlpf %v19, %v14 +0xe7 0x3e 0x00 0x00 0x28 0xdf + +#CHECK: vlpf %v31, %v31 +0xe7 0xff 0x00 0x00 0x2c 0xdf + +#CHECK: vlpg %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xdf + +#CHECK: vlpg %v19, %v14 +0xe7 0x3e 0x00 0x00 0x38 0xdf + +#CHECK: vlpg %v31, %v31 +0xe7 0xff 0x00 0x00 0x3c 0xdf + +#CHECK: vlph %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xdf + +#CHECK: vlph %v19, %v14 +0xe7 0x3e 0x00 0x00 0x18 0xdf + +#CHECK: vlph %v31, %v31 +0xe7 0xff 0x00 0x00 0x1c 0xdf + +#CHECK: vlr %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x56 + +#CHECK: vlr %v19, %v14 +0xe7 0x3e 0x00 0x00 0x08 0x56 + +#CHECK: vlr %v31, %v31 +0xe7 0xff 0x00 0x00 0x0c 0x56 + +#CHECK: vlrepb %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x05 + +#CHECK: vlrepb %v17, 2475(%r7,%r8) +0xe7 0x17 0x89 0xab 0x08 0x05 + +#CHECK: vlrepb %v31, 4095(%r15,%r15) +0xe7 0xff 0xff 0xff 0x08 0x05 + +#CHECK: vlrepf %v0, 0 +0xe7 0x00 0x00 0x00 0x20 0x05 + +#CHECK: vlrepf %v17, 2475(%r7,%r8) +0xe7 0x17 0x89 0xab 0x28 0x05 + +#CHECK: vlrepf %v31, 4095(%r15,%r15) +0xe7 0xff 0xff 0xff 0x28 0x05 + +#CHECK: vlrepg %v0, 0 +0xe7 0x00 0x00 0x00 0x30 0x05 + +#CHECK: vlrepg %v17, 2475(%r7,%r8) +0xe7 0x17 0x89 0xab 0x38 0x05 + +#CHECK: vlrepg %v31, 4095(%r15,%r15) +0xe7 0xff 0xff 0xff 0x38 0x05 + +#CHECK: vlreph %v0, 0 +0xe7 0x00 0x00 0x00 0x10 0x05 + +#CHECK: vlreph %v17, 2475(%r7,%r8) +0xe7 0x17 0x89 0xab 0x18 0x05 + +#CHECK: vlreph %v31, 4095(%r15,%r15) +0xe7 0xff 0xff 0xff 0x18 0x05 + +#CHECK: vlvgb %v0, %r0, 0 +0xe7 0x00 0x00 0x00 0x00 0x22 + +#CHECK: vlvgb %v18, %r3, 1383(%r4) +0xe7 0x23 0x45 0x67 0x08 0x22 + +#CHECK: vlvgb %v31, %r15, 4095(%r15) +0xe7 0xff 0xff 0xff 0x08 0x22 + +#CHECK: vlvgf %v0, %r0, 0 +0xe7 0x00 0x00 0x00 0x20 0x22 + +#CHECK: vlvgf %v18, %r3, 1383(%r4) +0xe7 0x23 0x45 0x67 0x28 0x22 + +#CHECK: vlvgf %v31, %r15, 4095(%r15) +0xe7 0xff 0xff 0xff 0x28 0x22 + +#CHECK: vlvgg %v0, %r0, 0 +0xe7 0x00 0x00 0x00 0x30 0x22 + +#CHECK: vlvgg %v18, %r3, 1383(%r4) +0xe7 0x23 0x45 0x67 0x38 0x22 + +#CHECK: vlvgg %v31, %r15, 4095(%r15) +0xe7 0xff 0xff 0xff 0x38 0x22 + +#CHECK: vlvgh %v0, %r0, 0 +0xe7 0x00 0x00 0x00 0x10 0x22 + +#CHECK: vlvgh %v18, %r3, 1383(%r4) +0xe7 0x23 0x45 0x67 0x18 0x22 + +#CHECK: vlvgh %v31, %r15, 4095(%r15) +0xe7 0xff 0xff 0xff 0x18 0x22 + +#CHECK: vlvgp %v0, %r0, %r0 +0xe7 0x00 0x00 0x00 0x00 0x62 + +#CHECK: vlvgp %v18, %r3, %r4 +0xe7 0x23 0x40 0x00 0x08 0x62 + +#CHECK: vlvgp %v31, %r15, %r15 +0xe7 0xff 0xf0 0x00 0x08 0x62 + +#CHECK: vmaeb %v0, %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xae + +#CHECK: vmaeb %v3, %v20, %v5, %v22 +0xe7 0x34 0x50 0x00 0x65 0xae + +#CHECK: vmaeb %v31, %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0xff 0xae + +#CHECK: vmaef %v0, %v0, %v0, %v0 +0xe7 0x00 0x02 0x00 0x00 0xae + +#CHECK: vmaef %v3, %v20, %v5, %v22 +0xe7 0x34 0x52 0x00 0x65 0xae + +#CHECK: vmaef %v31, %v31, %v31, %v31 +0xe7 0xff 0xf2 0x00 0xff 0xae + +#CHECK: vmaeh %v0, %v0, %v0, %v0 +0xe7 0x00 0x01 0x00 0x00 0xae + +#CHECK: vmaeh %v3, %v20, %v5, %v22 +0xe7 0x34 0x51 0x00 0x65 0xae + +#CHECK: vmaeh %v31, %v31, %v31, %v31 +0xe7 0xff 0xf1 0x00 0xff 0xae + +#CHECK: vmahb %v0, %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xab + +#CHECK: vmahb %v3, %v20, %v5, %v22 +0xe7 0x34 0x50 0x00 0x65 0xab + +#CHECK: vmahb %v31, %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0xff 0xab + +#CHECK: vmahf %v0, %v0, %v0, %v0 +0xe7 0x00 0x02 0x00 0x00 0xab + +#CHECK: vmahf %v3, %v20, %v5, %v22 +0xe7 0x34 0x52 0x00 0x65 0xab + +#CHECK: vmahf %v31, %v31, %v31, %v31 +0xe7 0xff 0xf2 0x00 0xff 0xab + +#CHECK: vmahh %v0, %v0, %v0, %v0 +0xe7 0x00 0x01 0x00 0x00 0xab + +#CHECK: vmahh %v3, %v20, %v5, %v22 +0xe7 0x34 0x51 0x00 0x65 0xab + +#CHECK: vmahh %v31, %v31, %v31, %v31 +0xe7 0xff 0xf1 0x00 0xff 0xab + +#CHECK: vmalb %v0, %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xaa + +#CHECK: vmalb %v3, %v20, %v5, %v22 +0xe7 0x34 0x50 0x00 0x65 0xaa + +#CHECK: vmalb %v31, %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0xff 0xaa + +#CHECK: vmaleb %v0, %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xac + +#CHECK: vmaleb %v3, %v20, %v5, %v22 +0xe7 0x34 0x50 0x00 0x65 0xac + +#CHECK: vmaleb %v31, %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0xff 0xac + +#CHECK: vmalef %v0, %v0, %v0, %v0 +0xe7 0x00 0x02 0x00 0x00 0xac + +#CHECK: vmalef %v3, %v20, %v5, %v22 +0xe7 0x34 0x52 0x00 0x65 0xac + +#CHECK: vmalef %v31, %v31, %v31, %v31 +0xe7 0xff 0xf2 0x00 0xff 0xac + +#CHECK: vmaleh %v0, %v0, %v0, %v0 +0xe7 0x00 0x01 0x00 0x00 0xac + +#CHECK: vmaleh %v3, %v20, %v5, %v22 +0xe7 0x34 0x51 0x00 0x65 0xac + +#CHECK: vmaleh %v31, %v31, %v31, %v31 +0xe7 0xff 0xf1 0x00 0xff 0xac + +#CHECK: vmalf %v0, %v0, %v0, %v0 +0xe7 0x00 0x02 0x00 0x00 0xaa + +#CHECK: vmalf %v3, %v20, %v5, %v22 +0xe7 0x34 0x52 0x00 0x65 0xaa + +#CHECK: vmalf %v31, %v31, %v31, %v31 +0xe7 0xff 0xf2 0x00 0xff 0xaa + +#CHECK: vmalhb %v0, %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xa9 + +#CHECK: vmalhb %v3, %v20, %v5, %v22 +0xe7 0x34 0x50 0x00 0x65 0xa9 + +#CHECK: vmalhb %v31, %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0xff 0xa9 + +#CHECK: vmalhf %v0, %v0, %v0, %v0 +0xe7 0x00 0x02 0x00 0x00 0xa9 + +#CHECK: vmalhf %v3, %v20, %v5, %v22 +0xe7 0x34 0x52 0x00 0x65 0xa9 + +#CHECK: vmalhf %v31, %v31, %v31, %v31 +0xe7 0xff 0xf2 0x00 0xff 0xa9 + +#CHECK: vmalhh %v0, %v0, %v0, %v0 +0xe7 0x00 0x01 0x00 0x00 0xa9 + +#CHECK: vmalhh %v3, %v20, %v5, %v22 +0xe7 0x34 0x51 0x00 0x65 0xa9 + +#CHECK: vmalhh %v31, %v31, %v31, %v31 +0xe7 0xff 0xf1 0x00 0xff 0xa9 + +#CHECK: vmalhw %v0, %v0, %v0, %v0 +0xe7 0x00 0x01 0x00 0x00 0xaa + +#CHECK: vmalhw %v3, %v20, %v5, %v22 +0xe7 0x34 0x51 0x00 0x65 0xaa + +#CHECK: vmalhw %v31, %v31, %v31, %v31 +0xe7 0xff 0xf1 0x00 0xff 0xaa + +#CHECK: vmalob %v0, %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xad + +#CHECK: vmalob %v3, %v20, %v5, %v22 +0xe7 0x34 0x50 0x00 0x65 0xad + +#CHECK: vmalob %v31, %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0xff 0xad + +#CHECK: vmalof %v0, %v0, %v0, %v0 +0xe7 0x00 0x02 0x00 0x00 0xad + +#CHECK: vmalof %v3, %v20, %v5, %v22 +0xe7 0x34 0x52 0x00 0x65 0xad + +#CHECK: vmalof %v31, %v31, %v31, %v31 +0xe7 0xff 0xf2 0x00 0xff 0xad + +#CHECK: vmaloh %v0, %v0, %v0, %v0 +0xe7 0x00 0x01 0x00 0x00 0xad + +#CHECK: vmaloh %v3, %v20, %v5, %v22 +0xe7 0x34 0x51 0x00 0x65 0xad + +#CHECK: vmaloh %v31, %v31, %v31, %v31 +0xe7 0xff 0xf1 0x00 0xff 0xad + +#CHECK: vmaob %v0, %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xaf + +#CHECK: vmaob %v3, %v20, %v5, %v22 +0xe7 0x34 0x50 0x00 0x65 0xaf + +#CHECK: vmaob %v31, %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0xff 0xaf + +#CHECK: vmaof %v0, %v0, %v0, %v0 +0xe7 0x00 0x02 0x00 0x00 0xaf + +#CHECK: vmaof %v3, %v20, %v5, %v22 +0xe7 0x34 0x52 0x00 0x65 0xaf + +#CHECK: vmaof %v31, %v31, %v31, %v31 +0xe7 0xff 0xf2 0x00 0xff 0xaf + +#CHECK: vmaoh %v0, %v0, %v0, %v0 +0xe7 0x00 0x01 0x00 0x00 0xaf + +#CHECK: vmaoh %v3, %v20, %v5, %v22 +0xe7 0x34 0x51 0x00 0x65 0xaf + +#CHECK: vmaoh %v31, %v31, %v31, %v31 +0xe7 0xff 0xf1 0x00 0xff 0xaf + +#CHECK: vmeb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xa6 + +#CHECK: vmeb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xa6 + +#CHECK: vmeb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xa6 + +#CHECK: vmef %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xa6 + +#CHECK: vmef %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xa6 + +#CHECK: vmef %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xa6 + +#CHECK: vmeh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xa6 + +#CHECK: vmeh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xa6 + +#CHECK: vmeh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xa6 + +#CHECK: vmhb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xa3 + +#CHECK: vmhb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xa3 + +#CHECK: vmhb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xa3 + +#CHECK: vmhf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xa3 + +#CHECK: vmhf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xa3 + +#CHECK: vmhf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xa3 + +#CHECK: vmhh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xa3 + +#CHECK: vmhh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xa3 + +#CHECK: vmhh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xa3 + +#CHECK: vmlb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xa2 + +#CHECK: vmlb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xa2 + +#CHECK: vmlb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xa2 + +#CHECK: vmlf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xa2 + +#CHECK: vmlf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xa2 + +#CHECK: vmlf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xa2 + +#CHECK: vmleb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xa4 + +#CHECK: vmleb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xa4 + +#CHECK: vmleb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xa4 + +#CHECK: vmlef %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xa4 + +#CHECK: vmlef %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xa4 + +#CHECK: vmlef %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xa4 + +#CHECK: vmleh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xa4 + +#CHECK: vmleh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xa4 + +#CHECK: vmleh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xa4 + +#CHECK: vmlhb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xa1 + +#CHECK: vmlhb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xa1 + +#CHECK: vmlhb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xa1 + +#CHECK: vmlhf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xa1 + +#CHECK: vmlhf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xa1 + +#CHECK: vmlhf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xa1 + +#CHECK: vmlhh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xa1 + +#CHECK: vmlhh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xa1 + +#CHECK: vmlhh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xa1 + +#CHECK: vmlhw %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xa2 + +#CHECK: vmlhw %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xa2 + +#CHECK: vmlhw %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xa2 + +#CHECK: vmlob %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xa5 + +#CHECK: vmlob %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xa5 + +#CHECK: vmlob %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xa5 + +#CHECK: vmlof %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xa5 + +#CHECK: vmlof %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xa5 + +#CHECK: vmlof %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xa5 + +#CHECK: vmloh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xa5 + +#CHECK: vmloh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xa5 + +#CHECK: vmloh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xa5 + +#CHECK: vmnb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xfe + +#CHECK: vmnb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xfe + +#CHECK: vmnb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xfe + +#CHECK: vmnf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xfe + +#CHECK: vmnf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xfe + +#CHECK: vmnf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xfe + +#CHECK: vmng %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xfe + +#CHECK: vmng %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xfe + +#CHECK: vmng %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xfe + +#CHECK: vmnh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xfe + +#CHECK: vmnh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xfe + +#CHECK: vmnh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xfe + +#CHECK: vmnlb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xfc + +#CHECK: vmnlb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xfc + +#CHECK: vmnlb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xfc + +#CHECK: vmnlf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xfc + +#CHECK: vmnlf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xfc + +#CHECK: vmnlf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xfc + +#CHECK: vmnlg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xfc + +#CHECK: vmnlg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xfc + +#CHECK: vmnlg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xfc + +#CHECK: vmnlh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xfc + +#CHECK: vmnlh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xfc + +#CHECK: vmnlh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xfc + +#CHECK: vmob %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xa7 + +#CHECK: vmob %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xa7 + +#CHECK: vmob %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xa7 + +#CHECK: vmof %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xa7 + +#CHECK: vmof %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xa7 + +#CHECK: vmof %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xa7 + +#CHECK: vmoh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xa7 + +#CHECK: vmoh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xa7 + +#CHECK: vmoh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xa7 + +#CHECK: vmrhb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x61 + +#CHECK: vmrhb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x61 + +#CHECK: vmrhb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x61 + +#CHECK: vmrhf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x61 + +#CHECK: vmrhf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0x61 + +#CHECK: vmrhf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0x61 + +#CHECK: vmrhg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0x61 + +#CHECK: vmrhg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0x61 + +#CHECK: vmrhg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0x61 + +#CHECK: vmrhh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x61 + +#CHECK: vmrhh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0x61 + +#CHECK: vmrhh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0x61 + +#CHECK: vmrlb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x60 + +#CHECK: vmrlb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x60 + +#CHECK: vmrlb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x60 + +#CHECK: vmrlf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x60 + +#CHECK: vmrlf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0x60 + +#CHECK: vmrlf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0x60 + +#CHECK: vmrlg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0x60 + +#CHECK: vmrlg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0x60 + +#CHECK: vmrlg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0x60 + +#CHECK: vmrlh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x60 + +#CHECK: vmrlh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0x60 + +#CHECK: vmrlh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0x60 + +#CHECK: vmxb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xff + +#CHECK: vmxb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xff + +#CHECK: vmxb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xff + +#CHECK: vmxf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xff + +#CHECK: vmxf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xff + +#CHECK: vmxf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xff + +#CHECK: vmxg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xff + +#CHECK: vmxg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xff + +#CHECK: vmxg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xff + +#CHECK: vmxh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xff + +#CHECK: vmxh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xff + +#CHECK: vmxh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xff + +#CHECK: vmxlb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xfd + +#CHECK: vmxlb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xfd + +#CHECK: vmxlb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xfd + +#CHECK: vmxlf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xfd + +#CHECK: vmxlf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xfd + +#CHECK: vmxlf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xfd + +#CHECK: vmxlg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xfd + +#CHECK: vmxlg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xfd + +#CHECK: vmxlg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xfd + +#CHECK: vmxlh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xfd + +#CHECK: vmxlh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xfd + +#CHECK: vmxlh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xfd + +#CHECK: vn %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x68 + +#CHECK: vn %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x68 + +#CHECK: vn %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x68 + +#CHECK: vnc %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x69 + +#CHECK: vnc %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x69 + +#CHECK: vnc %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x69 + +#CHECK: vno %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x6b + +#CHECK: vno %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x6b + +#CHECK: vno %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x6b + +#CHECK: vo %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x6a + +#CHECK: vo %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x6a + +#CHECK: vo %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x6a + +#CHECK: vpdi %v0, %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x84 + +#CHECK: vpdi %v3, %v20, %v5, 4 +0xe7 0x34 0x50 0x00 0x44 0x84 + +#CHECK: vpdi %v31, %v31, %v31, 15 +0xe7 0xff 0xf0 0x00 0xfe 0x84 + +#CHECK: vperm %v0, %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x8c + +#CHECK: vperm %v3, %v20, %v5, %v22 +0xe7 0x34 0x50 0x00 0x65 0x8c + +#CHECK: vperm %v31, %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0xff 0x8c + +#CHECK: vpkf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x94 + +#CHECK: vpkf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0x94 + +#CHECK: vpkf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0x94 + +#CHECK: vpkg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0x94 + +#CHECK: vpkg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0x94 + +#CHECK: vpkg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0x94 + +#CHECK: vpkh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x94 + +#CHECK: vpkh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0x94 + +#CHECK: vpkh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0x94 + +#CHECK: vpklsf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x95 + +#CHECK: vpklsf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0x95 + +#CHECK: vpklsfs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x24 0x95 + +#CHECK: vpklsf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0x95 + +#CHECK: vpklsg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0x95 + +#CHECK: vpklsg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0x95 + +#CHECK: vpklsgs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x34 0x95 + +#CHECK: vpklsg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0x95 + +#CHECK: vpklsh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x95 + +#CHECK: vpklsh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0x95 + +#CHECK: vpklshs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x14 0x95 + +#CHECK: vpklsh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0x95 + +#CHECK: vpksf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x97 + +#CHECK: vpksf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0x97 + +#CHECK: vpksfs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x24 0x97 + +#CHECK: vpksf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0x97 + +#CHECK: vpksg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0x97 + +#CHECK: vpksg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0x97 + +#CHECK: vpksgs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x34 0x97 + +#CHECK: vpksg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0x97 + +#CHECK: vpksh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x97 + +#CHECK: vpksh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0x97 + +#CHECK: vpkshs %v7, %v24, %v9 +0xe7 0x78 0x90 0x10 0x14 0x97 + +#CHECK: vpksh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0x97 + +#CHECK: vpopct %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x50 + +#CHECK: vpopct %v19, %v14, 0 +0xe7 0x3e 0x00 0x00 0x08 0x50 + +#CHECK: vpopct %v31, %v31 +0xe7 0xff 0x00 0x00 0x0c 0x50 + +#CHECK: vrepb %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x4d + +#CHECK: vrepb %v19, %v4, 22136 +0xe7 0x34 0x56 0x78 0x08 0x4d + +#CHECK: vrepb %v31, %v31, 65535 +0xe7 0xff 0xff 0xff 0x0c 0x4d + +#CHECK: vrepf %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x20 0x4d + +#CHECK: vrepf %v19, %v4, 22136 +0xe7 0x34 0x56 0x78 0x28 0x4d + +#CHECK: vrepf %v31, %v31, 65535 +0xe7 0xff 0xff 0xff 0x2c 0x4d + +#CHECK: vrepg %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x30 0x4d + +#CHECK: vrepg %v19, %v4, 22136 +0xe7 0x34 0x56 0x78 0x38 0x4d + +#CHECK: vrepg %v31, %v31, 65535 +0xe7 0xff 0xff 0xff 0x3c 0x4d + +#CHECK: vreph %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x10 0x4d + +#CHECK: vreph %v19, %v4, 22136 +0xe7 0x34 0x56 0x78 0x18 0x4d + +#CHECK: vreph %v31, %v31, 65535 +0xe7 0xff 0xff 0xff 0x1c 0x4d + +#CHECK: vrepib %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x45 + +#CHECK: vrepib %v23, -30293 +0xe7 0x70 0x89 0xab 0x08 0x45 + +#CHECK: vrepib %v31, -1 +0xe7 0xf0 0xff 0xff 0x08 0x45 + +#CHECK: vrepif %v0, 0 +0xe7 0x00 0x00 0x00 0x20 0x45 + +#CHECK: vrepif %v23, -30293 +0xe7 0x70 0x89 0xab 0x28 0x45 + +#CHECK: vrepif %v31, -1 +0xe7 0xf0 0xff 0xff 0x28 0x45 + +#CHECK: vrepig %v0, 0 +0xe7 0x00 0x00 0x00 0x30 0x45 + +#CHECK: vrepig %v23, -30293 +0xe7 0x70 0x89 0xab 0x38 0x45 + +#CHECK: vrepig %v31, -1 +0xe7 0xf0 0xff 0xff 0x38 0x45 + +#CHECK: vrepih %v0, 0 +0xe7 0x00 0x00 0x00 0x10 0x45 + +#CHECK: vrepih %v23, -30293 +0xe7 0x70 0x89 0xab 0x18 0x45 + +#CHECK: vrepih %v31, -1 +0xe7 0xf0 0xff 0xff 0x18 0x45 + +#CHECK: vsb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xf7 + +#CHECK: vsb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xf7 + +#CHECK: vsb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xf7 + +#CHECK: vsbiq %v0, %v0, %v0, %v0 +0xe7 0x00 0x04 0x00 0x00 0xbf + +#CHECK: vsbiq %v3, %v20, %v5, %v22 +0xe7 0x34 0x54 0x00 0x65 0xbf + +#CHECK: vsbiq %v31, %v31, %v31, %v31 +0xe7 0xff 0xf4 0x00 0xff 0xbf + +#CHECK: vsbcbiq %v0, %v0, %v0, %v0 +0xe7 0x00 0x04 0x00 0x00 0xbd + +#CHECK: vsbcbiq %v3, %v20, %v5, %v22 +0xe7 0x34 0x54 0x00 0x65 0xbd + +#CHECK: vsbcbiq %v31, %v31, %v31, %v31 +0xe7 0xff 0xf4 0x00 0xff 0xbd + +#CHECK: vscbib %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xf5 + +#CHECK: vscbib %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0xf5 + +#CHECK: vscbib %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0xf5 + +#CHECK: vscbif %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xf5 + +#CHECK: vscbif %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xf5 + +#CHECK: vscbif %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xf5 + +#CHECK: vscbig %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xf5 + +#CHECK: vscbig %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xf5 + +#CHECK: vscbig %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xf5 + +#CHECK: vscbih %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xf5 + +#CHECK: vscbih %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xf5 + +#CHECK: vscbih %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xf5 + +#CHECK: vscbiq %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x40 0xf5 + +#CHECK: vscbiq %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x4a 0xf5 + +#CHECK: vscbiq %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x4e 0xf5 + +#CHECK: vscef %v0, 0(%v0), 0 +0xe7 0x00 0x00 0x00 0x00 0x1b + +#CHECK: vscef %v10, 1000(%v19,%r7), 2 +0xe7 0xa3 0x73 0xe8 0x24 0x1b + +#CHECK: vscef %v31, 4095(%v31,%r15), 3 +0xe7 0xff 0xff 0xff 0x3c 0x1b + +#CHECK: vsceg %v0, 0(%v0), 0 +0xe7 0x00 0x00 0x00 0x00 0x1a + +#CHECK: vsceg %v10, 1000(%v19,%r7), 1 +0xe7 0xa3 0x73 0xe8 0x14 0x1a + +#CHECK: vsceg %v31, 4095(%v31,%r15), 1 +0xe7 0xff 0xff 0xff 0x1c 0x1a + +#CHECK: vsegb %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x5f + +#CHECK: vsegb %v19, %v14 +0xe7 0x3e 0x00 0x00 0x08 0x5f + +#CHECK: vsegb %v31, %v31 +0xe7 0xff 0x00 0x00 0x0c 0x5f + +#CHECK: vsegf %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x5f + +#CHECK: vsegf %v19, %v14 +0xe7 0x3e 0x00 0x00 0x28 0x5f + +#CHECK: vsegf %v31, %v31 +0xe7 0xff 0x00 0x00 0x2c 0x5f + +#CHECK: vsegh %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x5f + +#CHECK: vsegh %v19, %v14 +0xe7 0x3e 0x00 0x00 0x18 0x5f + +#CHECK: vsegh %v31, %v31 +0xe7 0xff 0x00 0x00 0x1c 0x5f + +#CHECK: vsel %v0, %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x8d + +#CHECK: vsel %v3, %v20, %v5, %v22 +0xe7 0x34 0x50 0x00 0x65 0x8d + +#CHECK: vsel %v31, %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0xff 0x8d + +#CHECK: vsf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xf7 + +#CHECK: vsf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0xf7 + +#CHECK: vsf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0xf7 + +#CHECK: vsg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0xf7 + +#CHECK: vsg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0xf7 + +#CHECK: vsg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0xf7 + +#CHECK: vsh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xf7 + +#CHECK: vsh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0xf7 + +#CHECK: vsh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0xf7 + +#CHECK: vsl %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x74 + +#CHECK: vsl %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x74 + +#CHECK: vsl %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x74 + +#CHECK: vslb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x75 + +#CHECK: vslb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x75 + +#CHECK: vslb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x75 + +#CHECK: vsldb %v0, %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x77 + +#CHECK: vsldb %v3, %v20, %v5, 103 +0xe7 0x34 0x50 0x67 0x04 0x77 + +#CHECK: vsldb %v31, %v31, %v31, 255 +0xe7 0xff 0xf0 0xff 0x0e 0x77 + +#CHECK: vsq %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x40 0xf7 + +#CHECK: vsq %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x4a 0xf7 + +#CHECK: vsq %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x4e 0xf7 + +#CHECK: vsra %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x7e + +#CHECK: vsra %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x7e + +#CHECK: vsra %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x7e + +#CHECK: vsrab %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x7f + +#CHECK: vsrab %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x7f + +#CHECK: vsrab %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x7f + +#CHECK: vsrl %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x7c + +#CHECK: vsrl %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x7c + +#CHECK: vsrl %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x7c + +#CHECK: vsrlb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x7d + +#CHECK: vsrlb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x7d + +#CHECK: vsrlb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x7d + +#CHECK: vst %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x0E + +#CHECK: vst %v17, 2475(%r7,%r8) +0xe7 0x17 0x89 0xab 0x08 0x0E + +#CHECK: vst %v31, 4095(%r15,%r15) +0xe7 0xff 0xff 0xff 0x08 0x0E + +#CHECK: vsteb %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x08 + +#CHECK: vsteb %v17, 2475(%r7,%r8), 12 +0xe7 0x17 0x89 0xab 0xc8 0x08 + +#CHECK: vsteb %v31, 4095(%r15,%r15), 15 +0xe7 0xff 0xff 0xff 0xf8 0x08 + +#CHECK: vstef %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x0b + +#CHECK: vstef %v17, 2475(%r7,%r8), 2 +0xe7 0x17 0x89 0xab 0x28 0x0b + +#CHECK: vstef %v31, 4095(%r15,%r15), 3 +0xe7 0xff 0xff 0xff 0x38 0x0b + +#CHECK: vsteg %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x0a + +#CHECK: vsteg %v17, 2475(%r7,%r8), 1 +0xe7 0x17 0x89 0xab 0x18 0x0a + +#CHECK: vsteg %v31, 4095(%r15,%r15), 1 +0xe7 0xff 0xff 0xff 0x18 0x0a + +#CHECK: vsteh %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x09 + +#CHECK: vsteh %v17, 2475(%r7,%r8), 5 +0xe7 0x17 0x89 0xab 0x58 0x09 + +#CHECK: vsteh %v31, 4095(%r15,%r15), 7 +0xe7 0xff 0xff 0xff 0x78 0x09 + +#CHECK: vstl %v0, %r0, 0 +0xe7 0x00 0x00 0x00 0x00 0x3f + +#CHECK: vstl %v18, %r3, 1383(%r4) +0xe7 0x23 0x45 0x67 0x08 0x3f + +#CHECK: vstl %v31, %r15, 4095(%r15) +0xe7 0xff 0xff 0xff 0x08 0x3f + +#CHECK: vstm %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x3e + +#CHECK: vstm %v12, %v18, 1110(%r3) +0xe7 0xc2 0x34 0x56 0x04 0x3e + +#CHECK: vstm %v31, %v31, 4095(%r15) +0xe7 0xff 0xff 0xff 0x0c 0x3e + +#CHECK: vstrcb %v0, %v0, %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x00 0x8a + +#CHECK: vstrcb %v0, %v0, %v0, %v0, 12 +0xe7 0x00 0x00 0xc0 0x00 0x8a + +#CHECK: vstrcb %v18, %v3, %v20, %v5, 0 +0xe7 0x23 0x40 0x00 0x5a 0x8a + +#CHECK: vstrcb %v31, %v31, %v31, %v31, 4 +0xe7 0xff 0xf0 0x40 0xff 0x8a + +#CHECK: vstrcbs %v31, %v31, %v31, %v31, 8 +0xe7 0xff 0xf0 0x90 0xff 0x8a + +#CHECK: vstrczb %v31, %v31, %v31, %v31, 4 +0xe7 0xff 0xf0 0x60 0xff 0x8a + +#CHECK: vstrczbs %v31, %v31, %v31, %v31, 8 +0xe7 0xff 0xf0 0xb0 0xff 0x8a + +#CHECK: vstrcf %v0, %v0, %v0, %v0, 0 +0xe7 0x00 0x02 0x00 0x00 0x8a + +#CHECK: vstrcf %v0, %v0, %v0, %v0, 12 +0xe7 0x00 0x02 0xc0 0x00 0x8a + +#CHECK: vstrcf %v18, %v3, %v20, %v5, 0 +0xe7 0x23 0x42 0x00 0x5a 0x8a + +#CHECK: vstrcf %v31, %v31, %v31, %v31, 4 +0xe7 0xff 0xf2 0x40 0xff 0x8a + +#CHECK: vstrcfs %v31, %v31, %v31, %v31, 8 +0xe7 0xff 0xf2 0x90 0xff 0x8a + +#CHECK: vstrczf %v31, %v31, %v31, %v31, 4 +0xe7 0xff 0xf2 0x60 0xff 0x8a + +#CHECK: vstrczfs %v31, %v31, %v31, %v31, 8 +0xe7 0xff 0xf2 0xb0 0xff 0x8a + +#CHECK: vstrch %v0, %v0, %v0, %v0, 0 +0xe7 0x00 0x01 0x00 0x00 0x8a + +#CHECK: vstrch %v0, %v0, %v0, %v0, 12 +0xe7 0x00 0x01 0xc0 0x00 0x8a + +#CHECK: vstrch %v18, %v3, %v20, %v5, 0 +0xe7 0x23 0x41 0x00 0x5a 0x8a + +#CHECK: vstrch %v31, %v31, %v31, %v31, 4 +0xe7 0xff 0xf1 0x40 0xff 0x8a + +#CHECK: vstrchs %v31, %v31, %v31, %v31, 8 +0xe7 0xff 0xf1 0x90 0xff 0x8a + +#CHECK: vstrczh %v31, %v31, %v31, %v31, 4 +0xe7 0xff 0xf1 0x60 0xff 0x8a + +#CHECK: vstrczhs %v31, %v31, %v31, %v31, 8 +0xe7 0xff 0xf1 0xb0 0xff 0x8a + +#CHECK: vsumgh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x65 + +#CHECK: vsumgh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0x65 + +#CHECK: vsumgh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0x65 + +#CHECK: vsumgf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x65 + +#CHECK: vsumgf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0x65 + +#CHECK: vsumgf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0x65 + +#CHECK: vsumqf %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x67 + +#CHECK: vsumqf %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x2a 0x67 + +#CHECK: vsumqf %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x2e 0x67 + +#CHECK: vsumqg %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0x67 + +#CHECK: vsumqg %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x3a 0x67 + +#CHECK: vsumqg %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x3e 0x67 + +#CHECK: vsumb %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x64 + +#CHECK: vsumb %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x64 + +#CHECK: vsumb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x64 + +#CHECK: vsumh %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x64 + +#CHECK: vsumh %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x1a 0x64 + +#CHECK: vsumh %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x1e 0x64 + +#CHECK: vtm %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xd8 + +#CHECK: vtm %v19, %v14 +0xe7 0x3e 0x00 0x00 0x08 0xd8 + +#CHECK: vtm %v31, %v31 +0xe7 0xff 0x00 0x00 0x0c 0xd8 + +#CHECK: vuphb %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xd7 + +#CHECK: vuphb %v19, %v14 +0xe7 0x3e 0x00 0x00 0x08 0xd7 + +#CHECK: vuphb %v31, %v31 +0xe7 0xff 0x00 0x00 0x0c 0xd7 + +#CHECK: vuphf %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xd7 + +#CHECK: vuphf %v19, %v14 +0xe7 0x3e 0x00 0x00 0x28 0xd7 + +#CHECK: vuphf %v31, %v31 +0xe7 0xff 0x00 0x00 0x2c 0xd7 + +#CHECK: vuphh %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xd7 + +#CHECK: vuphh %v19, %v14 +0xe7 0x3e 0x00 0x00 0x18 0xd7 + +#CHECK: vuphh %v31, %v31 +0xe7 0xff 0x00 0x00 0x1c 0xd7 + +#CHECK: vuplhb %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xd5 + +#CHECK: vuplhb %v19, %v14 +0xe7 0x3e 0x00 0x00 0x08 0xd5 + +#CHECK: vuplhb %v31, %v31 +0xe7 0xff 0x00 0x00 0x0c 0xd5 + +#CHECK: vuplhf %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xd5 + +#CHECK: vuplhf %v19, %v14 +0xe7 0x3e 0x00 0x00 0x28 0xd5 + +#CHECK: vuplhf %v31, %v31 +0xe7 0xff 0x00 0x00 0x2c 0xd5 + +#CHECK: vuplhh %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xd5 + +#CHECK: vuplhh %v19, %v14 +0xe7 0x3e 0x00 0x00 0x18 0xd5 + +#CHECK: vuplhh %v31, %v31 +0xe7 0xff 0x00 0x00 0x1c 0xd5 + +#CHECK: vuplb %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xd6 + +#CHECK: vuplb %v19, %v14 +0xe7 0x3e 0x00 0x00 0x08 0xd6 + +#CHECK: vuplb %v31, %v31 +0xe7 0xff 0x00 0x00 0x0c 0xd6 + +#CHECK: vuplf %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xd6 + +#CHECK: vuplf %v19, %v14 +0xe7 0x3e 0x00 0x00 0x28 0xd6 + +#CHECK: vuplf %v31, %v31 +0xe7 0xff 0x00 0x00 0x2c 0xd6 + +#CHECK: vuplhw %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xd6 + +#CHECK: vuplhw %v19, %v14 +0xe7 0x3e 0x00 0x00 0x18 0xd6 + +#CHECK: vuplhw %v31, %v31 +0xe7 0xff 0x00 0x00 0x1c 0xd6 + +#CHECK: vupllb %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0xd4 + +#CHECK: vupllb %v19, %v14 +0xe7 0x3e 0x00 0x00 0x08 0xd4 + +#CHECK: vupllb %v31, %v31 +0xe7 0xff 0x00 0x00 0x0c 0xd4 + +#CHECK: vupllf %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0xd4 + +#CHECK: vupllf %v19, %v14 +0xe7 0x3e 0x00 0x00 0x28 0xd4 + +#CHECK: vupllf %v31, %v31 +0xe7 0xff 0x00 0x00 0x2c 0xd4 + +#CHECK: vupllh %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0xd4 + +#CHECK: vupllh %v19, %v14 +0xe7 0x3e 0x00 0x00 0x18 0xd4 + +#CHECK: vupllh %v31, %v31 +0xe7 0xff 0x00 0x00 0x1c 0xd4 + +#CHECK: vx %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x6d + +#CHECK: vx %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x6d + +#CHECK: vx %v31, %v31, %v31 +0xe7 0xff 0xf0 0x00 0x0e 0x6d + +#CHECK: wcdgb %f0, %f0, 0, 0 +0xe7 0x00 0x00 0x08 0x30 0xc3 + +#CHECK: wcdgb %v19, %f14, 4, 10 +0xe7 0x3e 0x00 0xac 0x38 0xc3 + +#CHECK: wcdgb %v31, %v31, 7, 15 +0xe7 0xff 0x00 0xff 0x3c 0xc3 + +#CHECK: wcdlgb %f0, %f0, 0, 0 +0xe7 0x00 0x00 0x08 0x30 0xc1 + +#CHECK: wcdlgb %v19, %f14, 4, 10 +0xe7 0x3e 0x00 0xac 0x38 0xc1 + +#CHECK: wcdlgb %v31, %v31, 7, 15 +0xe7 0xff 0x00 0xff 0x3c 0xc1 + +#CHECK: wcgdb %f0, %f0, 0, 0 +0xe7 0x00 0x00 0x08 0x30 0xc2 + +#CHECK: wcgdb %v19, %f14, 4, 10 +0xe7 0x3e 0x00 0xac 0x38 0xc2 + +#CHECK: wcgdb %v31, %v31, 7, 15 +0xe7 0xff 0x00 0xff 0x3c 0xc2 + +#CHECK: wclgdb %f0, %f0, 0, 0 +0xe7 0x00 0x00 0x08 0x30 0xc0 + +#CHECK: wclgdb %v19, %f14, 4, 10 +0xe7 0x3e 0x00 0xac 0x38 0xc0 + +#CHECK: wclgdb %v31, %v31, 7, 15 +0xe7 0xff 0x00 0xff 0x3c 0xc0 + +#CHECK: wfadb %f0, %f0, %f0 +0xe7 0x00 0x00 0x08 0x30 0xe3 + +#CHECK: wfadb %v18, %f3, %v20 +0xe7 0x23 0x40 0x08 0x3a 0xe3 + +#CHECK: wfadb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x08 0x3e 0xe3 + +#CHECK: wfcdb %f0, %f0 +0xe7 0x00 0x00 0x00 0x30 0xcb + +#CHECK: wfcdb %v19, %f14 +0xe7 0x3e 0x00 0x00 0x38 0xcb + +#CHECK: wfcdb %v31, %v31 +0xe7 0xff 0x00 0x00 0x3c 0xcb + +#CHECK: wfcedb %f0, %f0, %f0 +0xe7 0x00 0x00 0x08 0x30 0xe8 + +#CHECK: wfcedb %v18, %f3, %v20 +0xe7 0x23 0x40 0x08 0x3a 0xe8 + +#CHECK: wfcedb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x08 0x3e 0xe8 + +#CHECK: wfcedbs %f0, %f0, %f0 +0xe7 0x00 0x00 0x18 0x30 0xe8 + +#CHECK: wfcedbs %v18, %f3, %v20 +0xe7 0x23 0x40 0x18 0x3a 0xe8 + +#CHECK: wfcedbs %v31, %v31, %v31 +0xe7 0xff 0xf0 0x18 0x3e 0xe8 + +#CHECK: wfchdb %f0, %f0, %f0 +0xe7 0x00 0x00 0x08 0x30 0xeb + +#CHECK: wfchdb %v18, %f3, %v20 +0xe7 0x23 0x40 0x08 0x3a 0xeb + +#CHECK: wfchdb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x08 0x3e 0xeb + +#CHECK: wfchdbs %f0, %f0, %f0 +0xe7 0x00 0x00 0x18 0x30 0xeb + +#CHECK: wfchdbs %v18, %f3, %v20 +0xe7 0x23 0x40 0x18 0x3a 0xeb + +#CHECK: wfchdbs %v31, %v31, %v31 +0xe7 0xff 0xf0 0x18 0x3e 0xeb + +#CHECK: wfchedb %f0, %f0, %f0 +0xe7 0x00 0x00 0x08 0x30 0xea + +#CHECK: wfchedb %v18, %f3, %v20 +0xe7 0x23 0x40 0x08 0x3a 0xea + +#CHECK: wfchedb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x08 0x3e 0xea + +#CHECK: wfchedbs %f0, %f0, %f0 +0xe7 0x00 0x00 0x18 0x30 0xea + +#CHECK: wfchedbs %v18, %f3, %v20 +0xe7 0x23 0x40 0x18 0x3a 0xea + +#CHECK: wfchedbs %v31, %v31, %v31 +0xe7 0xff 0xf0 0x18 0x3e 0xea + +#CHECK: wfddb %f0, %f0, %f0 +0xe7 0x00 0x00 0x08 0x30 0xe5 + +#CHECK: wfddb %v18, %f3, %v20 +0xe7 0x23 0x40 0x08 0x3a 0xe5 + +#CHECK: wfddb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x08 0x3e 0xe5 + +#CHECK: wfidb %f0, %f0, 0, 0 +0xe7 0x00 0x00 0x08 0x30 0xc7 + +#CHECK: wfidb %v19, %f14, 4, 10 +0xe7 0x3e 0x00 0xac 0x38 0xc7 + +#CHECK: wfidb %v31, %v31, 7, 15 +0xe7 0xff 0x00 0xff 0x3c 0xc7 + +#CHECK: wfkdb %f0, %f0 +0xe7 0x00 0x00 0x00 0x30 0xca + +#CHECK: wfkdb %v19, %f14 +0xe7 0x3e 0x00 0x00 0x38 0xca + +#CHECK: wfkdb %v31, %v31 +0xe7 0xff 0x00 0x00 0x3c 0xca + +#CHECK: wflcdb %f0, %f0 +0xe7 0x00 0x00 0x08 0x30 0xcc + +#CHECK: wflcdb %v19, %f14 +0xe7 0x3e 0x00 0x08 0x38 0xcc + +#CHECK: wflcdb %v31, %v31 +0xe7 0xff 0x00 0x08 0x3c 0xcc + +#CHECK: wflndb %f0, %f0 +0xe7 0x00 0x00 0x18 0x30 0xcc + +#CHECK: wflndb %v19, %f14 +0xe7 0x3e 0x00 0x18 0x38 0xcc + +#CHECK: wflndb %v31, %v31 +0xe7 0xff 0x00 0x18 0x3c 0xcc + +#CHECK: wflpdb %f0, %f0 +0xe7 0x00 0x00 0x28 0x30 0xcc + +#CHECK: wflpdb %v19, %f14 +0xe7 0x3e 0x00 0x28 0x38 0xcc + +#CHECK: wflpdb %v31, %v31 +0xe7 0xff 0x00 0x28 0x3c 0xcc + +#CHECK: wfmadb %f0, %f0, %f0, %f0 +0xe7 0x00 0x03 0x08 0x00 0x8f + +#CHECK: wfmadb %f3, %v20, %f5, %v22 +0xe7 0x34 0x53 0x08 0x65 0x8f + +#CHECK: wfmadb %v31, %v31, %v31, %v31 +0xe7 0xff 0xf3 0x08 0xff 0x8f + +#CHECK: wfmdb %f0, %f0, %f0 +0xe7 0x00 0x00 0x08 0x30 0xe7 + +#CHECK: wfmdb %v18, %f3, %v20 +0xe7 0x23 0x40 0x08 0x3a 0xe7 + +#CHECK: wfmdb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x08 0x3e 0xe7 + +#CHECK: wfmsdb %f0, %f0, %f0, %f0 +0xe7 0x00 0x03 0x08 0x00 0x8e + +#CHECK: wfmsdb %f3, %v20, %f5, %v22 +0xe7 0x34 0x53 0x08 0x65 0x8e + +#CHECK: wfmsdb %v31, %v31, %v31, %v31 +0xe7 0xff 0xf3 0x08 0xff 0x8e + +#CHECK: wfsdb %f0, %f0, %f0 +0xe7 0x00 0x00 0x08 0x30 0xe2 + +#CHECK: wfsdb %v18, %f3, %v20 +0xe7 0x23 0x40 0x08 0x3a 0xe2 + +#CHECK: wfsdb %v31, %v31, %v31 +0xe7 0xff 0xf0 0x08 0x3e 0xe2 + +#CHECK: wfsqdb %f0, %f0 +0xe7 0x00 0x00 0x08 0x30 0xce + +#CHECK: wfsqdb %v19, %f14 +0xe7 0x3e 0x00 0x08 0x38 0xce + +#CHECK: wfsqdb %v31, %v31 +0xe7 0xff 0x00 0x08 0x3c 0xce + +#CHECK: wftcidb %f0, %f0, 0 +0xe7 0x00 0x00 0x08 0x30 0x4a + +#CHECK: wftcidb %v19, %f4, 1383 +0xe7 0x34 0x56 0x78 0x38 0x4a + +#CHECK: wftcidb %v31, %v31, 4095 +0xe7 0xff 0xff 0xf8 0x3c 0x4a + +#CHECK: wldeb %f0, %f0 +0xe7 0x00 0x00 0x08 0x20 0xc4 + +#CHECK: wldeb %v19, %f14 +0xe7 0x3e 0x00 0x08 0x28 0xc4 + +#CHECK: wldeb %v31, %v31 +0xe7 0xff 0x00 0x08 0x2c 0xc4 + +#CHECK: wledb %f0, %f0, 0, 0 +0xe7 0x00 0x00 0x08 0x30 0xc5 + +#CHECK: wledb %v19, %f14, 4, 10 +0xe7 0x3e 0x00 0xac 0x38 0xc5 + +#CHECK: wledb %v31, %v31, 7, 15 +0xe7 0xff 0x00 0xff 0x3c 0xc5 diff --git a/llvm/test/MC/SystemZ/insn-bad-z13.s b/llvm/test/MC/SystemZ/insn-bad-z13.s new file mode 100644 index 00000000000..6468e3ae2ba --- /dev/null +++ b/llvm/test/MC/SystemZ/insn-bad-z13.s @@ -0,0 +1,1201 @@ +# For z13 only. +# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=z13 < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: lcbb %r0, 0, -1 +#CHECK: error: invalid operand +#CHECK: lcbb %r0, 0, 16 +#CHECK: error: invalid operand +#CHECK: lcbb %r0, -1, 0 +#CHECK: error: invalid operand +#CHECK: lcbb %r0, 4096, 0 +#CHECK: error: invalid use of vector addressing +#CHECK: lcbb %r0, 0(%v1,%r2), 0 + + lcbb %r0, 0, -1 + lcbb %r0, 0, 16 + lcbb %r0, -1, 0 + lcbb %r0, 4096, 0 + lcbb %r0, 0(%v1,%r2), 0 + +#CHECK: error: invalid operand +#CHECK: vcdgb %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vcdgb %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vcdgb %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vcdgb %v0, %v0, 16, 0 + + vcdgb %v0, %v0, 0, -1 + vcdgb %v0, %v0, 0, 16 + vcdgb %v0, %v0, -1, 0 + vcdgb %v0, %v0, 16, 0 + +#CHECK: error: invalid operand +#CHECK: vcdlgb %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vcdlgb %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vcdlgb %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vcdlgb %v0, %v0, 16, 0 + + vcdlgb %v0, %v0, 0, -1 + vcdlgb %v0, %v0, 0, 16 + vcdlgb %v0, %v0, -1, 0 + vcdlgb %v0, %v0, 16, 0 + +#CHECK: error: invalid operand +#CHECK: vcgdb %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vcgdb %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vcgdb %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vcgdb %v0, %v0, 16, 0 + + vcgdb %v0, %v0, 0, -1 + vcgdb %v0, %v0, 0, 16 + vcgdb %v0, %v0, -1, 0 + vcgdb %v0, %v0, 16, 0 + +#CHECK: error: invalid operand +#CHECK: vclgdb %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vclgdb %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vclgdb %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vclgdb %v0, %v0, 16, 0 + + vclgdb %v0, %v0, 0, -1 + vclgdb %v0, %v0, 0, 16 + vclgdb %v0, %v0, -1, 0 + vclgdb %v0, %v0, 16, 0 + +#CHECK: error: invalid operand +#CHECK: verimb %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: verimb %v0, %v0, %v0, 256 + + verimb %v0, %v0, %v0, -1 + verimb %v0, %v0, %v0, 256 + +#CHECK: error: invalid operand +#CHECK: verimf %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: verimf %v0, %v0, %v0, 256 + + verimf %v0, %v0, %v0, -1 + verimf %v0, %v0, %v0, 256 + +#CHECK: error: invalid operand +#CHECK: verimg %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: verimg %v0, %v0, %v0, 256 + + verimg %v0, %v0, %v0, -1 + verimg %v0, %v0, %v0, 256 + +#CHECK: error: invalid operand +#CHECK: verimh %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: verimh %v0, %v0, %v0, 256 + + verimh %v0, %v0, %v0, -1 + verimh %v0, %v0, %v0, 256 + +#CHECK: error: invalid operand +#CHECK: verllb %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: verllb %v0, %v0, 4096 + + verllb %v0, %v0, -1 + verllb %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: verllf %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: verllf %v0, %v0, 4096 + + verllf %v0, %v0, -1 + verllf %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: verllg %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: verllg %v0, %v0, 4096 + + verllg %v0, %v0, -1 + verllg %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: verllh %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: verllh %v0, %v0, 4096 + + verllh %v0, %v0, -1 + verllh %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: veslb %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: veslb %v0, %v0, 4096 + + veslb %v0, %v0, -1 + veslb %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: veslf %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: veslf %v0, %v0, 4096 + + veslf %v0, %v0, -1 + veslf %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: veslg %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: veslg %v0, %v0, 4096 + + veslg %v0, %v0, -1 + veslg %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: veslh %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: veslh %v0, %v0, 4096 + + veslh %v0, %v0, -1 + veslh %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: vesrab %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vesrab %v0, %v0, 4096 + + vesrab %v0, %v0, -1 + vesrab %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: vesraf %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vesraf %v0, %v0, 4096 + + vesraf %v0, %v0, -1 + vesraf %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: vesrag %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vesrag %v0, %v0, 4096 + + vesrag %v0, %v0, -1 + vesrag %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: vesrah %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vesrah %v0, %v0, 4096 + + vesrah %v0, %v0, -1 + vesrah %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: vesrlb %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vesrlb %v0, %v0, 4096 + + vesrlb %v0, %v0, -1 + vesrlb %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: vesrlf %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vesrlf %v0, %v0, 4096 + + vesrlf %v0, %v0, -1 + vesrlf %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: vesrlg %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vesrlg %v0, %v0, 4096 + + vesrlg %v0, %v0, -1 + vesrlg %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: vesrlh %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vesrlh %v0, %v0, 4096 + + vesrlh %v0, %v0, -1 + vesrlh %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: vfaeb %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vfaeb %v0, %v0, %v0, 16 +#CHECK: error: too few operands +#CHECK: vfaeb %v0, %v0 +#CHECK: error: invalid operand +#CHECK: vfaeb %v0, %v0, %v0, 0, 0 + + vfaeb %v0, %v0, %v0, -1 + vfaeb %v0, %v0, %v0, 16 + vfaeb %v0, %v0 + vfaeb %v0, %v0, %v0, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vfaebs %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vfaebs %v0, %v0, %v0, 16 +#CHECK: error: too few operands +#CHECK: vfaebs %v0, %v0 +#CHECK: error: invalid operand +#CHECK: vfaebs %v0, %v0, %v0, 0, 0 + + vfaebs %v0, %v0, %v0, -1 + vfaebs %v0, %v0, %v0, 16 + vfaebs %v0, %v0 + vfaebs %v0, %v0, %v0, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vfaef %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vfaef %v0, %v0, %v0, 16 +#CHECK: error: too few operands +#CHECK: vfaef %v0, %v0 +#CHECK: error: invalid operand +#CHECK: vfaef %v0, %v0, %v0, 0, 0 + + vfaef %v0, %v0, %v0, -1 + vfaef %v0, %v0, %v0, 16 + vfaef %v0, %v0 + vfaef %v0, %v0, %v0, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vfaeh %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vfaeh %v0, %v0, %v0, 16 +#CHECK: error: too few operands +#CHECK: vfaeh %v0, %v0 +#CHECK: error: invalid operand +#CHECK: vfaeh %v0, %v0, %v0, 0, 0 + + vfaeh %v0, %v0, %v0, -1 + vfaeh %v0, %v0, %v0, 16 + vfaeh %v0, %v0 + vfaeh %v0, %v0, %v0, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vfaezh %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vfaezh %v0, %v0, %v0, 16 +#CHECK: error: too few operands +#CHECK: vfaezh %v0, %v0 +#CHECK: error: invalid operand +#CHECK: vfaezh %v0, %v0, %v0, 0, 0 + + vfaezh %v0, %v0, %v0, -1 + vfaezh %v0, %v0, %v0, 16 + vfaezh %v0, %v0 + vfaezh %v0, %v0, %v0, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vfaezfs %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vfaezfs %v0, %v0, %v0, 16 +#CHECK: error: too few operands +#CHECK: vfaezfs %v0, %v0 +#CHECK: error: invalid operand +#CHECK: vfaezfs %v0, %v0, %v0, 0, 0 + + vfaezfs %v0, %v0, %v0, -1 + vfaezfs %v0, %v0, %v0, 16 + vfaezfs %v0, %v0 + vfaezfs %v0, %v0, %v0, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vfidb %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vfidb %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vfidb %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vfidb %v0, %v0, 16, 0 + + vfidb %v0, %v0, 0, -1 + vfidb %v0, %v0, 0, 16 + vfidb %v0, %v0, -1, 0 + vfidb %v0, %v0, 16, 0 + +#CHECK: error: invalid operand +#CHECK: vftcidb %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vftcidb %v0, %v0, 4096 + + vftcidb %v0, %v0, -1 + vftcidb %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: vgbm %v0, -1 +#CHECK: error: invalid operand +#CHECK: vgbm %v0, 0x10000 + + vgbm %v0, -1 + vgbm %v0, 0x10000 + +#CHECK: error: vector index required +#CHECK: vgef %v0, 0(%r1), 0 +#CHECK: error: vector index required +#CHECK: vgef %v0, 0(%r2,%r1), 0 +#CHECK: error: invalid operand +#CHECK: vgef %v0, 0(%v0,%r1), -1 +#CHECK: error: invalid operand +#CHECK: vgef %v0, 0(%v0,%r1), 4 +#CHECK: error: invalid operand +#CHECK: vgef %v0, -1(%v0,%r1), 0 +#CHECK: error: invalid operand +#CHECK: vgef %v0, 4096(%v0,%r1), 0 + + vgef %v0, 0(%r1), 0 + vgef %v0, 0(%r2,%r1), 0 + vgef %v0, 0(%v0,%r1), -1 + vgef %v0, 0(%v0,%r1), 4 + vgef %v0, -1(%v0,%r1), 0 + vgef %v0, 4096(%v0,%r1), 0 + +#CHECK: error: vector index required +#CHECK: vgeg %v0, 0(%r1), 0 +#CHECK: error: vector index required +#CHECK: vgeg %v0, 0(%r2,%r1), 0 +#CHECK: error: invalid operand +#CHECK: vgeg %v0, 0(%v0,%r1), -1 +#CHECK: error: invalid operand +#CHECK: vgeg %v0, 0(%v0,%r1), 2 +#CHECK: error: invalid operand +#CHECK: vgeg %v0, -1(%v0,%r1), 0 +#CHECK: error: invalid operand +#CHECK: vgeg %v0, 4096(%v0,%r1), 0 + + vgeg %v0, 0(%r1), 0 + vgeg %v0, 0(%r2,%r1), 0 + vgeg %v0, 0(%v0,%r1), -1 + vgeg %v0, 0(%v0,%r1), 2 + vgeg %v0, -1(%v0,%r1), 0 + vgeg %v0, 4096(%v0,%r1), 0 + +#CHECK: error: invalid operand +#CHECK: vgmb %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vgmb %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vgmb %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vgmb %v0, 256, 0 + + vgmb %v0, 0, -1 + vgmb %v0, 0, -1 + vgmb %v0, -1, 0 + vgmb %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vgmf %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vgmf %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vgmf %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vgmf %v0, 256, 0 + + vgmf %v0, 0, -1 + vgmf %v0, 0, -1 + vgmf %v0, -1, 0 + vgmf %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vgmg %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vgmg %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vgmg %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vgmg %v0, 256, 0 + + vgmg %v0, 0, -1 + vgmg %v0, 0, -1 + vgmg %v0, -1, 0 + vgmg %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vgmh %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vgmh %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vgmh %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vgmh %v0, 256, 0 + + vgmh %v0, 0, -1 + vgmh %v0, 0, -1 + vgmh %v0, -1, 0 + vgmh %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vl %v0, -1 +#CHECK: error: invalid operand +#CHECK: vl %v0, 4096 +#CHECK: error: invalid use of vector addressing +#CHECK: vl %v0, 0(%v1,%r2) + + vl %v0, -1 + vl %v0, 4096 + vl %v0, 0(%v1,%r2) + +#CHECK: error: invalid operand +#CHECK: vlbb %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vlbb %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vlbb %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vlbb %v0, 4096, 0 +#CHECK: error: invalid use of vector addressing +#CHECK: vlbb %v0, 0(%v1,%r2), 0 + + vlbb %v0, 0, -1 + vlbb %v0, 0, 16 + vlbb %v0, -1, 0 + vlbb %v0, 4096, 0 + vlbb %v0, 0(%v1,%r2), 0 + +#CHECK: error: invalid operand +#CHECK: vleb %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vleb %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vleb %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vleb %v0, 4096, 0 +#CHECK: error: invalid use of vector addressing +#CHECK: vleb %v0, 0(%v1,%r2), 0 + + vleb %v0, 0, -1 + vleb %v0, 0, 16 + vleb %v0, -1, 0 + vleb %v0, 4096, 0 + vleb %v0, 0(%v1,%r2), 0 + +#CHECK: error: invalid operand +#CHECK: vledb %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vledb %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vledb %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vledb %v0, %v0, 16, 0 + + vledb %v0, %v0, 0, -1 + vledb %v0, %v0, 0, 16 + vledb %v0, %v0, -1, 0 + vledb %v0, %v0, 16, 0 + +#CHECK: error: invalid operand +#CHECK: vlef %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vlef %v0, 0, 4 +#CHECK: error: invalid operand +#CHECK: vlef %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vlef %v0, 4096, 0 +#CHECK: error: invalid use of vector addressing +#CHECK: vlef %v0, 0(%v1,%r2), 0 + + vlef %v0, 0, -1 + vlef %v0, 0, 4 + vlef %v0, -1, 0 + vlef %v0, 4096, 0 + vlef %v0, 0(%v1,%r2), 0 + +#CHECK: error: invalid operand +#CHECK: vleg %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vleg %v0, 0, 2 +#CHECK: error: invalid operand +#CHECK: vleg %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vleg %v0, 4096, 0 +#CHECK: error: invalid use of vector addressing +#CHECK: vleg %v0, 0(%v1,%r2), 0 + + vleg %v0, 0, -1 + vleg %v0, 0, 2 + vleg %v0, -1, 0 + vleg %v0, 4096, 0 + vleg %v0, 0(%v1,%r2), 0 + +#CHECK: error: invalid operand +#CHECK: vleh %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vleh %v0, 0, 8 +#CHECK: error: invalid operand +#CHECK: vleh %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vleh %v0, 4096, 0 +#CHECK: error: invalid use of vector addressing +#CHECK: vleh %v0, 0(%v1,%r2), 0 + + vleh %v0, 0, -1 + vleh %v0, 0, 8 + vleh %v0, -1, 0 + vleh %v0, 4096, 0 + vleh %v0, 0(%v1,%r2), 0 + +#CHECK: error: invalid operand +#CHECK: vleib %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vleib %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vleib %v0, -32769, 0 +#CHECK: error: invalid operand +#CHECK: vleib %v0, 32768, 0 + + vleib %v0, 0, -1 + vleib %v0, 0, 16 + vleib %v0, -32769, 0 + vleib %v0, 32768, 0 + +#CHECK: error: invalid operand +#CHECK: vleif %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vleif %v0, 0, 4 +#CHECK: error: invalid operand +#CHECK: vleif %v0, -32769, 0 +#CHECK: error: invalid operand +#CHECK: vleif %v0, 32768, 0 + + vleif %v0, 0, -1 + vleif %v0, 0, 4 + vleif %v0, -32769, 0 + vleif %v0, 32768, 0 + +#CHECK: error: invalid operand +#CHECK: vleig %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vleig %v0, 0, 2 +#CHECK: error: invalid operand +#CHECK: vleig %v0, -32769, 0 +#CHECK: error: invalid operand +#CHECK: vleig %v0, 32768, 0 + + vleig %v0, 0, -1 + vleig %v0, 0, 2 + vleig %v0, -32769, 0 + vleig %v0, 32768, 0 + +#CHECK: error: invalid operand +#CHECK: vleih %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vleih %v0, 0, 8 +#CHECK: error: invalid operand +#CHECK: vleih %v0, -32769, 0 +#CHECK: error: invalid operand +#CHECK: vleih %v0, 32768, 0 + + vleih %v0, 0, -1 + vleih %v0, 0, 8 + vleih %v0, -32769, 0 + vleih %v0, 32768, 0 + +#CHECK: error: invalid operand +#CHECK: vlgvb %r0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vlgvb %r0, %v0, 4096 +#CHECK: error: %r0 used in an address +#CHECK: vlgvb %r0, %v0, 0(%r0) + + vlgvb %r0, %v0, -1 + vlgvb %r0, %v0, 4096 + vlgvb %r0, %v0, 0(%r0) + +#CHECK: error: invalid operand +#CHECK: vlgvf %r0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vlgvf %r0, %v0, 4096 +#CHECK: error: %r0 used in an address +#CHECK: vlgvf %r0, %v0, 0(%r0) + + vlgvf %r0, %v0, -1 + vlgvf %r0, %v0, 4096 + vlgvf %r0, %v0, 0(%r0) + +#CHECK: error: invalid operand +#CHECK: vlgvg %r0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vlgvg %r0, %v0, 4096 +#CHECK: error: %r0 used in an address +#CHECK: vlgvg %r0, %v0, 0(%r0) + + vlgvg %r0, %v0, -1 + vlgvg %r0, %v0, 4096 + vlgvg %r0, %v0, 0(%r0) + +#CHECK: error: invalid operand +#CHECK: vlgvh %r0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vlgvh %r0, %v0, 4096 +#CHECK: error: %r0 used in an address +#CHECK: vlgvh %r0, %v0, 0(%r0) + + vlgvh %r0, %v0, -1 + vlgvh %r0, %v0, 4096 + vlgvh %r0, %v0, 0(%r0) + +#CHECK: error: invalid operand +#CHECK: vll %v0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: vll %v0, %r0, 4096 +#CHECK: error: %r0 used in an address +#CHECK: vll %v0, %r0, 0(%r0) + + vll %v0, %r0, -1 + vll %v0, %r0, 4096 + vll %v0, %r0, 0(%r0) + +#CHECK: error: invalid operand +#CHECK: vllezb %v0, -1 +#CHECK: error: invalid operand +#CHECK: vllezb %v0, 4096 +#CHECK: error: invalid use of vector addressing +#CHECK: vllezb %v0, 0(%v1,%r2) + + vllezb %v0, -1 + vllezb %v0, 4096 + vllezb %v0, 0(%v1,%r2) + +#CHECK: error: invalid operand +#CHECK: vllezf %v0, -1 +#CHECK: error: invalid operand +#CHECK: vllezf %v0, 4096 +#CHECK: error: invalid use of vector addressing +#CHECK: vllezf %v0, 0(%v1,%r2) + + vllezf %v0, -1 + vllezf %v0, 4096 + vllezf %v0, 0(%v1,%r2) + +#CHECK: error: invalid operand +#CHECK: vllezg %v0, -1 +#CHECK: error: invalid operand +#CHECK: vllezg %v0, 4096 +#CHECK: error: invalid use of vector addressing +#CHECK: vllezg %v0, 0(%v1,%r2) + + vllezg %v0, -1 + vllezg %v0, 4096 + vllezg %v0, 0(%v1,%r2) + +#CHECK: error: invalid operand +#CHECK: vllezh %v0, -1 +#CHECK: error: invalid operand +#CHECK: vllezh %v0, 4096 +#CHECK: error: invalid use of vector addressing +#CHECK: vllezh %v0, 0(%v1,%r2) + + vllezh %v0, -1 + vllezh %v0, 4096 + vllezh %v0, 0(%v1,%r2) + +#CHECK: error: invalid operand +#CHECK: vlm %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vlm %v0, %v0, 4096 + + vlm %v0, %v0, -1 + vlm %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: vlrepb %v0, -1 +#CHECK: error: invalid operand +#CHECK: vlrepb %v0, 4096 +#CHECK: error: invalid use of vector addressing +#CHECK: vlrepb %v0, 0(%v1,%r2) + + vlrepb %v0, -1 + vlrepb %v0, 4096 + vlrepb %v0, 0(%v1,%r2) + +#CHECK: error: invalid operand +#CHECK: vlrepf %v0, -1 +#CHECK: error: invalid operand +#CHECK: vlrepf %v0, 4096 +#CHECK: error: invalid use of vector addressing +#CHECK: vlrepf %v0, 0(%v1,%r2) + + vlrepf %v0, -1 + vlrepf %v0, 4096 + vlrepf %v0, 0(%v1,%r2) + +#CHECK: error: invalid operand +#CHECK: vlrepg %v0, -1 +#CHECK: error: invalid operand +#CHECK: vlrepg %v0, 4096 +#CHECK: error: invalid use of vector addressing +#CHECK: vlrepg %v0, 0(%v1,%r2) + + vlrepg %v0, -1 + vlrepg %v0, 4096 + vlrepg %v0, 0(%v1,%r2) + +#CHECK: error: invalid operand +#CHECK: vlreph %v0, -1 +#CHECK: error: invalid operand +#CHECK: vlreph %v0, 4096 +#CHECK: error: invalid use of vector addressing +#CHECK: vlreph %v0, 0(%v1,%r2) + + vlreph %v0, -1 + vlreph %v0, 4096 + vlreph %v0, 0(%v1,%r2) + +#CHECK: error: invalid operand +#CHECK: vlvgb %v0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: vlvgb %v0, %r0, 4096 +#CHECK: error: %r0 used in an address +#CHECK: vlvgb %v0, %r0, 0(%r0) + + vlvgb %v0, %r0, -1 + vlvgb %v0, %r0, 4096 + vlvgb %v0, %r0, 0(%r0) + +#CHECK: error: invalid operand +#CHECK: vlvgf %v0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: vlvgf %v0, %r0, 4096 +#CHECK: error: %r0 used in an address +#CHECK: vlvgf %v0, %r0, 0(%r0) + + vlvgf %v0, %r0, -1 + vlvgf %v0, %r0, 4096 + vlvgf %v0, %r0, 0(%r0) + +#CHECK: error: invalid operand +#CHECK: vlvgg %v0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: vlvgg %v0, %r0, 4096 +#CHECK: error: %r0 used in an address +#CHECK: vlvgg %v0, %r0, 0(%r0) + + vlvgg %v0, %r0, -1 + vlvgg %v0, %r0, 4096 + vlvgg %v0, %r0, 0(%r0) + +#CHECK: error: invalid operand +#CHECK: vlvgh %v0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: vlvgh %v0, %r0, 4096 +#CHECK: error: %r0 used in an address +#CHECK: vlvgh %v0, %r0, 0(%r0) + + vlvgh %v0, %r0, -1 + vlvgh %v0, %r0, 4096 + vlvgh %v0, %r0, 0(%r0) + +#CHECK: error: invalid operand +#CHECK: vpdi %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vpdi %v0, %v0, %v0, 16 + + vpdi %v0, %v0, %v0, -1 + vpdi %v0, %v0, %v0, 16 + +#CHECK: error: invalid operand +#CHECK: vrepb %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vrepb %v0, %v0, 65536 + + vrepb %v0, %v0, -1 + vrepb %v0, %v0, 65536 + +#CHECK: error: invalid operand +#CHECK: vrepf %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vrepf %v0, %v0, 65536 + + vrepf %v0, %v0, -1 + vrepf %v0, %v0, 65536 + +#CHECK: error: invalid operand +#CHECK: vrepg %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vrepg %v0, %v0, 65536 + + vrepg %v0, %v0, -1 + vrepg %v0, %v0, 65536 + +#CHECK: error: invalid operand +#CHECK: vreph %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vreph %v0, %v0, 65536 + + vreph %v0, %v0, -1 + vreph %v0, %v0, 65536 + +#CHECK: error: invalid operand +#CHECK: vrepib %v0, -32769 +#CHECK: error: invalid operand +#CHECK: vrepib %v0, 32768 + + vrepib %v0, -32769 + vrepib %v0, 32768 + +#CHECK: error: invalid operand +#CHECK: vrepif %v0, -32769 +#CHECK: error: invalid operand +#CHECK: vrepif %v0, 32768 + + vrepif %v0, -32769 + vrepif %v0, 32768 + +#CHECK: error: invalid operand +#CHECK: vrepig %v0, -32769 +#CHECK: error: invalid operand +#CHECK: vrepig %v0, 32768 + + vrepig %v0, -32769 + vrepig %v0, 32768 + +#CHECK: error: invalid operand +#CHECK: vrepih %v0, -32769 +#CHECK: error: invalid operand +#CHECK: vrepih %v0, 32768 + + vrepih %v0, -32769 + vrepih %v0, 32768 + +#CHECK: error: vector index required +#CHECK: vscef %v0, 0(%r1), 0 +#CHECK: error: vector index required +#CHECK: vscef %v0, 0(%r2,%r1), 0 +#CHECK: error: invalid operand +#CHECK: vscef %v0, 0(%v0,%r1), -1 +#CHECK: error: invalid operand +#CHECK: vscef %v0, 0(%v0,%r1), 4 +#CHECK: error: invalid operand +#CHECK: vscef %v0, -1(%v0,%r1), 0 +#CHECK: error: invalid operand +#CHECK: vscef %v0, 4096(%v0,%r1), 0 + + vscef %v0, 0(%r1), 0 + vscef %v0, 0(%r2,%r1), 0 + vscef %v0, 0(%v0,%r1), -1 + vscef %v0, 0(%v0,%r1), 4 + vscef %v0, -1(%v0,%r1), 0 + vscef %v0, 4096(%v0,%r1), 0 + +#CHECK: error: vector index required +#CHECK: vsceg %v0, 0(%r1), 0 +#CHECK: error: vector index required +#CHECK: vsceg %v0, 0(%r2,%r1), 0 +#CHECK: error: invalid operand +#CHECK: vsceg %v0, 0(%v0,%r1), -1 +#CHECK: error: invalid operand +#CHECK: vsceg %v0, 0(%v0,%r1), 2 +#CHECK: error: invalid operand +#CHECK: vsceg %v0, -1(%v0,%r1), 0 +#CHECK: error: invalid operand +#CHECK: vsceg %v0, 4096(%v0,%r1), 0 + + vsceg %v0, 0(%r1), 0 + vsceg %v0, 0(%r2,%r1), 0 + vsceg %v0, 0(%v0,%r1), -1 + vsceg %v0, 0(%v0,%r1), 2 + vsceg %v0, -1(%v0,%r1), 0 + vsceg %v0, 4096(%v0,%r1), 0 + +#CHECK: error: invalid operand +#CHECK: vsldb %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vsldb %v0, %v0, %v0, 256 + + vsldb %v0, %v0, %v0, -1 + vsldb %v0, %v0, %v0, 256 + +#CHECK: error: invalid operand +#CHECK: vst %v0, -1 +#CHECK: error: invalid operand +#CHECK: vst %v0, 4096 +#CHECK: error: invalid use of vector addressing +#CHECK: vst %v0, 0(%v1,%r2) + + vst %v0, -1 + vst %v0, 4096 + vst %v0, 0(%v1,%r2) + +#CHECK: error: invalid operand +#CHECK: vsteb %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vsteb %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vsteb %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vsteb %v0, 4096, 0 +#CHECK: error: invalid use of vector addressing +#CHECK: vsteb %v0, 0(%v1,%r2), 0 + + vsteb %v0, 0, -1 + vsteb %v0, 0, 16 + vsteb %v0, -1, 0 + vsteb %v0, 4096, 0 + vsteb %v0, 0(%v1,%r2), 0 + +#CHECK: error: invalid operand +#CHECK: vstef %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vstef %v0, 0, 4 +#CHECK: error: invalid operand +#CHECK: vstef %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vstef %v0, 4096, 0 +#CHECK: error: invalid use of vector addressing +#CHECK: vstef %v0, 0(%v1,%r2), 0 + + vstef %v0, 0, -1 + vstef %v0, 0, 4 + vstef %v0, -1, 0 + vstef %v0, 4096, 0 + vstef %v0, 0(%v1,%r2), 0 + +#CHECK: error: invalid operand +#CHECK: vsteg %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vsteg %v0, 0, 2 +#CHECK: error: invalid operand +#CHECK: vsteg %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vsteg %v0, 4096, 0 +#CHECK: error: invalid use of vector addressing +#CHECK: vsteg %v0, 0(%v1,%r2), 0 + + vsteg %v0, 0, -1 + vsteg %v0, 0, 2 + vsteg %v0, -1, 0 + vsteg %v0, 4096, 0 + vsteg %v0, 0(%v1,%r2), 0 + +#CHECK: error: invalid operand +#CHECK: vsteh %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vsteh %v0, 0, 8 +#CHECK: error: invalid operand +#CHECK: vsteh %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vsteh %v0, 4096, 0 +#CHECK: error: invalid use of vector addressing +#CHECK: vsteh %v0, 0(%v1,%r2), 0 + + vsteh %v0, 0, -1 + vsteh %v0, 0, 8 + vsteh %v0, -1, 0 + vsteh %v0, 4096, 0 + vsteh %v0, 0(%v1,%r2), 0 + +#CHECK: error: invalid operand +#CHECK: vstl %v0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: vstl %v0, %r0, 4096 +#CHECK: error: %r0 used in an address +#CHECK: vstl %v0, %r0, 0(%r0) + + vstl %v0, %r0, -1 + vstl %v0, %r0, 4096 + vstl %v0, %r0, 0(%r0) + +#CHECK: error: invalid operand +#CHECK: vstm %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vstm %v0, %v0, 4096 + + vstm %v0, %v0, -1 + vstm %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: vstrcb %v0, %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vstrcb %v0, %v0, %v0, %v0, 16 +#CHECK: error: too few operands +#CHECK: vstrcb %v0, %v0, %v0 +#CHECK: error: invalid operand +#CHECK: vstrcb %v0, %v0, %v0, %v0, 0, 0 + + vstrcb %v0, %v0, %v0, %v0, -1 + vstrcb %v0, %v0, %v0, %v0, 16 + vstrcb %v0, %v0, %v0 + vstrcb %v0, %v0, %v0, %v0, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vstrcbs %v0, %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vstrcbs %v0, %v0, %v0, %v0, 16 +#CHECK: error: too few operands +#CHECK: vstrcbs %v0, %v0, %v0 +#CHECK: error: invalid operand +#CHECK: vstrcbs %v0, %v0, %v0, %v0, 0, 0 + + vstrcbs %v0, %v0, %v0, %v0, -1 + vstrcbs %v0, %v0, %v0, %v0, 16 + vstrcbs %v0, %v0, %v0 + vstrcbs %v0, %v0, %v0, %v0, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vstrcf %v0, %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vstrcf %v0, %v0, %v0, %v0, 16 +#CHECK: error: too few operands +#CHECK: vstrcf %v0, %v0, %v0 +#CHECK: error: invalid operand +#CHECK: vstrcf %v0, %v0, %v0, %v0, 0, 0 + + vstrcf %v0, %v0, %v0, %v0, -1 + vstrcf %v0, %v0, %v0, %v0, 16 + vstrcf %v0, %v0, %v0 + vstrcf %v0, %v0, %v0, %v0, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vstrch %v0, %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vstrch %v0, %v0, %v0, %v0, 16 +#CHECK: error: too few operands +#CHECK: vstrch %v0, %v0, %v0 +#CHECK: error: invalid operand +#CHECK: vstrch %v0, %v0, %v0, %v0, 0, 0 + + vstrch %v0, %v0, %v0, %v0, -1 + vstrch %v0, %v0, %v0, %v0, 16 + vstrch %v0, %v0, %v0 + vstrch %v0, %v0, %v0, %v0, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vstrczh %v0, %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vstrczh %v0, %v0, %v0, %v0, 16 +#CHECK: error: too few operands +#CHECK: vstrczh %v0, %v0, %v0 +#CHECK: error: invalid operand +#CHECK: vstrczh %v0, %v0, %v0, %v0, 0, 0 + + vstrczh %v0, %v0, %v0, %v0, -1 + vstrczh %v0, %v0, %v0, %v0, 16 + vstrczh %v0, %v0, %v0 + vstrczh %v0, %v0, %v0, %v0, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vstrczfs %v0, %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vstrczfs %v0, %v0, %v0, %v0, 16 +#CHECK: error: too few operands +#CHECK: vstrczfs %v0, %v0, %v0 +#CHECK: error: invalid operand +#CHECK: vstrczfs %v0, %v0, %v0, %v0, 0, 0 + + vstrczfs %v0, %v0, %v0, %v0, -1 + vstrczfs %v0, %v0, %v0, %v0, 16 + vstrczfs %v0, %v0, %v0 + vstrczfs %v0, %v0, %v0, %v0, 0, 0 + +#CHECK: error: invalid operand +#CHECK: wcdgb %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: wcdgb %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: wcdgb %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: wcdgb %v0, %v0, 16, 0 + + wcdgb %v0, %v0, 0, -1 + wcdgb %v0, %v0, 0, 16 + wcdgb %v0, %v0, -1, 0 + wcdgb %v0, %v0, 16, 0 + +#CHECK: error: invalid operand +#CHECK: wcdlgb %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: wcdlgb %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: wcdlgb %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: wcdlgb %v0, %v0, 16, 0 + + wcdlgb %v0, %v0, 0, -1 + wcdlgb %v0, %v0, 0, 16 + wcdlgb %v0, %v0, -1, 0 + wcdlgb %v0, %v0, 16, 0 + +#CHECK: error: invalid operand +#CHECK: wcgdb %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: wcgdb %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: wcgdb %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: wcgdb %v0, %v0, 16, 0 + + wcgdb %v0, %v0, 0, -1 + wcgdb %v0, %v0, 0, 16 + wcgdb %v0, %v0, -1, 0 + wcgdb %v0, %v0, 16, 0 + +#CHECK: error: invalid operand +#CHECK: wclgdb %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: wclgdb %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: wclgdb %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: wclgdb %v0, %v0, 16, 0 + + wclgdb %v0, %v0, 0, -1 + wclgdb %v0, %v0, 0, 16 + wclgdb %v0, %v0, -1, 0 + wclgdb %v0, %v0, 16, 0 + +#CHECK: error: invalid operand +#CHECK: wfidb %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: wfidb %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: wfidb %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: wfidb %v0, %v0, 16, 0 + + wfidb %v0, %v0, 0, -1 + wfidb %v0, %v0, 0, 16 + wfidb %v0, %v0, -1, 0 + wfidb %v0, %v0, 16, 0 + +#CHECK: error: invalid operand +#CHECK: wftcidb %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: wftcidb %v0, %v0, 4096 + + wftcidb %v0, %v0, -1 + wftcidb %v0, %v0, 4096 + +#CHECK: error: invalid operand +#CHECK: wledb %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: wledb %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: wledb %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: wledb %v0, %v0, 16, 0 + + wledb %v0, %v0, 0, -1 + wledb %v0, %v0, 0, 16 + wledb %v0, %v0, -1, 0 + wledb %v0, %v0, 16, 0 diff --git a/llvm/test/MC/SystemZ/insn-bad-zEC12.s b/llvm/test/MC/SystemZ/insn-bad-zEC12.s index d96e35d885b..ee31f5707af 100644 --- a/llvm/test/MC/SystemZ/insn-bad-zEC12.s +++ b/llvm/test/MC/SystemZ/insn-bad-zEC12.s @@ -2,6 +2,11 @@ # RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 < %s 2> %t # RUN: FileCheck < %t %s +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: lcbb %r0, 0, 0 + + lcbb %r0, 0, 0 + #CHECK: error: invalid operand #CHECK: ntstg %r0, -524289 #CHECK: error: invalid operand @@ -82,3 +87,1492 @@ tbeginc 0(%r1,%r2), 0 tbeginc 0, -1 tbeginc 0, 65536 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vab %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vaf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vag %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vah %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vaq %v0, %v0, %v0 + + vab %v0, %v0, %v0 + vaf %v0, %v0, %v0 + vag %v0, %v0, %v0 + vah %v0, %v0, %v0 + vaq %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vaccb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vaccf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vaccg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vacch %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vaccq %v0, %v0, %v0 + + vaccb %v0, %v0, %v0 + vaccf %v0, %v0, %v0 + vaccg %v0, %v0, %v0 + vacch %v0, %v0, %v0 + vaccq %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vacccq %v0, %v0, %v0 + + vacccq %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vacq %v0, %v0, %v0 + + vacq %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vavgb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vavgf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vavgg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vavgh %v0, %v0, %v0 + + vavgb %v0, %v0, %v0 + vavgf %v0, %v0, %v0 + vavgg %v0, %v0, %v0 + vavgh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vavglb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vavglf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vavglg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vavglh %v0, %v0, %v0 + + vavglb %v0, %v0, %v0 + vavglf %v0, %v0, %v0 + vavglg %v0, %v0, %v0 + vavglh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vcdgb %v0, %v0, 0, 0 + + vcdgb %v0, %v0, 0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vcdlgb %v0, %v0, 0, 0 + + vcdlgb %v0, %v0, 0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vceqb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vceqf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vceqg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vceqh %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vceqbs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vceqhs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vceqfs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vceqgs %v0, %v0, %v0 + + vceqb %v0, %v0, %v0 + vceqf %v0, %v0, %v0 + vceqg %v0, %v0, %v0 + vceqh %v0, %v0, %v0 + vceqbs %v0, %v0, %v0 + vceqhs %v0, %v0, %v0 + vceqfs %v0, %v0, %v0 + vceqgs %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vcgdb %v0, %v0, 0, 0 + + vcgdb %v0, %v0, 0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vchb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vchf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vchg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vchh %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vchbs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vchhs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vchfs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vchgs %v0, %v0, %v0 + + vchb %v0, %v0, %v0 + vchf %v0, %v0, %v0 + vchg %v0, %v0, %v0 + vchh %v0, %v0, %v0 + vchbs %v0, %v0, %v0 + vchhs %v0, %v0, %v0 + vchfs %v0, %v0, %v0 + vchgs %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vchlb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vchlf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vchlg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vchlh %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vchlbs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vchlhs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vchlfs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vchlgs %v0, %v0, %v0 + + vchlb %v0, %v0, %v0 + vchlf %v0, %v0, %v0 + vchlg %v0, %v0, %v0 + vchlh %v0, %v0, %v0 + vchlbs %v0, %v0, %v0 + vchlhs %v0, %v0, %v0 + vchlfs %v0, %v0, %v0 + vchlgs %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vcksm %v0, %v0, %v0 + + vcksm %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vclgdb %v0, %v0, 0, 0 + + vclgdb %v0, %v0, 0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vclzb %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vclzf %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vclzg %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vclzh %v0, %v0 + + vclzb %v0, %v0 + vclzf %v0, %v0 + vclzg %v0, %v0 + vclzh %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vctzb %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vctzf %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vctzg %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vctzh %v0, %v0 + + vctzb %v0, %v0 + vctzf %v0, %v0 + vctzg %v0, %v0 + vctzh %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vecb %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vecf %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vecg %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vech %v0, %v0 + + vecb %v0, %v0 + vecf %v0, %v0 + vecg %v0, %v0 + vech %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: verimb %v0, %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: verimf %v0, %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: verimg %v0, %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: verimh %v0, %v0, %v0, 0 + + verimb %v0, %v0, %v0, 0 + verimf %v0, %v0, %v0, 0 + verimg %v0, %v0, %v0, 0 + verimh %v0, %v0, %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: veclb %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: veclf %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: veclg %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: veclh %v0, %v0 + + veclb %v0, %v0 + veclf %v0, %v0 + veclg %v0, %v0 + veclh %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: verllvb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: verllvf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: verllvg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: verllvh %v0, %v0, %v0 + + verllvb %v0, %v0, %v0 + verllvf %v0, %v0, %v0 + verllvg %v0, %v0, %v0 + verllvh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: verllb %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: verllf %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: verllg %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: verllh %v0, %v0, 0 + + verllb %v0, %v0, 0 + verllf %v0, %v0, 0 + verllg %v0, %v0, 0 + verllh %v0, %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: veslvb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: veslvf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: veslvg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: veslvh %v0, %v0, %v0 + + veslvb %v0, %v0, %v0 + veslvf %v0, %v0, %v0 + veslvg %v0, %v0, %v0 + veslvh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: veslb %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: veslf %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: veslg %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: veslh %v0, %v0, 0 + + veslb %v0, %v0, 0 + veslf %v0, %v0, 0 + veslg %v0, %v0, 0 + veslh %v0, %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vesravb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vesravf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vesravg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vesravh %v0, %v0, %v0 + + vesravb %v0, %v0, %v0 + vesravf %v0, %v0, %v0 + vesravg %v0, %v0, %v0 + vesravh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vesrab %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vesraf %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vesrag %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vesrah %v0, %v0, 0 + + vesrab %v0, %v0, 0 + vesraf %v0, %v0, 0 + vesrag %v0, %v0, 0 + vesrah %v0, %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vesrlvb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vesrlvf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vesrlvg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vesrlvh %v0, %v0, %v0 + + vesrlvb %v0, %v0, %v0 + vesrlvf %v0, %v0, %v0 + vesrlvg %v0, %v0, %v0 + vesrlvh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vesrlb %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vesrlf %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vesrlg %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vesrlh %v0, %v0, 0 + + vesrlb %v0, %v0, 0 + vesrlf %v0, %v0, 0 + vesrlg %v0, %v0, 0 + vesrlh %v0, %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfadb %v0, %v0, %v0 + + vfadb %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfcedb %v0, %v0, %v0 +#CHECK: vfcedbs %v0, %v0, %v0 + + vfcedb %v0, %v0, %v0 + vfcedbs %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfchdb %v0, %v0, %v0 +#CHECK: vfchdbs %v0, %v0, %v0 + + vfchdb %v0, %v0, %v0 + vfchdbs %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfddb %v0, %v0, %v0 + + vfddb %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfaeb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfaezb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfaebs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfaezbs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfaeh %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfaezh %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfaehs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfaezhs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfaef %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfaezf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfaefs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfaezfs %v0, %v0, %v0 + + vfaeb %v0, %v0, %v0 + vfaezb %v0, %v0, %v0 + vfaebs %v0, %v0, %v0 + vfaezbs %v0, %v0, %v0 + vfaeh %v0, %v0, %v0 + vfaezh %v0, %v0, %v0 + vfaehs %v0, %v0, %v0 + vfaezhs %v0, %v0, %v0 + vfaef %v0, %v0, %v0 + vfaezf %v0, %v0, %v0 + vfaefs %v0, %v0, %v0 + vfaezfs %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfeeb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfeezb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfeebs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfeezbs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfeeh %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfeezh %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfeehs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfeezhs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfeef %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfeezf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfeefs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfeezfs %v0, %v0, %v0 + + vfeeb %v0, %v0, %v0 + vfeezb %v0, %v0, %v0 + vfeebs %v0, %v0, %v0 + vfeezbs %v0, %v0, %v0 + vfeeh %v0, %v0, %v0 + vfeezh %v0, %v0, %v0 + vfeehs %v0, %v0, %v0 + vfeezhs %v0, %v0, %v0 + vfeef %v0, %v0, %v0 + vfeezf %v0, %v0, %v0 + vfeefs %v0, %v0, %v0 + vfeezfs %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfeneb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfenezb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfenebs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfenezbs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfeneh %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfenezh %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfenehs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfenezhs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfenef %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfenezf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfenefs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfenezfs %v0, %v0, %v0 + + vfeneb %v0, %v0, %v0 + vfenezb %v0, %v0, %v0 + vfenebs %v0, %v0, %v0 + vfenezbs %v0, %v0, %v0 + vfeneh %v0, %v0, %v0 + vfenezh %v0, %v0, %v0 + vfenehs %v0, %v0, %v0 + vfenezhs %v0, %v0, %v0 + vfenef %v0, %v0, %v0 + vfenezf %v0, %v0, %v0 + vfenefs %v0, %v0, %v0 + vfenezfs %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfidb %v0, %v0, 0, 0 + + vfidb %v0, %v0, 0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vistrb %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vistrbs %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vistrh %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vistrhs %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vistrf %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vistrfs %v0, %v0 + + vistrb %v0, %v0 + vistrbs %v0, %v0 + vistrh %v0, %v0 + vistrhs %v0, %v0 + vistrf %v0, %v0 + vistrfs %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vflcdb %v0, %v0 + + vflcdb %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vflndb %v0, %v0 + + vflndb %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vflpdb %v0, %v0 + + vflpdb %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfmadb %v0, %v0, %v0, %v0 + + vfmadb %v0, %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfmdb %v0, %v0, %v0 + + vfmdb %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfmsdb %v0, %v0, %v0, %v0 + + vfmsdb %v0, %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfsdb %v0, %v0, %v0 + + vfsdb %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vfsqdb %v0, %v0 + + vfsqdb %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vftcidb %v0, %v0, 0 + + vftcidb %v0, %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vgbm %v0, 0 + + vgbm %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vgef %v0, 0(%v0, %r1), 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vgeg %v0, 0(%v0, %r1), 0 + + vgef %v0, 0(%v0, %r1), 0 + vgeg %v0, 0(%v0, %r1), 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vgfmab %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vgfmaf %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vgfmag %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vgfmah %v0, %v0, %v0, %v0 + + vgfmab %v0, %v0, %v0, %v0 + vgfmaf %v0, %v0, %v0, %v0 + vgfmag %v0, %v0, %v0, %v0 + vgfmah %v0, %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vgfmb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vgfmf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vgfmg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vgfmh %v0, %v0, %v0 + + vgfmb %v0, %v0, %v0 + vgfmf %v0, %v0, %v0 + vgfmg %v0, %v0, %v0 + vgfmh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vgmb %v0, 0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vgmf %v0, 0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vgmg %v0, 0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vgmh %v0, 0, 0 + + vgmb %v0, 0, 0 + vgmf %v0, 0, 0 + vgmg %v0, 0, 0 + vgmh %v0, 0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vl %v0, 0 + + vl %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlbb %v0, 0, 0 + + vlbb %v0, 0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlcb %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlcf %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlcg %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlch %v0, %v0 + + vlcb %v0, %v0 + vlcf %v0, %v0 + vlcg %v0, %v0 + vlch %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vldeb %v0, %v0 + + vldeb %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vleb %v0, 0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlef %v0, 0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vleg %v0, 0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vleh %v0, 0, 0 + + vleb %v0, 0, 0 + vlef %v0, 0, 0 + vleg %v0, 0, 0 + vleh %v0, 0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vledb %v0, %v0, 0, 0 + + vledb %v0, %v0, 0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vleib %v0, 0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vleif %v0, 0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vleig %v0, 0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vleih %v0, 0, 0 + + vleib %v0, 0, 0 + vleif %v0, 0, 0 + vleig %v0, 0, 0 + vleih %v0, 0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlgvb %r0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlgvf %r0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlgvg %r0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlgvh %r0, %v0, 0 + + vlgvb %r0, %v0, 0 + vlgvf %r0, %v0, 0 + vlgvg %r0, %v0, 0 + vlgvh %r0, %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vll %v0, %r0, 0 + + vll %v0, %r0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vllezb %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vllezf %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vllezg %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vllezh %v0, 0 + + vllezb %v0, 0 + vllezf %v0, 0 + vllezg %v0, 0 + vllezh %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlm %v0, %v0, 0 + + vlm %v0, %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlpb %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlpf %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlpg %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlph %v0, %v0 + + vlpb %v0, %v0 + vlpf %v0, %v0 + vlpg %v0, %v0 + vlph %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlr %v0, %v0 + + vlr %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlrepb %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlrepf %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlrepg %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlreph %v0, 0 + + vlrepb %v0, 0 + vlrepf %v0, 0 + vlrepg %v0, 0 + vlreph %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlvgb %v0, %r0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlvgf %v0, %r0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlvgg %v0, %r0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlvgh %v0, %r0, 0 + + vlvgb %v0, %r0, 0 + vlvgf %v0, %r0, 0 + vlvgg %v0, %r0, 0 + vlvgh %v0, %r0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vlvgp %v0, %r0, %r0 + + vlvgp %v0, %r0, %r0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmaeb %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmaef %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmaeh %v0, %v0, %v0, %v0 + + vmaeb %v0, %v0, %v0, %v0 + vmaef %v0, %v0, %v0, %v0 + vmaeh %v0, %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmahb %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmahf %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmahh %v0, %v0, %v0, %v0 + + vmahb %v0, %v0, %v0, %v0 + vmahf %v0, %v0, %v0, %v0 + vmahh %v0, %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmalb %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmalf %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmalhw %v0, %v0, %v0, %v0 + + vmalb %v0, %v0, %v0, %v0 + vmalf %v0, %v0, %v0, %v0 + vmalhw %v0, %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmaleb %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmalef %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmaleh %v0, %v0, %v0, %v0 + + vmaleb %v0, %v0, %v0, %v0 + vmalef %v0, %v0, %v0, %v0 + vmaleh %v0, %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmalhb %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmalhf %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmalhh %v0, %v0, %v0, %v0 + + vmalhb %v0, %v0, %v0, %v0 + vmalhf %v0, %v0, %v0, %v0 + vmalhh %v0, %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmalob %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmalof %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmaloh %v0, %v0, %v0, %v0 + + vmalob %v0, %v0, %v0, %v0 + vmalof %v0, %v0, %v0, %v0 + vmaloh %v0, %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmaob %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmaof %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmaoh %v0, %v0, %v0, %v0 + + vmaob %v0, %v0, %v0, %v0 + vmaof %v0, %v0, %v0, %v0 + vmaoh %v0, %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmeb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmef %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmeh %v0, %v0, %v0 + + vmeb %v0, %v0, %v0 + vmef %v0, %v0, %v0 + vmeh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmhb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmhf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmhh %v0, %v0, %v0 + + vmhb %v0, %v0, %v0 + vmhf %v0, %v0, %v0 + vmhh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmlb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmlf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmlh %v0, %v0, %v0 + + vmlb %v0, %v0, %v0 + vmlf %v0, %v0, %v0 + vmlh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmleb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmlef %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmleh %v0, %v0, %v0 + + vmleb %v0, %v0, %v0 + vmlef %v0, %v0, %v0 + vmleh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmlhb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmlhf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmlhh %v0, %v0, %v0 + + vmlhb %v0, %v0, %v0 + vmlhf %v0, %v0, %v0 + vmlhh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmlob %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmlof %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmloh %v0, %v0, %v0 + + vmlob %v0, %v0, %v0 + vmlof %v0, %v0, %v0 + vmloh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmnb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmnf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmng %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmnh %v0, %v0, %v0 + + vmnb %v0, %v0, %v0 + vmnf %v0, %v0, %v0 + vmng %v0, %v0, %v0 + vmnh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmnlb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmnlf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmnlg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmnlh %v0, %v0, %v0 + + vmnlb %v0, %v0, %v0 + vmnlf %v0, %v0, %v0 + vmnlg %v0, %v0, %v0 + vmnlh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmob %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmof %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmoh %v0, %v0, %v0 + + vmob %v0, %v0, %v0 + vmof %v0, %v0, %v0 + vmoh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmrhb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmrhf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmrhg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmrhh %v0, %v0, %v0 + + vmrhb %v0, %v0, %v0 + vmrhf %v0, %v0, %v0 + vmrhg %v0, %v0, %v0 + vmrhh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmrlb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmrlf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmrlg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmrlh %v0, %v0, %v0 + + vmrlb %v0, %v0, %v0 + vmrlf %v0, %v0, %v0 + vmrlg %v0, %v0, %v0 + vmrlh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmxb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmxf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmxg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmxh %v0, %v0, %v0 + + vmxb %v0, %v0, %v0 + vmxf %v0, %v0, %v0 + vmxg %v0, %v0, %v0 + vmxh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmxlb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmxlf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmxlg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vmxlh %v0, %v0, %v0 + + vmxlb %v0, %v0, %v0 + vmxlf %v0, %v0, %v0 + vmxlg %v0, %v0, %v0 + vmxlh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vn %v0, %v0, %v0 + + vn %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vnc %v0, %v0, %v0 + + vnc %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vno %v0, %v0, %v0 + + vno %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vo %v0, %v0, %v0 + + vo %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vone %v0 + + vone %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vpdi %v0, %v0, %v0, 0 + + vpdi %v0, %v0, %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vperm %v0, %v0, %v0, %v0 + + vperm %v0, %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vpkf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vpkg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vpkh %v0, %v0, %v0 + + vpkf %v0, %v0, %v0 + vpkg %v0, %v0, %v0 + vpkh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vpksf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vpksg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vpksh %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vpksfs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vpksgs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vpkshs %v0, %v0, %v0 + + vpksf %v0, %v0, %v0 + vpksg %v0, %v0, %v0 + vpksh %v0, %v0, %v0 + vpksfs %v0, %v0, %v0 + vpksgs %v0, %v0, %v0 + vpkshs %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vpklsf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vpklsg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vpklsh %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vpklsfs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vpklsgs %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vpklshs %v0, %v0, %v0 + + vpklsf %v0, %v0, %v0 + vpklsg %v0, %v0, %v0 + vpklsh %v0, %v0, %v0 + vpklsfs %v0, %v0, %v0 + vpklsgs %v0, %v0, %v0 + vpklshs %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vpopct %v0, %v0 + + vpopct %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vrepb %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vrepf %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vrepg %v0, %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vreph %v0, %v0, 0 + + vrepb %v0, %v0, 0 + vrepf %v0, %v0, 0 + vrepg %v0, %v0, 0 + vreph %v0, %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vrepib %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vrepif %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vrepig %v0, 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vrepih %v0, 0 + + vrepib %v0, 0 + vrepif %v0, 0 + vrepig %v0, 0 + vrepih %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsg %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsh %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsq %v0, %v0, %v0 + + vsb %v0, %v0, %v0 + vsf %v0, %v0, %v0 + vsg %v0, %v0, %v0 + vsh %v0, %v0, %v0 + vsq %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsbcbiq %v0, %v0, %v0 + + vsbcbiq %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsbiq %v0, %v0, %v0 + + vsbiq %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vscbib %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vscbif %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vscbig %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vscbih %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vscbiq %v0, %v0, %v0 + + vscbib %v0, %v0, %v0 + vscbif %v0, %v0, %v0 + vscbig %v0, %v0, %v0 + vscbih %v0, %v0, %v0 + vscbiq %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vscef %v0, 0(%v0, %r1), 0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsceg %v0, 0(%v0, %r1), 0 + + vscef %v0, 0(%v0, %r1), 0 + vsceg %v0, 0(%v0, %r1), 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsegb %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsegf %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsegh %v0, %v0 + + vsegb %v0, %v0 + vsegf %v0, %v0 + vsegh %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsel %v0, %v0, %v0, %v0 + + vsel %v0, %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsl %v0, %v0, %v0 + + vsl %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vslb %v0, %v0, %v0 + + vslb %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsldb %v0, %v0, %v0, 0 + + vsldb %v0, %v0, %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsra %v0, %v0, %v0 + + vsra %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsrab %v0, %v0, %v0 + + vsrab %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsrl %v0, %v0, %v0 + + vsrl %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsrlb %v0, %v0, %v0 + + vsrlb %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vst %v0, 0 + + vst %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vstl %v0, %r0, 0 + + vstl %v0, %r0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vstm %v0, %v0, 0 + + vstm %v0, %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vstrcb %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vstrczb %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vstrcbs %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vstrczbs %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vstrch %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vstrczh %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vstrchs %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vstrczhs %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vstrcf %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vstrczf %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vstrcfs %v0, %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vstrczfs %v0, %v0, %v0, %v0 + + vstrcb %v0, %v0, %v0, %v0 + vstrczb %v0, %v0, %v0, %v0 + vstrcbs %v0, %v0, %v0, %v0 + vstrczbs %v0, %v0, %v0, %v0 + vstrch %v0, %v0, %v0, %v0 + vstrczh %v0, %v0, %v0, %v0 + vstrchs %v0, %v0, %v0, %v0 + vstrczhs %v0, %v0, %v0, %v0 + vstrcf %v0, %v0, %v0, %v0 + vstrczf %v0, %v0, %v0, %v0 + vstrcfs %v0, %v0, %v0, %v0 + vstrczfs %v0, %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsumgh %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsumgf %v0, %v0, %v0 + + vsumgh %v0, %v0, %v0 + vsumgf %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsumqf %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsumqg %v0, %v0, %v0 + + vsumqf %v0, %v0, %v0 + vsumqg %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsumb %v0, %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vsumh %v0, %v0, %v0 + + vsumb %v0, %v0, %v0 + vsumh %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vtm %v0, %v0 + + vtm %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vuphb %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vuphf %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vuphh %v0, %v0 + + vuphb %v0, %v0 + vuphf %v0, %v0 + vuphh %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vuplhb %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vuplhf %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vuplhh %v0, %v0 + + vuplhb %v0, %v0 + vuplhf %v0, %v0 + vuplhh %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vuplb %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vuplf %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vuplhw %v0, %v0 + + vuplb %v0, %v0 + vuplf %v0, %v0 + vuplhw %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vupllb %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vupllf %v0, %v0 +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vupllh %v0, %v0 + + vupllb %v0, %v0 + vupllf %v0, %v0 + vupllh %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vx %v0, %v0, %v0 + + vx %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: vzero %v0 + + vzero %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wcdgb %v0, %v0, 0, 0 + + wcdgb %v0, %v0, 0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wcdlgb %v0, %v0, 0, 0 + + wcdlgb %v0, %v0, 0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wcgdb %v0, %v0, 0, 0 + + wcgdb %v0, %v0, 0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wclgdb %v0, %v0, 0, 0 + + wclgdb %v0, %v0, 0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wfadb %v0, %v0, %v0 + + wfadb %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wfcdb %v0, %v0 + + wfcdb %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wfcedb %v0, %v0, %v0 +#CHECK: wfcedbs %v0, %v0, %v0 + + wfcedb %v0, %v0, %v0 + wfcedbs %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wfchdb %v0, %v0, %v0 +#CHECK: wfchdbs %v0, %v0, %v0 + + wfchdb %v0, %v0, %v0 + wfchdbs %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wfchedb %v0, %v0, %v0 +#CHECK: wfchedbs %v0, %v0, %v0 + + wfchedb %v0, %v0, %v0 + wfchedbs %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wfddb %v0, %v0, %v0 + + wfddb %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wfidb %v0, %v0, 0, 0 + + wfidb %v0, %v0, 0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wfkdb %v0, %v0 + + wfkdb %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wflcdb %v0, %v0 + + wflcdb %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wflndb %v0, %v0 + + wflndb %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wflpdb %v0, %v0 + + wflpdb %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wfmadb %v0, %v0, %v0, %v0 + + wfmadb %v0, %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wfmdb %v0, %v0, %v0 + + wfmdb %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wfmsdb %v0, %v0, %v0, %v0 + + wfmsdb %v0, %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wfsdb %v0, %v0, %v0 + + wfsdb %v0, %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wfsqdb %v0, %v0 + + wfsqdb %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wftcidb %v0, %v0, 0 + + wftcidb %v0, %v0, 0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wldeb %v0, %v0 + + wldeb %v0, %v0 + +#CHECK: error: {{(instruction requires: vector)?}} +#CHECK: wledb %v0, %v0, 0, 0 + + wledb %v0, %v0, 0, 0 diff --git a/llvm/test/MC/SystemZ/insn-good-z13.s b/llvm/test/MC/SystemZ/insn-good-z13.s new file mode 100644 index 00000000000..621b946d19d --- /dev/null +++ b/llvm/test/MC/SystemZ/insn-good-z13.s @@ -0,0 +1,5039 @@ +# For z13 and above. +# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z13 -show-encoding %s \ +# RUN: | FileCheck %s + +#CHECK: lcbb %r0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x27] +#CHECK: lcbb %r0, 0, 15 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x27] +#CHECK: lcbb %r0, 4095, 0 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x27] +#CHECK: lcbb %r0, 0(%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x27] +#CHECK: lcbb %r0, 0(%r15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x27] +#CHECK: lcbb %r15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x27] +#CHECK: lcbb %r2, 1383(%r3,%r4), 8 # encoding: [0xe7,0x23,0x45,0x67,0x80,0x27] + + lcbb %r0, 0, 0 + lcbb %r0, 0, 15 + lcbb %r0, 4095, 0 + lcbb %r0, 0(%r15), 0 + lcbb %r0, 0(%r15,%r1), 0 + lcbb %r15, 0, 0 + lcbb %r2, 1383(%r3,%r4), 8 + +#CHECK: vab %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf3] +#CHECK: vab %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf3] +#CHECK: vab %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf3] +#CHECK: vab %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf3] +#CHECK: vab %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xf3] + + vab %v0, %v0, %v0 + vab %v0, %v0, %v31 + vab %v0, %v31, %v0 + vab %v31, %v0, %v0 + vab %v18, %v3, %v20 + +#CHECK: vaccb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf1] +#CHECK: vaccb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf1] +#CHECK: vaccb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf1] +#CHECK: vaccb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf1] +#CHECK: vaccb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xf1] + + vaccb %v0, %v0, %v0 + vaccb %v0, %v0, %v31 + vaccb %v0, %v31, %v0 + vaccb %v31, %v0, %v0 + vaccb %v18, %v3, %v20 + +#CHECK: vacccq %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x04,0x00,0x00,0xb9] +#CHECK: vacccq %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x04,0x00,0xf1,0xb9] +#CHECK: vacccq %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf4,0x00,0x02,0xb9] +#CHECK: vacccq %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x04,0x00,0x04,0xb9] +#CHECK: vacccq %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x04,0x00,0x08,0xb9] +#CHECK: vacccq %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x54,0x00,0x97,0xb9] + + vacccq %v0, %v0, %v0, %v0 + vacccq %v0, %v0, %v0, %v31 + vacccq %v0, %v0, %v31, %v0 + vacccq %v0, %v31, %v0, %v0 + vacccq %v31, %v0, %v0, %v0 + vacccq %v13, %v17, %v21, %v25 + +#CHECK: vaccf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xf1] +#CHECK: vaccf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xf1] +#CHECK: vaccf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xf1] +#CHECK: vaccf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xf1] +#CHECK: vaccf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xf1] + + vaccf %v0, %v0, %v0 + vaccf %v0, %v0, %v31 + vaccf %v0, %v31, %v0 + vaccf %v31, %v0, %v0 + vaccf %v18, %v3, %v20 + +#CHECK: vaccg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xf1] +#CHECK: vaccg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xf1] +#CHECK: vaccg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xf1] +#CHECK: vaccg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xf1] +#CHECK: vaccg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xf1] + + vaccg %v0, %v0, %v0 + vaccg %v0, %v0, %v31 + vaccg %v0, %v31, %v0 + vaccg %v31, %v0, %v0 + vaccg %v18, %v3, %v20 + +#CHECK: vacch %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xf1] +#CHECK: vacch %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xf1] +#CHECK: vacch %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xf1] +#CHECK: vacch %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xf1] +#CHECK: vacch %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xf1] + + vacch %v0, %v0, %v0 + vacch %v0, %v0, %v31 + vacch %v0, %v31, %v0 + vacch %v31, %v0, %v0 + vacch %v18, %v3, %v20 + +#CHECK: vaccq %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x40,0xf1] +#CHECK: vaccq %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x42,0xf1] +#CHECK: vaccq %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x44,0xf1] +#CHECK: vaccq %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x48,0xf1] +#CHECK: vaccq %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x4a,0xf1] + + vaccq %v0, %v0, %v0 + vaccq %v0, %v0, %v31 + vaccq %v0, %v31, %v0 + vaccq %v31, %v0, %v0 + vaccq %v18, %v3, %v20 + +#CHECK: vacq %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x04,0x00,0x00,0xbb] +#CHECK: vacq %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x04,0x00,0xf1,0xbb] +#CHECK: vacq %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf4,0x00,0x02,0xbb] +#CHECK: vacq %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x04,0x00,0x04,0xbb] +#CHECK: vacq %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x04,0x00,0x08,0xbb] +#CHECK: vacq %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x54,0x00,0x97,0xbb] + + vacq %v0, %v0, %v0, %v0 + vacq %v0, %v0, %v0, %v31 + vacq %v0, %v0, %v31, %v0 + vacq %v0, %v31, %v0, %v0 + vacq %v31, %v0, %v0, %v0 + vacq %v13, %v17, %v21, %v25 + +#CHECK: vaf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xf3] +#CHECK: vaf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xf3] +#CHECK: vaf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xf3] +#CHECK: vaf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xf3] +#CHECK: vaf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xf3] + + vaf %v0, %v0, %v0 + vaf %v0, %v0, %v31 + vaf %v0, %v31, %v0 + vaf %v31, %v0, %v0 + vaf %v18, %v3, %v20 + +#CHECK: vag %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xf3] +#CHECK: vag %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xf3] +#CHECK: vag %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xf3] +#CHECK: vag %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xf3] +#CHECK: vag %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xf3] + + vag %v0, %v0, %v0 + vag %v0, %v0, %v31 + vag %v0, %v31, %v0 + vag %v31, %v0, %v0 + vag %v18, %v3, %v20 + +#CHECK: vah %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xf3] +#CHECK: vah %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xf3] +#CHECK: vah %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xf3] +#CHECK: vah %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xf3] +#CHECK: vah %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xf3] + + vah %v0, %v0, %v0 + vah %v0, %v0, %v31 + vah %v0, %v31, %v0 + vah %v31, %v0, %v0 + vah %v18, %v3, %v20 + +#CHECK: vaq %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x40,0xf3] +#CHECK: vaq %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x42,0xf3] +#CHECK: vaq %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x44,0xf3] +#CHECK: vaq %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x48,0xf3] +#CHECK: vaq %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x4a,0xf3] + + vaq %v0, %v0, %v0 + vaq %v0, %v0, %v31 + vaq %v0, %v31, %v0 + vaq %v31, %v0, %v0 + vaq %v18, %v3, %v20 + +#CHECK: vavgb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf2] +#CHECK: vavgb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf2] +#CHECK: vavgb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf2] +#CHECK: vavgb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf2] +#CHECK: vavgb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xf2] + + vavgb %v0, %v0, %v0 + vavgb %v0, %v0, %v31 + vavgb %v0, %v31, %v0 + vavgb %v31, %v0, %v0 + vavgb %v18, %v3, %v20 + +#CHECK: vavgf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xf2] +#CHECK: vavgf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xf2] +#CHECK: vavgf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xf2] +#CHECK: vavgf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xf2] +#CHECK: vavgf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xf2] + + vavgf %v0, %v0, %v0 + vavgf %v0, %v0, %v31 + vavgf %v0, %v31, %v0 + vavgf %v31, %v0, %v0 + vavgf %v18, %v3, %v20 + +#CHECK: vavgg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xf2] +#CHECK: vavgg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xf2] +#CHECK: vavgg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xf2] +#CHECK: vavgg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xf2] +#CHECK: vavgg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xf2] + + vavgg %v0, %v0, %v0 + vavgg %v0, %v0, %v31 + vavgg %v0, %v31, %v0 + vavgg %v31, %v0, %v0 + vavgg %v18, %v3, %v20 + +#CHECK: vavgh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xf2] +#CHECK: vavgh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xf2] +#CHECK: vavgh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xf2] +#CHECK: vavgh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xf2] +#CHECK: vavgh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xf2] + + vavgh %v0, %v0, %v0 + vavgh %v0, %v0, %v31 + vavgh %v0, %v31, %v0 + vavgh %v31, %v0, %v0 + vavgh %v18, %v3, %v20 + +#CHECK: vavglb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf0] +#CHECK: vavglb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf0] +#CHECK: vavglb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf0] +#CHECK: vavglb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf0] +#CHECK: vavglb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xf0] + + vavglb %v0, %v0, %v0 + vavglb %v0, %v0, %v31 + vavglb %v0, %v31, %v0 + vavglb %v31, %v0, %v0 + vavglb %v18, %v3, %v20 + +#CHECK: vavglf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xf0] +#CHECK: vavglf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xf0] +#CHECK: vavglf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xf0] +#CHECK: vavglf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xf0] +#CHECK: vavglf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xf0] + + vavglf %v0, %v0, %v0 + vavglf %v0, %v0, %v31 + vavglf %v0, %v31, %v0 + vavglf %v31, %v0, %v0 + vavglf %v18, %v3, %v20 + +#CHECK: vavglg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xf0] +#CHECK: vavglg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xf0] +#CHECK: vavglg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xf0] +#CHECK: vavglg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xf0] +#CHECK: vavglg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xf0] + + vavglg %v0, %v0, %v0 + vavglg %v0, %v0, %v31 + vavglg %v0, %v31, %v0 + vavglg %v31, %v0, %v0 + vavglg %v18, %v3, %v20 + +#CHECK: vavglh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xf0] +#CHECK: vavglh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xf0] +#CHECK: vavglh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xf0] +#CHECK: vavglh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xf0] +#CHECK: vavglh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xf0] + + vavglh %v0, %v0, %v0 + vavglh %v0, %v0, %v31 + vavglh %v0, %v31, %v0 + vavglh %v31, %v0, %v0 + vavglh %v18, %v3, %v20 + +#CHECK: vcdgb %v0, %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xc3] +#CHECK: vcdgb %v0, %v0, 0, 15 # encoding: [0xe7,0x00,0x00,0xf0,0x30,0xc3] +#CHECK: vcdgb %v0, %v0, 4, 0 # encoding: [0xe7,0x00,0x00,0x04,0x30,0xc3] +#CHECK: vcdgb %v0, %v0, 12, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc3] +#CHECK: vcdgb %v0, %v31, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xc3] +#CHECK: vcdgb %v31, %v0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xc3] +#CHECK: vcdgb %v14, %v17, 4, 10 # encoding: [0xe7,0xe1,0x00,0xa4,0x34,0xc3] + + vcdgb %v0, %v0, 0, 0 + vcdgb %v0, %v0, 0, 15 + vcdgb %v0, %v0, 4, 0 + vcdgb %v0, %v0, 12, 0 + vcdgb %v0, %v31, 0, 0 + vcdgb %v31, %v0, 0, 0 + vcdgb %v14, %v17, 4, 10 + +#CHECK: vcdlgb %v0, %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xc1] +#CHECK: vcdlgb %v0, %v0, 0, 15 # encoding: [0xe7,0x00,0x00,0xf0,0x30,0xc1] +#CHECK: vcdlgb %v0, %v0, 4, 0 # encoding: [0xe7,0x00,0x00,0x04,0x30,0xc1] +#CHECK: vcdlgb %v0, %v0, 12, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc1] +#CHECK: vcdlgb %v0, %v31, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xc1] +#CHECK: vcdlgb %v31, %v0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xc1] +#CHECK: vcdlgb %v14, %v17, 4, 10 # encoding: [0xe7,0xe1,0x00,0xa4,0x34,0xc1] + + vcdlgb %v0, %v0, 0, 0 + vcdlgb %v0, %v0, 0, 15 + vcdlgb %v0, %v0, 4, 0 + vcdlgb %v0, %v0, 12, 0 + vcdlgb %v0, %v31, 0, 0 + vcdlgb %v31, %v0, 0, 0 + vcdlgb %v14, %v17, 4, 10 + +#CHECK: vcksm %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x66] +#CHECK: vcksm %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x66] +#CHECK: vcksm %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x66] +#CHECK: vcksm %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x66] +#CHECK: vcksm %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x66] + + vcksm %v0, %v0, %v0 + vcksm %v0, %v0, %v31 + vcksm %v0, %v31, %v0 + vcksm %v31, %v0, %v0 + vcksm %v18, %v3, %v20 + +#CHECK: vceqb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf8] +#CHECK: vceqb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf8] +#CHECK: vceqb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf8] +#CHECK: vceqb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf8] +#CHECK: vceqb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xf8] +#CHECK: vceqbs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x04,0xf8] + + vceqb %v0, %v0, %v0 + vceqb %v0, %v0, %v31 + vceqb %v0, %v31, %v0 + vceqb %v31, %v0, %v0 + vceqb %v18, %v3, %v20 + vceqbs %v5, %v22, %v7 + +#CHECK: vceqf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xf8] +#CHECK: vceqf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xf8] +#CHECK: vceqf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xf8] +#CHECK: vceqf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xf8] +#CHECK: vceqf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xf8] +#CHECK: vceqfs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x24,0xf8] + + vceqf %v0, %v0, %v0 + vceqf %v0, %v0, %v31 + vceqf %v0, %v31, %v0 + vceqf %v31, %v0, %v0 + vceqf %v18, %v3, %v20 + vceqfs %v5, %v22, %v7 + +#CHECK: vceqg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xf8] +#CHECK: vceqg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xf8] +#CHECK: vceqg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xf8] +#CHECK: vceqg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xf8] +#CHECK: vceqg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xf8] +#CHECK: vceqgs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x34,0xf8] + + vceqg %v0, %v0, %v0 + vceqg %v0, %v0, %v31 + vceqg %v0, %v31, %v0 + vceqg %v31, %v0, %v0 + vceqg %v18, %v3, %v20 + vceqgs %v5, %v22, %v7 + +#CHECK: vceqh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xf8] +#CHECK: vceqh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xf8] +#CHECK: vceqh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xf8] +#CHECK: vceqh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xf8] +#CHECK: vceqh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xf8] +#CHECK: vceqhs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x14,0xf8] + + vceqh %v0, %v0, %v0 + vceqh %v0, %v0, %v31 + vceqh %v0, %v31, %v0 + vceqh %v31, %v0, %v0 + vceqh %v18, %v3, %v20 + vceqhs %v5, %v22, %v7 + +#CHECK: vcgdb %v0, %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xc2] +#CHECK: vcgdb %v0, %v0, 0, 15 # encoding: [0xe7,0x00,0x00,0xf0,0x30,0xc2] +#CHECK: vcgdb %v0, %v0, 4, 0 # encoding: [0xe7,0x00,0x00,0x04,0x30,0xc2] +#CHECK: vcgdb %v0, %v0, 12, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc2] +#CHECK: vcgdb %v0, %v31, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xc2] +#CHECK: vcgdb %v31, %v0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xc2] +#CHECK: vcgdb %v14, %v17, 4, 10 # encoding: [0xe7,0xe1,0x00,0xa4,0x34,0xc2] + + vcgdb %v0, %v0, 0, 0 + vcgdb %v0, %v0, 0, 15 + vcgdb %v0, %v0, 4, 0 + vcgdb %v0, %v0, 12, 0 + vcgdb %v0, %v31, 0, 0 + vcgdb %v31, %v0, 0, 0 + vcgdb %v14, %v17, 4, 10 + +#CHECK: vchb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xfb] +#CHECK: vchb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xfb] +#CHECK: vchb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xfb] +#CHECK: vchb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xfb] +#CHECK: vchb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xfb] +#CHECK: vchbs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x04,0xfb] + + vchb %v0, %v0, %v0 + vchb %v0, %v0, %v31 + vchb %v0, %v31, %v0 + vchb %v31, %v0, %v0 + vchb %v18, %v3, %v20 + vchbs %v5, %v22, %v7 + +#CHECK: vchf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xfb] +#CHECK: vchf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xfb] +#CHECK: vchf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xfb] +#CHECK: vchf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xfb] +#CHECK: vchf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xfb] +#CHECK: vchfs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x24,0xfb] + + vchf %v0, %v0, %v0 + vchf %v0, %v0, %v31 + vchf %v0, %v31, %v0 + vchf %v31, %v0, %v0 + vchf %v18, %v3, %v20 + vchfs %v5, %v22, %v7 + +#CHECK: vchg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xfb] +#CHECK: vchg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xfb] +#CHECK: vchg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xfb] +#CHECK: vchg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xfb] +#CHECK: vchg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xfb] +#CHECK: vchgs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x34,0xfb] + + vchg %v0, %v0, %v0 + vchg %v0, %v0, %v31 + vchg %v0, %v31, %v0 + vchg %v31, %v0, %v0 + vchg %v18, %v3, %v20 + vchgs %v5, %v22, %v7 + +#CHECK: vchh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xfb] +#CHECK: vchh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xfb] +#CHECK: vchh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xfb] +#CHECK: vchh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xfb] +#CHECK: vchh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xfb] +#CHECK: vchhs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x14,0xfb] + + vchh %v0, %v0, %v0 + vchh %v0, %v0, %v31 + vchh %v0, %v31, %v0 + vchh %v31, %v0, %v0 + vchh %v18, %v3, %v20 + vchhs %v5, %v22, %v7 + +#CHECK: vchlb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf9] +#CHECK: vchlb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf9] +#CHECK: vchlb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf9] +#CHECK: vchlb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf9] +#CHECK: vchlb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xf9] +#CHECK: vchlbs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x04,0xf9] + + vchlb %v0, %v0, %v0 + vchlb %v0, %v0, %v31 + vchlb %v0, %v31, %v0 + vchlb %v31, %v0, %v0 + vchlb %v18, %v3, %v20 + vchlbs %v5, %v22, %v7 + +#CHECK: vchlf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xf9] +#CHECK: vchlf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xf9] +#CHECK: vchlf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xf9] +#CHECK: vchlf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xf9] +#CHECK: vchlf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xf9] +#CHECK: vchlfs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x24,0xf9] + + vchlf %v0, %v0, %v0 + vchlf %v0, %v0, %v31 + vchlf %v0, %v31, %v0 + vchlf %v31, %v0, %v0 + vchlf %v18, %v3, %v20 + vchlfs %v5, %v22, %v7 + +#CHECK: vchlg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xf9] +#CHECK: vchlg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xf9] +#CHECK: vchlg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xf9] +#CHECK: vchlg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xf9] +#CHECK: vchlg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xf9] +#CHECK: vchlgs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x34,0xf9] + + vchlg %v0, %v0, %v0 + vchlg %v0, %v0, %v31 + vchlg %v0, %v31, %v0 + vchlg %v31, %v0, %v0 + vchlg %v18, %v3, %v20 + vchlgs %v5, %v22, %v7 + +#CHECK: vchlh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xf9] +#CHECK: vchlh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xf9] +#CHECK: vchlh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xf9] +#CHECK: vchlh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xf9] +#CHECK: vchlh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xf9] +#CHECK: vchlhs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x14,0xf9] + + vchlh %v0, %v0, %v0 + vchlh %v0, %v0, %v31 + vchlh %v0, %v31, %v0 + vchlh %v31, %v0, %v0 + vchlh %v18, %v3, %v20 + vchlhs %v5, %v22, %v7 + +#CHECK: vclgdb %v0, %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xc0] +#CHECK: vclgdb %v0, %v0, 0, 15 # encoding: [0xe7,0x00,0x00,0xf0,0x30,0xc0] +#CHECK: vclgdb %v0, %v0, 4, 0 # encoding: [0xe7,0x00,0x00,0x04,0x30,0xc0] +#CHECK: vclgdb %v0, %v0, 12, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc0] +#CHECK: vclgdb %v0, %v31, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xc0] +#CHECK: vclgdb %v31, %v0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xc0] +#CHECK: vclgdb %v14, %v17, 4, 10 # encoding: [0xe7,0xe1,0x00,0xa4,0x34,0xc0] + + vclgdb %v0, %v0, 0, 0 + vclgdb %v0, %v0, 0, 15 + vclgdb %v0, %v0, 4, 0 + vclgdb %v0, %v0, 12, 0 + vclgdb %v0, %v31, 0, 0 + vclgdb %v31, %v0, 0, 0 + vclgdb %v14, %v17, 4, 10 + +#CHECK: vclzb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x53] +#CHECK: vclzb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x53] +#CHECK: vclzb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x53] +#CHECK: vclzb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x53] +#CHECK: vclzb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x53] +#CHECK: vclzb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0x53] + + vclzb %v0, %v0 + vclzb %v0, %v15 + vclzb %v0, %v31 + vclzb %v15, %v0 + vclzb %v31, %v0 + vclzb %v14, %v17 + +#CHECK: vclzf %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x53] +#CHECK: vclzf %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x53] +#CHECK: vclzf %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x53] +#CHECK: vclzf %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x53] +#CHECK: vclzf %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x53] +#CHECK: vclzf %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x24,0x53] + + vclzf %v0, %v0 + vclzf %v0, %v15 + vclzf %v0, %v31 + vclzf %v15, %v0 + vclzf %v31, %v0 + vclzf %v14, %v17 + +#CHECK: vclzg %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x53] +#CHECK: vclzg %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x53] +#CHECK: vclzg %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x53] +#CHECK: vclzg %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x53] +#CHECK: vclzg %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x53] +#CHECK: vclzg %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x34,0x53] + + vclzg %v0, %v0 + vclzg %v0, %v15 + vclzg %v0, %v31 + vclzg %v15, %v0 + vclzg %v31, %v0 + vclzg %v14, %v17 + +#CHECK: vclzh %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x53] +#CHECK: vclzh %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x53] +#CHECK: vclzh %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x53] +#CHECK: vclzh %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x53] +#CHECK: vclzh %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x53] +#CHECK: vclzh %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x14,0x53] + + vclzh %v0, %v0 + vclzh %v0, %v15 + vclzh %v0, %v31 + vclzh %v15, %v0 + vclzh %v31, %v0 + vclzh %v14, %v17 + +#CHECK: vctzb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x52] +#CHECK: vctzb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x52] +#CHECK: vctzb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x52] +#CHECK: vctzb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x52] +#CHECK: vctzb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x52] +#CHECK: vctzb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0x52] + + vctzb %v0, %v0 + vctzb %v0, %v15 + vctzb %v0, %v31 + vctzb %v15, %v0 + vctzb %v31, %v0 + vctzb %v14, %v17 + +#CHECK: vctzf %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x52] +#CHECK: vctzf %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x52] +#CHECK: vctzf %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x52] +#CHECK: vctzf %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x52] +#CHECK: vctzf %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x52] +#CHECK: vctzf %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x24,0x52] + + vctzf %v0, %v0 + vctzf %v0, %v15 + vctzf %v0, %v31 + vctzf %v15, %v0 + vctzf %v31, %v0 + vctzf %v14, %v17 + +#CHECK: vctzg %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x52] +#CHECK: vctzg %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x52] +#CHECK: vctzg %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x52] +#CHECK: vctzg %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x52] +#CHECK: vctzg %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x52] +#CHECK: vctzg %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x34,0x52] + + vctzg %v0, %v0 + vctzg %v0, %v15 + vctzg %v0, %v31 + vctzg %v15, %v0 + vctzg %v31, %v0 + vctzg %v14, %v17 + +#CHECK: vctzh %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x52] +#CHECK: vctzh %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x52] +#CHECK: vctzh %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x52] +#CHECK: vctzh %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x52] +#CHECK: vctzh %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x52] +#CHECK: vctzh %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x14,0x52] + + vctzh %v0, %v0 + vctzh %v0, %v15 + vctzh %v0, %v31 + vctzh %v15, %v0 + vctzh %v31, %v0 + vctzh %v14, %v17 + +#CHECK: vecb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xdb] +#CHECK: vecb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xdb] +#CHECK: vecb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xdb] +#CHECK: vecb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xdb] +#CHECK: vecb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xdb] +#CHECK: vecb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xdb] + + vecb %v0, %v0 + vecb %v0, %v15 + vecb %v0, %v31 + vecb %v15, %v0 + vecb %v31, %v0 + vecb %v14, %v17 + +#CHECK: vecf %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xdb] +#CHECK: vecf %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xdb] +#CHECK: vecf %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xdb] +#CHECK: vecf %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xdb] +#CHECK: vecf %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xdb] +#CHECK: vecf %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xdb] + + vecf %v0, %v0 + vecf %v0, %v15 + vecf %v0, %v31 + vecf %v15, %v0 + vecf %v31, %v0 + vecf %v14, %v17 + +#CHECK: vecg %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xdb] +#CHECK: vecg %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0xdb] +#CHECK: vecg %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xdb] +#CHECK: vecg %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0xdb] +#CHECK: vecg %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xdb] +#CHECK: vecg %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x34,0xdb] + + vecg %v0, %v0 + vecg %v0, %v15 + vecg %v0, %v31 + vecg %v15, %v0 + vecg %v31, %v0 + vecg %v14, %v17 + +#CHECK: vech %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xdb] +#CHECK: vech %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0xdb] +#CHECK: vech %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xdb] +#CHECK: vech %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0xdb] +#CHECK: vech %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xdb] +#CHECK: vech %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x14,0xdb] + + vech %v0, %v0 + vech %v0, %v15 + vech %v0, %v31 + vech %v15, %v0 + vech %v31, %v0 + vech %v14, %v17 + +#CHECK: veclb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xd9] +#CHECK: veclb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xd9] +#CHECK: veclb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xd9] +#CHECK: veclb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xd9] +#CHECK: veclb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xd9] +#CHECK: veclb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xd9] + + veclb %v0, %v0 + veclb %v0, %v15 + veclb %v0, %v31 + veclb %v15, %v0 + veclb %v31, %v0 + veclb %v14, %v17 + +#CHECK: veclf %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xd9] +#CHECK: veclf %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xd9] +#CHECK: veclf %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xd9] +#CHECK: veclf %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xd9] +#CHECK: veclf %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xd9] +#CHECK: veclf %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xd9] + + veclf %v0, %v0 + veclf %v0, %v15 + veclf %v0, %v31 + veclf %v15, %v0 + veclf %v31, %v0 + veclf %v14, %v17 + +#CHECK: veclg %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xd9] +#CHECK: veclg %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0xd9] +#CHECK: veclg %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xd9] +#CHECK: veclg %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0xd9] +#CHECK: veclg %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xd9] +#CHECK: veclg %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x34,0xd9] + + veclg %v0, %v0 + veclg %v0, %v15 + veclg %v0, %v31 + veclg %v15, %v0 + veclg %v31, %v0 + veclg %v14, %v17 + +#CHECK: veclh %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xd9] +#CHECK: veclh %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0xd9] +#CHECK: veclh %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xd9] +#CHECK: veclh %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0xd9] +#CHECK: veclh %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xd9] +#CHECK: veclh %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x14,0xd9] + + veclh %v0, %v0 + veclh %v0, %v15 + veclh %v0, %v31 + veclh %v15, %v0 + veclh %v31, %v0 + veclh %v14, %v17 + +#CHECK: verimb %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x72] +#CHECK: verimb %v0, %v0, %v0, 255 # encoding: [0xe7,0x00,0x00,0xff,0x00,0x72] +#CHECK: verimb %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x72] +#CHECK: verimb %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x72] +#CHECK: verimb %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x72] +#CHECK: verimb %v13, %v17, %v21, 121 # encoding: [0xe7,0xd1,0x50,0x79,0x06,0x72] + + verimb %v0, %v0, %v0, 0 + verimb %v0, %v0, %v0, 255 + verimb %v0, %v0, %v31, 0 + verimb %v0, %v31, %v0, 0 + verimb %v31, %v0, %v0, 0 + verimb %v13, %v17, %v21, 0x79 + +#CHECK: verimf %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x72] +#CHECK: verimf %v0, %v0, %v0, 255 # encoding: [0xe7,0x00,0x00,0xff,0x20,0x72] +#CHECK: verimf %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x72] +#CHECK: verimf %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x72] +#CHECK: verimf %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x72] +#CHECK: verimf %v13, %v17, %v21, 121 # encoding: [0xe7,0xd1,0x50,0x79,0x26,0x72] + + verimf %v0, %v0, %v0, 0 + verimf %v0, %v0, %v0, 255 + verimf %v0, %v0, %v31, 0 + verimf %v0, %v31, %v0, 0 + verimf %v31, %v0, %v0, 0 + verimf %v13, %v17, %v21, 0x79 + +#CHECK: verimg %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x72] +#CHECK: verimg %v0, %v0, %v0, 255 # encoding: [0xe7,0x00,0x00,0xff,0x30,0x72] +#CHECK: verimg %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x72] +#CHECK: verimg %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x72] +#CHECK: verimg %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x72] +#CHECK: verimg %v13, %v17, %v21, 121 # encoding: [0xe7,0xd1,0x50,0x79,0x36,0x72] + + verimg %v0, %v0, %v0, 0 + verimg %v0, %v0, %v0, 255 + verimg %v0, %v0, %v31, 0 + verimg %v0, %v31, %v0, 0 + verimg %v31, %v0, %v0, 0 + verimg %v13, %v17, %v21, 0x79 + +#CHECK: verimh %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x72] +#CHECK: verimh %v0, %v0, %v0, 255 # encoding: [0xe7,0x00,0x00,0xff,0x10,0x72] +#CHECK: verimh %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x72] +#CHECK: verimh %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x72] +#CHECK: verimh %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x72] +#CHECK: verimh %v13, %v17, %v21, 121 # encoding: [0xe7,0xd1,0x50,0x79,0x16,0x72] + + verimh %v0, %v0, %v0, 0 + verimh %v0, %v0, %v0, 255 + verimh %v0, %v0, %v31, 0 + verimh %v0, %v31, %v0, 0 + verimh %v31, %v0, %v0, 0 + verimh %v13, %v17, %v21, 0x79 + +#CHECK: verllvb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x73] +#CHECK: verllvb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x73] +#CHECK: verllvb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x73] +#CHECK: verllvb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x73] +#CHECK: verllvb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x73] + + verllvb %v0, %v0, %v0 + verllvb %v0, %v0, %v31 + verllvb %v0, %v31, %v0 + verllvb %v31, %v0, %v0 + verllvb %v18, %v3, %v20 + +#CHECK: verllvf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x73] +#CHECK: verllvf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x73] +#CHECK: verllvf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x73] +#CHECK: verllvf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x73] +#CHECK: verllvf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x73] + + verllvf %v0, %v0, %v0 + verllvf %v0, %v0, %v31 + verllvf %v0, %v31, %v0 + verllvf %v31, %v0, %v0 + verllvf %v18, %v3, %v20 + +#CHECK: verllvg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x73] +#CHECK: verllvg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x73] +#CHECK: verllvg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x73] +#CHECK: verllvg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x73] +#CHECK: verllvg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x73] + + verllvg %v0, %v0, %v0 + verllvg %v0, %v0, %v31 + verllvg %v0, %v31, %v0 + verllvg %v31, %v0, %v0 + verllvg %v18, %v3, %v20 + +#CHECK: verllvh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x73] +#CHECK: verllvh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x73] +#CHECK: verllvh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x73] +#CHECK: verllvh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x73] +#CHECK: verllvh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x73] + + verllvh %v0, %v0, %v0 + verllvh %v0, %v0, %v31 + verllvh %v0, %v31, %v0 + verllvh %v31, %v0, %v0 + verllvh %v18, %v3, %v20 + +#CHECK: verllb %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x33] +#CHECK: verllb %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x33] +#CHECK: verllb %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x33] +#CHECK: verllb %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x33] +#CHECK: verllb %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x33] +#CHECK: verllb %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x04,0x33] + + verllb %v0, %v0, 0 + verllb %v0, %v0, 4095 + verllb %v0, %v0, 0(%r15) + verllb %v0, %v31, 0 + verllb %v31, %v0, 0 + verllb %v14, %v17, 1074(%r5) + +#CHECK: verllf %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x33] +#CHECK: verllf %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x33] +#CHECK: verllf %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x33] +#CHECK: verllf %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x33] +#CHECK: verllf %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x33] +#CHECK: verllf %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x24,0x33] + + verllf %v0, %v0, 0 + verllf %v0, %v0, 4095 + verllf %v0, %v0, 0(%r15) + verllf %v0, %v31, 0 + verllf %v31, %v0, 0 + verllf %v14, %v17, 1074(%r5) + +#CHECK: verllg %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x33] +#CHECK: verllg %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x30,0x33] +#CHECK: verllg %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x33] +#CHECK: verllg %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x33] +#CHECK: verllg %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x33] +#CHECK: verllg %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x34,0x33] + + verllg %v0, %v0, 0 + verllg %v0, %v0, 4095 + verllg %v0, %v0, 0(%r15) + verllg %v0, %v31, 0 + verllg %v31, %v0, 0 + verllg %v14, %v17, 1074(%r5) + +#CHECK: verllh %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x33] +#CHECK: verllh %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x10,0x33] +#CHECK: verllh %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x33] +#CHECK: verllh %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x33] +#CHECK: verllh %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x33] +#CHECK: verllh %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x14,0x33] + + verllh %v0, %v0, 0 + verllh %v0, %v0, 4095 + verllh %v0, %v0, 0(%r15) + verllh %v0, %v31, 0 + verllh %v31, %v0, 0 + verllh %v14, %v17, 1074(%r5) + +#CHECK: veslvb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x70] +#CHECK: veslvb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x70] +#CHECK: veslvb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x70] +#CHECK: veslvb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x70] +#CHECK: veslvb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x70] + + veslvb %v0, %v0, %v0 + veslvb %v0, %v0, %v31 + veslvb %v0, %v31, %v0 + veslvb %v31, %v0, %v0 + veslvb %v18, %v3, %v20 + +#CHECK: veslvf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x70] +#CHECK: veslvf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x70] +#CHECK: veslvf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x70] +#CHECK: veslvf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x70] +#CHECK: veslvf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x70] + + veslvf %v0, %v0, %v0 + veslvf %v0, %v0, %v31 + veslvf %v0, %v31, %v0 + veslvf %v31, %v0, %v0 + veslvf %v18, %v3, %v20 + +#CHECK: veslvg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x70] +#CHECK: veslvg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x70] +#CHECK: veslvg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x70] +#CHECK: veslvg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x70] +#CHECK: veslvg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x70] + + veslvg %v0, %v0, %v0 + veslvg %v0, %v0, %v31 + veslvg %v0, %v31, %v0 + veslvg %v31, %v0, %v0 + veslvg %v18, %v3, %v20 + +#CHECK: veslvh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x70] +#CHECK: veslvh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x70] +#CHECK: veslvh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x70] +#CHECK: veslvh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x70] +#CHECK: veslvh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x70] + + veslvh %v0, %v0, %v0 + veslvh %v0, %v0, %v31 + veslvh %v0, %v31, %v0 + veslvh %v31, %v0, %v0 + veslvh %v18, %v3, %v20 + +#CHECK: veslb %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x30] +#CHECK: veslb %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x30] +#CHECK: veslb %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x30] +#CHECK: veslb %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x30] +#CHECK: veslb %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x30] +#CHECK: veslb %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x04,0x30] + + veslb %v0, %v0, 0 + veslb %v0, %v0, 4095 + veslb %v0, %v0, 0(%r15) + veslb %v0, %v31, 0 + veslb %v31, %v0, 0 + veslb %v14, %v17, 1074(%r5) + +#CHECK: veslf %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x30] +#CHECK: veslf %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x30] +#CHECK: veslf %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x30] +#CHECK: veslf %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x30] +#CHECK: veslf %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x30] +#CHECK: veslf %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x24,0x30] + + veslf %v0, %v0, 0 + veslf %v0, %v0, 4095 + veslf %v0, %v0, 0(%r15) + veslf %v0, %v31, 0 + veslf %v31, %v0, 0 + veslf %v14, %v17, 1074(%r5) + +#CHECK: veslg %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x30] +#CHECK: veslg %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x30,0x30] +#CHECK: veslg %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x30] +#CHECK: veslg %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x30] +#CHECK: veslg %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x30] +#CHECK: veslg %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x34,0x30] + + veslg %v0, %v0, 0 + veslg %v0, %v0, 4095 + veslg %v0, %v0, 0(%r15) + veslg %v0, %v31, 0 + veslg %v31, %v0, 0 + veslg %v14, %v17, 1074(%r5) + +#CHECK: veslh %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x30] +#CHECK: veslh %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x10,0x30] +#CHECK: veslh %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x30] +#CHECK: veslh %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x30] +#CHECK: veslh %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x30] +#CHECK: veslh %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x14,0x30] + + veslh %v0, %v0, 0 + veslh %v0, %v0, 4095 + veslh %v0, %v0, 0(%r15) + veslh %v0, %v31, 0 + veslh %v31, %v0, 0 + veslh %v14, %v17, 1074(%r5) + +#CHECK: vesravb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x7a] +#CHECK: vesravb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x7a] +#CHECK: vesravb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x7a] +#CHECK: vesravb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x7a] +#CHECK: vesravb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x7a] + + vesravb %v0, %v0, %v0 + vesravb %v0, %v0, %v31 + vesravb %v0, %v31, %v0 + vesravb %v31, %v0, %v0 + vesravb %v18, %v3, %v20 + +#CHECK: vesravf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x7a] +#CHECK: vesravf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x7a] +#CHECK: vesravf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x7a] +#CHECK: vesravf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x7a] +#CHECK: vesravf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x7a] + + vesravf %v0, %v0, %v0 + vesravf %v0, %v0, %v31 + vesravf %v0, %v31, %v0 + vesravf %v31, %v0, %v0 + vesravf %v18, %v3, %v20 + +#CHECK: vesravg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x7a] +#CHECK: vesravg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x7a] +#CHECK: vesravg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x7a] +#CHECK: vesravg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x7a] +#CHECK: vesravg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x7a] + + vesravg %v0, %v0, %v0 + vesravg %v0, %v0, %v31 + vesravg %v0, %v31, %v0 + vesravg %v31, %v0, %v0 + vesravg %v18, %v3, %v20 + +#CHECK: vesravh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x7a] +#CHECK: vesravh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x7a] +#CHECK: vesravh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x7a] +#CHECK: vesravh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x7a] +#CHECK: vesravh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x7a] + + vesravh %v0, %v0, %v0 + vesravh %v0, %v0, %v31 + vesravh %v0, %v31, %v0 + vesravh %v31, %v0, %v0 + vesravh %v18, %v3, %v20 + +#CHECK: vesrab %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x3a] +#CHECK: vesrab %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x3a] +#CHECK: vesrab %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x3a] +#CHECK: vesrab %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x3a] +#CHECK: vesrab %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x3a] +#CHECK: vesrab %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x04,0x3a] + + vesrab %v0, %v0, 0 + vesrab %v0, %v0, 4095 + vesrab %v0, %v0, 0(%r15) + vesrab %v0, %v31, 0 + vesrab %v31, %v0, 0 + vesrab %v14, %v17, 1074(%r5) + +#CHECK: vesraf %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x3a] +#CHECK: vesraf %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x3a] +#CHECK: vesraf %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x3a] +#CHECK: vesraf %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x3a] +#CHECK: vesraf %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x3a] +#CHECK: vesraf %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x24,0x3a] + + vesraf %v0, %v0, 0 + vesraf %v0, %v0, 4095 + vesraf %v0, %v0, 0(%r15) + vesraf %v0, %v31, 0 + vesraf %v31, %v0, 0 + vesraf %v14, %v17, 1074(%r5) + +#CHECK: vesrag %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x3a] +#CHECK: vesrag %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x30,0x3a] +#CHECK: vesrag %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x3a] +#CHECK: vesrag %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x3a] +#CHECK: vesrag %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x3a] +#CHECK: vesrag %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x34,0x3a] + + vesrag %v0, %v0, 0 + vesrag %v0, %v0, 4095 + vesrag %v0, %v0, 0(%r15) + vesrag %v0, %v31, 0 + vesrag %v31, %v0, 0 + vesrag %v14, %v17, 1074(%r5) + +#CHECK: vesrah %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x3a] +#CHECK: vesrah %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x10,0x3a] +#CHECK: vesrah %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x3a] +#CHECK: vesrah %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x3a] +#CHECK: vesrah %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x3a] +#CHECK: vesrah %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x14,0x3a] + + vesrah %v0, %v0, 0 + vesrah %v0, %v0, 4095 + vesrah %v0, %v0, 0(%r15) + vesrah %v0, %v31, 0 + vesrah %v31, %v0, 0 + vesrah %v14, %v17, 1074(%r5) + +#CHECK: vesrlvb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x78] +#CHECK: vesrlvb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x78] +#CHECK: vesrlvb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x78] +#CHECK: vesrlvb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x78] +#CHECK: vesrlvb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x78] + + vesrlvb %v0, %v0, %v0 + vesrlvb %v0, %v0, %v31 + vesrlvb %v0, %v31, %v0 + vesrlvb %v31, %v0, %v0 + vesrlvb %v18, %v3, %v20 + +#CHECK: vesrlvf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x78] +#CHECK: vesrlvf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x78] +#CHECK: vesrlvf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x78] +#CHECK: vesrlvf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x78] +#CHECK: vesrlvf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x78] + + vesrlvf %v0, %v0, %v0 + vesrlvf %v0, %v0, %v31 + vesrlvf %v0, %v31, %v0 + vesrlvf %v31, %v0, %v0 + vesrlvf %v18, %v3, %v20 + +#CHECK: vesrlvg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x78] +#CHECK: vesrlvg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x78] +#CHECK: vesrlvg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x78] +#CHECK: vesrlvg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x78] +#CHECK: vesrlvg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x78] + + vesrlvg %v0, %v0, %v0 + vesrlvg %v0, %v0, %v31 + vesrlvg %v0, %v31, %v0 + vesrlvg %v31, %v0, %v0 + vesrlvg %v18, %v3, %v20 + +#CHECK: vesrlvh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x78] +#CHECK: vesrlvh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x78] +#CHECK: vesrlvh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x78] +#CHECK: vesrlvh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x78] +#CHECK: vesrlvh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x78] + + vesrlvh %v0, %v0, %v0 + vesrlvh %v0, %v0, %v31 + vesrlvh %v0, %v31, %v0 + vesrlvh %v31, %v0, %v0 + vesrlvh %v18, %v3, %v20 + +#CHECK: vesrlb %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x38] +#CHECK: vesrlb %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x38] +#CHECK: vesrlb %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x38] +#CHECK: vesrlb %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x38] +#CHECK: vesrlb %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x38] +#CHECK: vesrlb %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x04,0x38] + + vesrlb %v0, %v0, 0 + vesrlb %v0, %v0, 4095 + vesrlb %v0, %v0, 0(%r15) + vesrlb %v0, %v31, 0 + vesrlb %v31, %v0, 0 + vesrlb %v14, %v17, 1074(%r5) + +#CHECK: vesrlf %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x38] +#CHECK: vesrlf %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x38] +#CHECK: vesrlf %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x38] +#CHECK: vesrlf %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x38] +#CHECK: vesrlf %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x38] +#CHECK: vesrlf %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x24,0x38] + + vesrlf %v0, %v0, 0 + vesrlf %v0, %v0, 4095 + vesrlf %v0, %v0, 0(%r15) + vesrlf %v0, %v31, 0 + vesrlf %v31, %v0, 0 + vesrlf %v14, %v17, 1074(%r5) + +#CHECK: vesrlg %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x38] +#CHECK: vesrlg %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x30,0x38] +#CHECK: vesrlg %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x38] +#CHECK: vesrlg %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x38] +#CHECK: vesrlg %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x38] +#CHECK: vesrlg %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x34,0x38] + + vesrlg %v0, %v0, 0 + vesrlg %v0, %v0, 4095 + vesrlg %v0, %v0, 0(%r15) + vesrlg %v0, %v31, 0 + vesrlg %v31, %v0, 0 + vesrlg %v14, %v17, 1074(%r5) + +#CHECK: vesrlh %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x38] +#CHECK: vesrlh %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x10,0x38] +#CHECK: vesrlh %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x38] +#CHECK: vesrlh %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x38] +#CHECK: vesrlh %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x38] +#CHECK: vesrlh %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x14,0x38] + + vesrlh %v0, %v0, 0 + vesrlh %v0, %v0, 4095 + vesrlh %v0, %v0, 0(%r15) + vesrlh %v0, %v31, 0 + vesrlh %v31, %v0, 0 + vesrlh %v14, %v17, 1074(%r5) + +#CHECK: vfadb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xe3] +#CHECK: vfadb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xe3] +#CHECK: vfadb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xe3] +#CHECK: vfadb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xe3] +#CHECK: vfadb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xe3] + + vfadb %v0, %v0, %v0 + vfadb %v0, %v0, %v31 + vfadb %v0, %v31, %v0 + vfadb %v31, %v0, %v0 + vfadb %v18, %v3, %v20 + +#CHECK: vfaeb %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x82] +#CHECK: vfaeb %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x82] +#CHECK: vfaeb %v0, %v0, %v0, 12 # encoding: [0xe7,0x00,0x00,0xc0,0x00,0x82] +#CHECK: vfaeb %v0, %v0, %v15, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x82] +#CHECK: vfaeb %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x82] +#CHECK: vfaeb %v0, %v15, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x82] +#CHECK: vfaeb %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x82] +#CHECK: vfaeb %v15, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x82] +#CHECK: vfaeb %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x82] +#CHECK: vfaeb %v18, %v3, %v20, 4 # encoding: [0xe7,0x23,0x40,0x40,0x0a,0x82] +#CHECK: vfaeb %v18, %v3, %v20, 15 # encoding: [0xe7,0x23,0x40,0xf0,0x0a,0x82] +#CHECK: vfaebs %v18, %v3, %v20, 8 # encoding: [0xe7,0x23,0x40,0x90,0x0a,0x82] +#CHECK: vfaezb %v18, %v3, %v20, 4 # encoding: [0xe7,0x23,0x40,0x60,0x0a,0x82] +#CHECK: vfaezbs %v18, %v3, %v20, 8 # encoding: [0xe7,0x23,0x40,0xb0,0x0a,0x82] +#CHECK: vfaezbs %v18, %v3, %v20, 15 # encoding: [0xe7,0x23,0x40,0xf0,0x0a,0x82] + + vfaeb %v0, %v0, %v0 + vfaeb %v0, %v0, %v0, 0 + vfaeb %v0, %v0, %v0, 12 + vfaeb %v0, %v0, %v15 + vfaeb %v0, %v0, %v31 + vfaeb %v0, %v15, %v0 + vfaeb %v0, %v31, %v0 + vfaeb %v15, %v0, %v0 + vfaeb %v31, %v0, %v0 + vfaeb %v18, %v3, %v20, 4 + vfaeb %v18, %v3, %v20, 15 + vfaebs %v18, %v3, %v20, 8 + vfaezb %v18, %v3, %v20, 4 + vfaezbs %v18, %v3, %v20, 8 + vfaezbs %v18, %v3, %v20, 15 + +#CHECK: vfaef %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x82] +#CHECK: vfaef %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x82] +#CHECK: vfaef %v0, %v0, %v0, 12 # encoding: [0xe7,0x00,0x00,0xc0,0x20,0x82] +#CHECK: vfaef %v0, %v0, %v15, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x82] +#CHECK: vfaef %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x82] +#CHECK: vfaef %v0, %v15, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x82] +#CHECK: vfaef %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x82] +#CHECK: vfaef %v15, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x82] +#CHECK: vfaef %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x82] +#CHECK: vfaef %v18, %v3, %v20, 4 # encoding: [0xe7,0x23,0x40,0x40,0x2a,0x82] +#CHECK: vfaef %v18, %v3, %v20, 15 # encoding: [0xe7,0x23,0x40,0xf0,0x2a,0x82] +#CHECK: vfaefs %v18, %v3, %v20, 8 # encoding: [0xe7,0x23,0x40,0x90,0x2a,0x82] +#CHECK: vfaezf %v18, %v3, %v20, 4 # encoding: [0xe7,0x23,0x40,0x60,0x2a,0x82] +#CHECK: vfaezfs %v18, %v3, %v20, 8 # encoding: [0xe7,0x23,0x40,0xb0,0x2a,0x82] +#CHECK: vfaezfs %v18, %v3, %v20, 15 # encoding: [0xe7,0x23,0x40,0xf0,0x2a,0x82] + + vfaef %v0, %v0, %v0 + vfaef %v0, %v0, %v0, 0 + vfaef %v0, %v0, %v0, 12 + vfaef %v0, %v0, %v15 + vfaef %v0, %v0, %v31 + vfaef %v0, %v15, %v0 + vfaef %v0, %v31, %v0 + vfaef %v15, %v0, %v0 + vfaef %v31, %v0, %v0 + vfaef %v18, %v3, %v20, 4 + vfaef %v18, %v3, %v20, 15 + vfaefs %v18, %v3, %v20, 8 + vfaezf %v18, %v3, %v20, 4 + vfaezfs %v18, %v3, %v20, 8 + vfaezfs %v18, %v3, %v20, 15 + +#CHECK: vfaeh %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x82] +#CHECK: vfaeh %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x82] +#CHECK: vfaeh %v0, %v0, %v0, 12 # encoding: [0xe7,0x00,0x00,0xc0,0x10,0x82] +#CHECK: vfaeh %v0, %v0, %v15, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x82] +#CHECK: vfaeh %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x82] +#CHECK: vfaeh %v0, %v15, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x82] +#CHECK: vfaeh %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x82] +#CHECK: vfaeh %v15, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x82] +#CHECK: vfaeh %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x82] +#CHECK: vfaeh %v18, %v3, %v20, 4 # encoding: [0xe7,0x23,0x40,0x40,0x1a,0x82] +#CHECK: vfaeh %v18, %v3, %v20, 15 # encoding: [0xe7,0x23,0x40,0xf0,0x1a,0x82] +#CHECK: vfaehs %v18, %v3, %v20, 8 # encoding: [0xe7,0x23,0x40,0x90,0x1a,0x82] +#CHECK: vfaezh %v18, %v3, %v20, 4 # encoding: [0xe7,0x23,0x40,0x60,0x1a,0x82] +#CHECK: vfaezhs %v18, %v3, %v20, 8 # encoding: [0xe7,0x23,0x40,0xb0,0x1a,0x82] +#CHECK: vfaezhs %v18, %v3, %v20, 15 # encoding: [0xe7,0x23,0x40,0xf0,0x1a,0x82] + + vfaeh %v0, %v0, %v0 + vfaeh %v0, %v0, %v0, 0 + vfaeh %v0, %v0, %v0, 12 + vfaeh %v0, %v0, %v15 + vfaeh %v0, %v0, %v31 + vfaeh %v0, %v15, %v0 + vfaeh %v0, %v31, %v0 + vfaeh %v15, %v0, %v0 + vfaeh %v31, %v0, %v0 + vfaeh %v18, %v3, %v20, 4 + vfaeh %v18, %v3, %v20, 15 + vfaehs %v18, %v3, %v20, 8 + vfaezh %v18, %v3, %v20, 4 + vfaezhs %v18, %v3, %v20, 8 + vfaezhs %v18, %v3, %v20, 15 + +#CHECK: vfcedb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xe8] +#CHECK: vfcedb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xe8] +#CHECK: vfcedb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xe8] +#CHECK: vfcedb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xe8] +#CHECK: vfcedb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xe8] + + vfcedb %v0, %v0, %v0 + vfcedb %v0, %v0, %v31 + vfcedb %v0, %v31, %v0 + vfcedb %v31, %v0, %v0 + vfcedb %v18, %v3, %v20 + +#CHECK: vfcedbs %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x10,0x30,0xe8] +#CHECK: vfcedbs %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x10,0x32,0xe8] +#CHECK: vfcedbs %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x10,0x34,0xe8] +#CHECK: vfcedbs %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x10,0x38,0xe8] +#CHECK: vfcedbs %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x10,0x3a,0xe8] + + vfcedbs %v0, %v0, %v0 + vfcedbs %v0, %v0, %v31 + vfcedbs %v0, %v31, %v0 + vfcedbs %v31, %v0, %v0 + vfcedbs %v18, %v3, %v20 + +#CHECK: vfchdb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xeb] +#CHECK: vfchdb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xeb] +#CHECK: vfchdb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xeb] +#CHECK: vfchdb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xeb] +#CHECK: vfchdb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xeb] + + vfchdb %v0, %v0, %v0 + vfchdb %v0, %v0, %v31 + vfchdb %v0, %v31, %v0 + vfchdb %v31, %v0, %v0 + vfchdb %v18, %v3, %v20 + +#CHECK: vfchdbs %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x10,0x30,0xeb] +#CHECK: vfchdbs %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x10,0x32,0xeb] +#CHECK: vfchdbs %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x10,0x34,0xeb] +#CHECK: vfchdbs %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x10,0x38,0xeb] +#CHECK: vfchdbs %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x10,0x3a,0xeb] + + vfchdbs %v0, %v0, %v0 + vfchdbs %v0, %v0, %v31 + vfchdbs %v0, %v31, %v0 + vfchdbs %v31, %v0, %v0 + vfchdbs %v18, %v3, %v20 + +#CHECK: vfchedb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xea] +#CHECK: vfchedb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xea] +#CHECK: vfchedb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xea] +#CHECK: vfchedb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xea] +#CHECK: vfchedb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xea] + + vfchedb %v0, %v0, %v0 + vfchedb %v0, %v0, %v31 + vfchedb %v0, %v31, %v0 + vfchedb %v31, %v0, %v0 + vfchedb %v18, %v3, %v20 + +#CHECK: vfchedbs %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x10,0x30,0xea] +#CHECK: vfchedbs %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x10,0x32,0xea] +#CHECK: vfchedbs %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x10,0x34,0xea] +#CHECK: vfchedbs %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x10,0x38,0xea] +#CHECK: vfchedbs %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x10,0x3a,0xea] + + vfchedbs %v0, %v0, %v0 + vfchedbs %v0, %v0, %v31 + vfchedbs %v0, %v31, %v0 + vfchedbs %v31, %v0, %v0 + vfchedbs %v18, %v3, %v20 + +#CHECK: vfddb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xe5] +#CHECK: vfddb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xe5] +#CHECK: vfddb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xe5] +#CHECK: vfddb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xe5] +#CHECK: vfddb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xe5] + + vfddb %v0, %v0, %v0 + vfddb %v0, %v0, %v31 + vfddb %v0, %v31, %v0 + vfddb %v31, %v0, %v0 + vfddb %v18, %v3, %v20 + +#CHECK: vfeeb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x80] +#CHECK: vfeeb %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x80] +#CHECK: vfeeb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x80] +#CHECK: vfeeb %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x80] +#CHECK: vfeeb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x80] +#CHECK: vfeeb %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x80] +#CHECK: vfeeb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x80] +#CHECK: vfeeb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x80] +#CHECK: vfeebs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x04,0x80] +#CHECK: vfeezb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x20,0x0a,0x80] +#CHECK: vfeezbs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x30,0x04,0x80] + + vfeeb %v0, %v0, %v0 + vfeeb %v0, %v0, %v15 + vfeeb %v0, %v0, %v31 + vfeeb %v0, %v15, %v0 + vfeeb %v0, %v31, %v0 + vfeeb %v15, %v0, %v0 + vfeeb %v31, %v0, %v0 + vfeeb %v18, %v3, %v20 + vfeebs %v5, %v22, %v7 + vfeezb %v18, %v3, %v20 + vfeezbs %v5, %v22, %v7 + +#CFECK: vfeef %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x80] +#CFECK: vfeef %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x80] +#CFECK: vfeef %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x80] +#CFECK: vfeef %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x80] +#CFECK: vfeef %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x80] +#CFECK: vfeef %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x80] +#CFECK: vfeef %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x80] +#CFECK: vfeef %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x80] +#CFECK: vfeefs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x24,0x80] +#CFECK: vfeezf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x20,0x2a,0x80] +#CFECK: vfeezfs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x30,0x24,0x80] + + vfeef %v0, %v0, %v0 + vfeef %v0, %v0, %v15 + vfeef %v0, %v0, %v31 + vfeef %v0, %v15, %v0 + vfeef %v0, %v31, %v0 + vfeef %v15, %v0, %v0 + vfeef %v31, %v0, %v0 + vfeef %v18, %v3, %v20 + vfeefs %v5, %v22, %v7 + vfeezf %v18, %v3, %v20 + vfeezfs %v5, %v22, %v7 + +#CHECK: vfeeh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x80] +#CHECK: vfeeh %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x80] +#CHECK: vfeeh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x80] +#CHECK: vfeeh %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x80] +#CHECK: vfeeh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x80] +#CHECK: vfeeh %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x80] +#CHECK: vfeeh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x80] +#CHECK: vfeeh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x80] +#CHECK: vfeehs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x14,0x80] +#CHECK: vfeezh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x20,0x1a,0x80] +#CHECK: vfeezhs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x30,0x14,0x80] + + vfeeh %v0, %v0, %v0 + vfeeh %v0, %v0, %v15 + vfeeh %v0, %v0, %v31 + vfeeh %v0, %v15, %v0 + vfeeh %v0, %v31, %v0 + vfeeh %v15, %v0, %v0 + vfeeh %v31, %v0, %v0 + vfeeh %v18, %v3, %v20 + vfeehs %v5, %v22, %v7 + vfeezh %v18, %v3, %v20 + vfeezhs %v5, %v22, %v7 + +#CHECK: vfeneb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x81] +#CHECK: vfeneb %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x81] +#CHECK: vfeneb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x81] +#CHECK: vfeneb %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x81] +#CHECK: vfeneb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x81] +#CHECK: vfeneb %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x81] +#CHECK: vfeneb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x81] +#CHECK: vfeneb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x81] +#CHECK: vfenebs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x04,0x81] +#CHECK: vfenezb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x20,0x0a,0x81] +#CHECK: vfenezbs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x30,0x04,0x81] + + vfeneb %v0, %v0, %v0 + vfeneb %v0, %v0, %v15 + vfeneb %v0, %v0, %v31 + vfeneb %v0, %v15, %v0 + vfeneb %v0, %v31, %v0 + vfeneb %v15, %v0, %v0 + vfeneb %v31, %v0, %v0 + vfeneb %v18, %v3, %v20 + vfenebs %v5, %v22, %v7 + vfenezb %v18, %v3, %v20 + vfenezbs %v5, %v22, %v7 + +#CFECK: vfenef %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x81] +#CFECK: vfenef %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x81] +#CFECK: vfenef %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x81] +#CFECK: vfenef %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x81] +#CFECK: vfenef %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x81] +#CFECK: vfenef %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x81] +#CFECK: vfenef %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x81] +#CFECK: vfenef %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x81] +#CFECK: vfenefs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x24,0x81] +#CFECK: vfenezf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x20,0x2a,0x81] +#CFECK: vfenezfs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x30,0x24,0x81] + + vfenef %v0, %v0, %v0 + vfenef %v0, %v0, %v15 + vfenef %v0, %v0, %v31 + vfenef %v0, %v15, %v0 + vfenef %v0, %v31, %v0 + vfenef %v15, %v0, %v0 + vfenef %v31, %v0, %v0 + vfenef %v18, %v3, %v20 + vfenefs %v5, %v22, %v7 + vfenezf %v18, %v3, %v20 + vfenezfs %v5, %v22, %v7 + +#CHECK: vfeneh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x81] +#CHECK: vfeneh %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x81] +#CHECK: vfeneh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x81] +#CHECK: vfeneh %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x81] +#CHECK: vfeneh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x81] +#CHECK: vfeneh %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x81] +#CHECK: vfeneh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x81] +#CHECK: vfeneh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x81] +#CHECK: vfenehs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x14,0x81] +#CHECK: vfenezh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x20,0x1a,0x81] +#CHECK: vfenezhs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x30,0x14,0x81] + + vfeneh %v0, %v0, %v0 + vfeneh %v0, %v0, %v15 + vfeneh %v0, %v0, %v31 + vfeneh %v0, %v15, %v0 + vfeneh %v0, %v31, %v0 + vfeneh %v15, %v0, %v0 + vfeneh %v31, %v0, %v0 + vfeneh %v18, %v3, %v20 + vfenehs %v5, %v22, %v7 + vfenezh %v18, %v3, %v20 + vfenezhs %v5, %v22, %v7 + +#CHECK: vfidb %v0, %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xc7] +#CHECK: vfidb %v0, %v0, 0, 15 # encoding: [0xe7,0x00,0x00,0xf0,0x30,0xc7] +#CHECK: vfidb %v0, %v0, 4, 0 # encoding: [0xe7,0x00,0x00,0x04,0x30,0xc7] +#CHECK: vfidb %v0, %v0, 12, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc7] +#CHECK: vfidb %v0, %v31, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xc7] +#CHECK: vfidb %v31, %v0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xc7] +#CHECK: vfidb %v14, %v17, 4, 10 # encoding: [0xe7,0xe1,0x00,0xa4,0x34,0xc7] + + vfidb %v0, %v0, 0, 0 + vfidb %v0, %v0, 0, 15 + vfidb %v0, %v0, 4, 0 + vfidb %v0, %v0, 12, 0 + vfidb %v0, %v31, 0, 0 + vfidb %v31, %v0, 0, 0 + vfidb %v14, %v17, 4, 10 + +#CHECK: vistrb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x5c] +#CHECK: vistrb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x5c] +#CHECK: vistrb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x5c] +#CHECK: vistrb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x5c] +#CHECK: vistrb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x5c] +#CHECK: vistrb %v18, %v3 # encoding: [0xe7,0x23,0x00,0x00,0x08,0x5c] +#CHECK: vistrbs %v5, %v22 # encoding: [0xe7,0x56,0x00,0x10,0x04,0x5c] + + vistrb %v0, %v0 + vistrb %v0, %v15 + vistrb %v0, %v31 + vistrb %v15, %v0 + vistrb %v31, %v0 + vistrb %v18, %v3 + vistrbs %v5, %v22 + +#CBECK: vistrf %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x5c] +#CBECK: vistrf %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x5c] +#CBECK: vistrf %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x5c] +#CBECK: vistrf %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x5c] +#CBECK: vistrf %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x5c] +#CBECK: vistrf %v18, %v3 # encoding: [0xe7,0x23,0x00,0x00,0x28,0x5c] +#CBECK: vistrfs %v5, %v22 # encoding: [0xe7,0x56,0x00,0x10,0x24,0x5c] + + vistrf %v0, %v0 + vistrf %v0, %v15 + vistrf %v0, %v31 + vistrf %v15, %v0 + vistrf %v31, %v0 + vistrf %v18, %v3 + vistrfs %v5, %v22 + +#CHECK: vistrh %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x5c] +#CHECK: vistrh %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x5c] +#CHECK: vistrh %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x5c] +#CHECK: vistrh %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x5c] +#CHECK: vistrh %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x5c] +#CHECK: vistrh %v18, %v3 # encoding: [0xe7,0x23,0x00,0x00,0x18,0x5c] +#CHECK: vistrhs %v5, %v22 # encoding: [0xe7,0x56,0x00,0x10,0x14,0x5c] + + vistrh %v0, %v0 + vistrh %v0, %v15 + vistrh %v0, %v31 + vistrh %v15, %v0 + vistrh %v31, %v0 + vistrh %v18, %v3 + vistrhs %v5, %v22 + +#CHECK: vflcdb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xcc] +#CHECK: vflcdb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0xcc] +#CHECK: vflcdb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xcc] +#CHECK: vflcdb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0xcc] +#CHECK: vflcdb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xcc] +#CHECK: vflcdb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x34,0xcc] + + vflcdb %v0, %v0 + vflcdb %v0, %v15 + vflcdb %v0, %v31 + vflcdb %v15, %v0 + vflcdb %v31, %v0 + vflcdb %v14, %v17 + +#CHECK: vflndb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x10,0x30,0xcc] +#CHECK: vflndb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x10,0x30,0xcc] +#CHECK: vflndb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x10,0x34,0xcc] +#CHECK: vflndb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x10,0x30,0xcc] +#CHECK: vflndb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x10,0x38,0xcc] +#CHECK: vflndb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x10,0x34,0xcc] + + vflndb %v0, %v0 + vflndb %v0, %v15 + vflndb %v0, %v31 + vflndb %v15, %v0 + vflndb %v31, %v0 + vflndb %v14, %v17 + +#CHECK: vflpdb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x20,0x30,0xcc] +#CHECK: vflpdb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x20,0x30,0xcc] +#CHECK: vflpdb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x20,0x34,0xcc] +#CHECK: vflpdb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x20,0x30,0xcc] +#CHECK: vflpdb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x20,0x38,0xcc] +#CHECK: vflpdb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x20,0x34,0xcc] + + vflpdb %v0, %v0 + vflpdb %v0, %v15 + vflpdb %v0, %v31 + vflpdb %v15, %v0 + vflpdb %v31, %v0 + vflpdb %v14, %v17 + +#CHECK: vfmadb %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x03,0x00,0x00,0x8f] +#CHECK: vfmadb %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x03,0x00,0xf1,0x8f] +#CHECK: vfmadb %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf3,0x00,0x02,0x8f] +#CHECK: vfmadb %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x03,0x00,0x04,0x8f] +#CHECK: vfmadb %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x03,0x00,0x08,0x8f] +#CHECK: vfmadb %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x53,0x00,0x97,0x8f] + + vfmadb %v0, %v0, %v0, %v0 + vfmadb %v0, %v0, %v0, %v31 + vfmadb %v0, %v0, %v31, %v0 + vfmadb %v0, %v31, %v0, %v0 + vfmadb %v31, %v0, %v0, %v0 + vfmadb %v13, %v17, %v21, %v25 + +#CHECK: vfmdb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xe7] +#CHECK: vfmdb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xe7] +#CHECK: vfmdb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xe7] +#CHECK: vfmdb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xe7] +#CHECK: vfmdb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xe7] + + vfmdb %v0, %v0, %v0 + vfmdb %v0, %v0, %v31 + vfmdb %v0, %v31, %v0 + vfmdb %v31, %v0, %v0 + vfmdb %v18, %v3, %v20 + +#CHECK: vfmsdb %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x03,0x00,0x00,0x8e] +#CHECK: vfmsdb %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x03,0x00,0xf1,0x8e] +#CHECK: vfmsdb %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf3,0x00,0x02,0x8e] +#CHECK: vfmsdb %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x03,0x00,0x04,0x8e] +#CHECK: vfmsdb %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x03,0x00,0x08,0x8e] +#CHECK: vfmsdb %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x53,0x00,0x97,0x8e] + + vfmsdb %v0, %v0, %v0, %v0 + vfmsdb %v0, %v0, %v0, %v31 + vfmsdb %v0, %v0, %v31, %v0 + vfmsdb %v0, %v31, %v0, %v0 + vfmsdb %v31, %v0, %v0, %v0 + vfmsdb %v13, %v17, %v21, %v25 + +#CHECK: vfsdb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xe2] +#CHECK: vfsdb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xe2] +#CHECK: vfsdb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xe2] +#CHECK: vfsdb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xe2] +#CHECK: vfsdb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xe2] + + vfsdb %v0, %v0, %v0 + vfsdb %v0, %v0, %v31 + vfsdb %v0, %v31, %v0 + vfsdb %v31, %v0, %v0 + vfsdb %v18, %v3, %v20 + +#CHECK: vfsqdb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xce] +#CHECK: vfsqdb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0xce] +#CHECK: vfsqdb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xce] +#CHECK: vfsqdb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0xce] +#CHECK: vfsqdb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xce] +#CHECK: vfsqdb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x34,0xce] + + vfsqdb %v0, %v0 + vfsqdb %v0, %v15 + vfsqdb %v0, %v31 + vfsqdb %v15, %v0 + vfsqdb %v31, %v0 + vfsqdb %v14, %v17 + +#CHECK: vftcidb %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x4a] +#CHECK: vftcidb %v0, %v0, 4095 # encoding: [0xe7,0x00,0xff,0xf0,0x30,0x4a] +#CHECK: vftcidb %v0, %v15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x4a] +#CHECK: vftcidb %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x4a] +#CHECK: vftcidb %v15, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x4a] +#CHECK: vftcidb %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x4a] +#CHECK: vftcidb %v4, %v21, 1656 # encoding: [0xe7,0x45,0x67,0x80,0x34,0x4a] + + vftcidb %v0, %v0, 0 + vftcidb %v0, %v0, 4095 + vftcidb %v0, %v15, 0 + vftcidb %v0, %v31, 0 + vftcidb %v15, %v0, 0 + vftcidb %v31, %v0, 0 + vftcidb %v4, %v21, 0x678 + +#CHECK: vgbm %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x44] +#CHECK: vgbm %v0, 65535 # encoding: [0xe7,0x00,0xff,0xff,0x00,0x44] +#CHECK: vgbm %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x44] +#CHECK: vgbm %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x44] +#CHECK: vgbm %v17, 4660 # encoding: [0xe7,0x10,0x12,0x34,0x08,0x44] + + vgbm %v0, 0 + vgbm %v0, 0xffff + vgbm %v15, 0 + vgbm %v31, 0 + vgbm %v17, 0x1234 + +#CHECK: vgef %v0, 0(%v0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x13] +#CHECK: vgef %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x13] +#CHECK: vgef %v0, 0(%v0,%r1), 3 # encoding: [0xe7,0x00,0x10,0x00,0x30,0x13] +#CHECK: vgef %v0, 0(%v0,%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x13] +#CHECK: vgef %v0, 0(%v15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x13] +#CHECK: vgef %v0, 0(%v31,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x04,0x13] +#CHECK: vgef %v0, 4095(%v0,%r1), 0 # encoding: [0xe7,0x00,0x1f,0xff,0x00,0x13] +#CHECK: vgef %v15, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x00,0x13] +#CHECK: vgef %v31, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x13] +#CHECK: vgef %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x13] + + vgef %v0, 0(%v0), 0 + vgef %v0, 0(%v0,%r1), 0 + vgef %v0, 0(%v0,%r1), 3 + vgef %v0, 0(%v0,%r15), 0 + vgef %v0, 0(%v15,%r1), 0 + vgef %v0, 0(%v31,%r1), 0 + vgef %v0, 4095(%v0, %r1), 0 + vgef %v15, 0(%v0,%r1), 0 + vgef %v31, 0(%v0,%r1), 0 + vgef %v10, 1000(%v19,%r7), 1 + +#CHECK: vgeg %v0, 0(%v0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x12] +#CHECK: vgeg %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x12] +#CHECK: vgeg %v0, 0(%v0,%r1), 1 # encoding: [0xe7,0x00,0x10,0x00,0x10,0x12] +#CHECK: vgeg %v0, 0(%v0,%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x12] +#CHECK: vgeg %v0, 0(%v15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x12] +#CHECK: vgeg %v0, 0(%v31,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x04,0x12] +#CHECK: vgeg %v0, 4095(%v0,%r1), 0 # encoding: [0xe7,0x00,0x1f,0xff,0x00,0x12] +#CHECK: vgeg %v15, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x00,0x12] +#CHECK: vgeg %v31, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x12] +#CHECK: vgeg %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x12] + + vgeg %v0, 0(%v0), 0 + vgeg %v0, 0(%v0,%r1), 0 + vgeg %v0, 0(%v0,%r1), 1 + vgeg %v0, 0(%v0,%r15), 0 + vgeg %v0, 0(%v15,%r1), 0 + vgeg %v0, 0(%v31,%r1), 0 + vgeg %v0, 4095(%v0,%r1), 0 + vgeg %v15, 0(%v0,%r1), 0 + vgeg %v31, 0(%v0,%r1), 0 + vgeg %v10, 1000(%v19,%r7), 1 + +#CHECK: vgfmab %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xbc] +#CHECK: vgfmab %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xbc] +#CHECK: vgfmab %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xbc] +#CHECK: vgfmab %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xbc] +#CHECK: vgfmab %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xbc] +#CHECK: vgfmab %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x50,0x00,0x97,0xbc] + + vgfmab %v0, %v0, %v0, %v0 + vgfmab %v0, %v0, %v0, %v31 + vgfmab %v0, %v0, %v31, %v0 + vgfmab %v0, %v31, %v0, %v0 + vgfmab %v31, %v0, %v0, %v0 + vgfmab %v13, %v17, %v21, %v25 + +#CHECK: vgfmaf %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x02,0x00,0x00,0xbc] +#CHECK: vgfmaf %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x02,0x00,0xf1,0xbc] +#CHECK: vgfmaf %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf2,0x00,0x02,0xbc] +#CHECK: vgfmaf %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x02,0x00,0x04,0xbc] +#CHECK: vgfmaf %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x02,0x00,0x08,0xbc] +#CHECK: vgfmaf %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x52,0x00,0x97,0xbc] + + vgfmaf %v0, %v0, %v0, %v0 + vgfmaf %v0, %v0, %v0, %v31 + vgfmaf %v0, %v0, %v31, %v0 + vgfmaf %v0, %v31, %v0, %v0 + vgfmaf %v31, %v0, %v0, %v0 + vgfmaf %v13, %v17, %v21, %v25 + +#CHECK: vgfmag %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x03,0x00,0x00,0xbc] +#CHECK: vgfmag %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x03,0x00,0xf1,0xbc] +#CHECK: vgfmag %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf3,0x00,0x02,0xbc] +#CHECK: vgfmag %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x03,0x00,0x04,0xbc] +#CHECK: vgfmag %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x03,0x00,0x08,0xbc] +#CHECK: vgfmag %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x53,0x00,0x97,0xbc] + + vgfmag %v0, %v0, %v0, %v0 + vgfmag %v0, %v0, %v0, %v31 + vgfmag %v0, %v0, %v31, %v0 + vgfmag %v0, %v31, %v0, %v0 + vgfmag %v31, %v0, %v0, %v0 + vgfmag %v13, %v17, %v21, %v25 + +#CHECK: vgfmah %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x01,0x00,0x00,0xbc] +#CHECK: vgfmah %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x01,0x00,0xf1,0xbc] +#CHECK: vgfmah %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf1,0x00,0x02,0xbc] +#CHECK: vgfmah %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x01,0x00,0x04,0xbc] +#CHECK: vgfmah %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x01,0x00,0x08,0xbc] +#CHECK: vgfmah %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x51,0x00,0x97,0xbc] + + vgfmah %v0, %v0, %v0, %v0 + vgfmah %v0, %v0, %v0, %v31 + vgfmah %v0, %v0, %v31, %v0 + vgfmah %v0, %v31, %v0, %v0 + vgfmah %v31, %v0, %v0, %v0 + vgfmah %v13, %v17, %v21, %v25 + +#CHECK: vgfmb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xb4] +#CHECK: vgfmb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xb4] +#CHECK: vgfmb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xb4] +#CHECK: vgfmb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xb4] +#CHECK: vgfmb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xb4] + + vgfmb %v0, %v0, %v0 + vgfmb %v0, %v0, %v31 + vgfmb %v0, %v31, %v0 + vgfmb %v31, %v0, %v0 + vgfmb %v18, %v3, %v20 + +#CHECK: vgfmf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xb4] +#CHECK: vgfmf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xb4] +#CHECK: vgfmf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xb4] +#CHECK: vgfmf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xb4] +#CHECK: vgfmf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xb4] + + vgfmf %v0, %v0, %v0 + vgfmf %v0, %v0, %v31 + vgfmf %v0, %v31, %v0 + vgfmf %v31, %v0, %v0 + vgfmf %v18, %v3, %v20 + +#CHECK: vgfmg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xb4] +#CHECK: vgfmg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xb4] +#CHECK: vgfmg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xb4] +#CHECK: vgfmg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xb4] +#CHECK: vgfmg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xb4] + + vgfmg %v0, %v0, %v0 + vgfmg %v0, %v0, %v31 + vgfmg %v0, %v31, %v0 + vgfmg %v31, %v0, %v0 + vgfmg %v18, %v3, %v20 + +#CHECK: vgfmh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xb4] +#CHECK: vgfmh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xb4] +#CHECK: vgfmh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xb4] +#CHECK: vgfmh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xb4] +#CHECK: vgfmh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xb4] + + vgfmh %v0, %v0, %v0 + vgfmh %v0, %v0, %v31 + vgfmh %v0, %v31, %v0 + vgfmh %v31, %v0, %v0 + vgfmh %v18, %v3, %v20 + +#CHECK: vgmb %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x46] +#CHECK: vgmb %v0, 0, 255 # encoding: [0xe7,0x00,0x00,0xff,0x00,0x46] +#CHECK: vgmb %v0, 255, 0 # encoding: [0xe7,0x00,0xff,0x00,0x00,0x46] +#CHECK: vgmb %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x46] +#CHECK: vgmb %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x46] +#CHECK: vgmb %v21, 2, 3 # encoding: [0xe7,0x50,0x02,0x03,0x08,0x46] + + vgmb %v0, 0, 0 + vgmb %v0, 0, 255 + vgmb %v0, 255, 0 + vgmb %v15, 0, 0 + vgmb %v31, 0, 0 + vgmb %v21, 2, 3 + +#CHECK: vgmf %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x46] +#CHECK: vgmf %v0, 0, 255 # encoding: [0xe7,0x00,0x00,0xff,0x20,0x46] +#CHECK: vgmf %v0, 255, 0 # encoding: [0xe7,0x00,0xff,0x00,0x20,0x46] +#CHECK: vgmf %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x46] +#CHECK: vgmf %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x46] +#CHECK: vgmf %v21, 2, 3 # encoding: [0xe7,0x50,0x02,0x03,0x28,0x46] + + vgmf %v0, 0, 0 + vgmf %v0, 0, 255 + vgmf %v0, 255, 0 + vgmf %v15, 0, 0 + vgmf %v31, 0, 0 + vgmf %v21, 2, 3 + +#CHECK: vgmg %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x46] +#CHECK: vgmg %v0, 0, 255 # encoding: [0xe7,0x00,0x00,0xff,0x30,0x46] +#CHECK: vgmg %v0, 255, 0 # encoding: [0xe7,0x00,0xff,0x00,0x30,0x46] +#CHECK: vgmg %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x46] +#CHECK: vgmg %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x46] +#CHECK: vgmg %v21, 2, 3 # encoding: [0xe7,0x50,0x02,0x03,0x38,0x46] + + vgmg %v0, 0, 0 + vgmg %v0, 0, 255 + vgmg %v0, 255, 0 + vgmg %v15, 0, 0 + vgmg %v31, 0, 0 + vgmg %v21, 2, 3 + +#CHECK: vgmh %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x46] +#CHECK: vgmh %v0, 0, 255 # encoding: [0xe7,0x00,0x00,0xff,0x10,0x46] +#CHECK: vgmh %v0, 255, 0 # encoding: [0xe7,0x00,0xff,0x00,0x10,0x46] +#CHECK: vgmh %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x46] +#CHECK: vgmh %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x46] +#CHECK: vgmh %v21, 2, 3 # encoding: [0xe7,0x50,0x02,0x03,0x18,0x46] + + vgmh %v0, 0, 0 + vgmh %v0, 0, 255 + vgmh %v0, 255, 0 + vgmh %v15, 0, 0 + vgmh %v31, 0, 0 + vgmh %v21, 2, 3 + +#CHECK: vl %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x06] +#CHECK: vl %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x06] +#CHECK: vl %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x06] +#CHECK: vl %v0, 0(%r15,%r1) # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x06] +#CHECK: vl %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x06] +#CHECK: vl %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x06] +#CHECK: vl %v18, 1383(%r3,%r4) # encoding: [0xe7,0x23,0x45,0x67,0x08,0x06] + + vl %v0, 0 + vl %v0, 4095 + vl %v0, 0(%r15) + vl %v0, 0(%r15,%r1) + vl %v15, 0 + vl %v31, 0 + vl %v18, 0x567(%r3,%r4) + +#CHECK: vlbb %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x07] +#CHECK: vlbb %v0, 0, 15 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x07] +#CHECK: vlbb %v0, 4095, 0 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x07] +#CHECK: vlbb %v0, 0(%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x07] +#CHECK: vlbb %v0, 0(%r15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x07] +#CHECK: vlbb %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x07] +#CHECK: vlbb %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x07] +#CHECK: vlbb %v18, 1383(%r3,%r4), 8 # encoding: [0xe7,0x23,0x45,0x67,0x88,0x07] + + vlbb %v0, 0, 0 + vlbb %v0, 0, 15 + vlbb %v0, 4095, 0 + vlbb %v0, 0(%r15), 0 + vlbb %v0, 0(%r15,%r1), 0 + vlbb %v15, 0, 0 + vlbb %v31, 0, 0 + vlbb %v18, 1383(%r3,%r4), 8 + +#CHECK: vlcb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xde] +#CHECK: vlcb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xde] +#CHECK: vlcb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xde] +#CHECK: vlcb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xde] +#CHECK: vlcb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xde] +#CHECK: vlcb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xde] + + vlcb %v0, %v0 + vlcb %v0, %v15 + vlcb %v0, %v31 + vlcb %v15, %v0 + vlcb %v31, %v0 + vlcb %v14, %v17 + +#CHECK: vlcf %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xde] +#CHECK: vlcf %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xde] +#CHECK: vlcf %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xde] +#CHECK: vlcf %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xde] +#CHECK: vlcf %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xde] +#CHECK: vlcf %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xde] + + vlcf %v0, %v0 + vlcf %v0, %v15 + vlcf %v0, %v31 + vlcf %v15, %v0 + vlcf %v31, %v0 + vlcf %v14, %v17 + +#CHECK: vlcg %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xde] +#CHECK: vlcg %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0xde] +#CHECK: vlcg %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xde] +#CHECK: vlcg %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0xde] +#CHECK: vlcg %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xde] +#CHECK: vlcg %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x34,0xde] + + vlcg %v0, %v0 + vlcg %v0, %v15 + vlcg %v0, %v31 + vlcg %v15, %v0 + vlcg %v31, %v0 + vlcg %v14, %v17 + +#CHECK: vlch %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xde] +#CHECK: vlch %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0xde] +#CHECK: vlch %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xde] +#CHECK: vlch %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0xde] +#CHECK: vlch %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xde] +#CHECK: vlch %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x14,0xde] + + vlch %v0, %v0 + vlch %v0, %v15 + vlch %v0, %v31 + vlch %v15, %v0 + vlch %v31, %v0 + vlch %v14, %v17 + +#CHECK: vldeb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xc4] +#CHECK: vldeb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xc4] +#CHECK: vldeb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xc4] +#CHECK: vldeb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xc4] +#CHECK: vldeb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xc4] +#CHECK: vldeb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xc4] + + vldeb %v0, %v0 + vldeb %v0, %v15 + vldeb %v0, %v31 + vldeb %v15, %v0 + vldeb %v31, %v0 + vldeb %v14, %v17 + +#CHECK: vleb %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x00] +#CHECK: vleb %v0, 0, 15 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x00] +#CHECK: vleb %v0, 4095, 0 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x00] +#CHECK: vleb %v0, 0(%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x00] +#CHECK: vleb %v0, 0(%r15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x00] +#CHECK: vleb %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x00] +#CHECK: vleb %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x00] +#CHECK: vleb %v18, 1383(%r3,%r4), 8 # encoding: [0xe7,0x23,0x45,0x67,0x88,0x00] + + vleb %v0, 0, 0 + vleb %v0, 0, 15 + vleb %v0, 4095, 0 + vleb %v0, 0(%r15), 0 + vleb %v0, 0(%r15,%r1), 0 + vleb %v15, 0, 0 + vleb %v31, 0, 0 + vleb %v18, 1383(%r3,%r4), 8 + +#CHECK: vledb %v0, %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xc5] +#CHECK: vledb %v0, %v0, 0, 15 # encoding: [0xe7,0x00,0x00,0xf0,0x30,0xc5] +#CHECK: vledb %v0, %v0, 4, 0 # encoding: [0xe7,0x00,0x00,0x04,0x30,0xc5] +#CHECK: vledb %v0, %v0, 12, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc5] +#CHECK: vledb %v0, %v31, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xc5] +#CHECK: vledb %v31, %v0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xc5] +#CHECK: vledb %v14, %v17, 4, 10 # encoding: [0xe7,0xe1,0x00,0xa4,0x34,0xc5] + + vledb %v0, %v0, 0, 0 + vledb %v0, %v0, 0, 15 + vledb %v0, %v0, 4, 0 + vledb %v0, %v0, 12, 0 + vledb %v0, %v31, 0, 0 + vledb %v31, %v0, 0, 0 + vledb %v14, %v17, 4, 10 + +#CHECK: vlef %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x03] +#CHECK: vlef %v0, 0, 3 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x03] +#CHECK: vlef %v0, 4095, 0 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x03] +#CHECK: vlef %v0, 0(%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x03] +#CHECK: vlef %v0, 0(%r15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x03] +#CHECK: vlef %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x03] +#CHECK: vlef %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x03] +#CHECK: vlef %v18, 1383(%r3,%r4), 2 # encoding: [0xe7,0x23,0x45,0x67,0x28,0x03] + + vlef %v0, 0, 0 + vlef %v0, 0, 3 + vlef %v0, 4095, 0 + vlef %v0, 0(%r15), 0 + vlef %v0, 0(%r15,%r1), 0 + vlef %v15, 0, 0 + vlef %v31, 0, 0 + vlef %v18, 1383(%r3,%r4), 2 + +#CHECK: vleg %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x02] +#CHECK: vleg %v0, 0, 1 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x02] +#CHECK: vleg %v0, 4095, 0 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x02] +#CHECK: vleg %v0, 0(%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x02] +#CHECK: vleg %v0, 0(%r15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x02] +#CHECK: vleg %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x02] +#CHECK: vleg %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x02] +#CHECK: vleg %v18, 1383(%r3,%r4), 1 # encoding: [0xe7,0x23,0x45,0x67,0x18,0x02] + + vleg %v0, 0, 0 + vleg %v0, 0, 1 + vleg %v0, 4095, 0 + vleg %v0, 0(%r15), 0 + vleg %v0, 0(%r15,%r1), 0 + vleg %v15, 0, 0 + vleg %v31, 0, 0 + vleg %v18, 1383(%r3,%r4), 1 + +#CHECK: vleh %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x01] +#CHECK: vleh %v0, 0, 7 # encoding: [0xe7,0x00,0x00,0x00,0x70,0x01] +#CHECK: vleh %v0, 4095, 0 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x01] +#CHECK: vleh %v0, 0(%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x01] +#CHECK: vleh %v0, 0(%r15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x01] +#CHECK: vleh %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x01] +#CHECK: vleh %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x01] +#CHECK: vleh %v18, 1383(%r3,%r4), 4 # encoding: [0xe7,0x23,0x45,0x67,0x48,0x01] + + vleh %v0, 0, 0 + vleh %v0, 0, 7 + vleh %v0, 4095, 0 + vleh %v0, 0(%r15), 0 + vleh %v0, 0(%r15,%r1), 0 + vleh %v15, 0, 0 + vleh %v31, 0, 0 + vleh %v18, 1383(%r3,%r4), 4 + +#CHECK: vleib %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x40] +#CHECK: vleib %v0, 0, 15 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x40] +#CHECK: vleib %v0, -32768, 0 # encoding: [0xe7,0x00,0x80,0x00,0x00,0x40] +#CHECK: vleib %v0, 32767, 0 # encoding: [0xe7,0x00,0x7f,0xff,0x00,0x40] +#CHECK: vleib %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x40] +#CHECK: vleib %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x40] +#CHECK: vleib %v18, 13398, 11 # encoding: [0xe7,0x20,0x34,0x56,0xb8,0x40] + + vleib %v0, 0, 0 + vleib %v0, 0, 15 + vleib %v0, -32768, 0 + vleib %v0, 32767, 0 + vleib %v15, 0, 0 + vleib %v31, 0, 0 + vleib %v18, 0x3456, 11 + +#CHECK: vleif %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x43] +#CHECK: vleif %v0, 0, 3 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x43] +#CHECK: vleif %v0, -32768, 0 # encoding: [0xe7,0x00,0x80,0x00,0x00,0x43] +#CHECK: vleif %v0, 32767, 0 # encoding: [0xe7,0x00,0x7f,0xff,0x00,0x43] +#CHECK: vleif %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x43] +#CHECK: vleif %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x43] +#CHECK: vleif %v18, 13398, 3 # encoding: [0xe7,0x20,0x34,0x56,0x38,0x43] + + vleif %v0, 0, 0 + vleif %v0, 0, 3 + vleif %v0, -32768, 0 + vleif %v0, 32767, 0 + vleif %v15, 0, 0 + vleif %v31, 0, 0 + vleif %v18, 0x3456, 3 + +#CHECK: vleig %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x42] +#CHECK: vleig %v0, 0, 1 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x42] +#CHECK: vleig %v0, -32768, 0 # encoding: [0xe7,0x00,0x80,0x00,0x00,0x42] +#CHECK: vleig %v0, 32767, 0 # encoding: [0xe7,0x00,0x7f,0xff,0x00,0x42] +#CHECK: vleig %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x42] +#CHECK: vleig %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x42] +#CHECK: vleig %v18, 13398, 1 # encoding: [0xe7,0x20,0x34,0x56,0x18,0x42] + + vleig %v0, 0, 0 + vleig %v0, 0, 1 + vleig %v0, -32768, 0 + vleig %v0, 32767, 0 + vleig %v15, 0, 0 + vleig %v31, 0, 0 + vleig %v18, 0x3456, 1 + +#CHECK: vleih %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x41] +#CHECK: vleih %v0, 0, 7 # encoding: [0xe7,0x00,0x00,0x00,0x70,0x41] +#CHECK: vleih %v0, -32768, 0 # encoding: [0xe7,0x00,0x80,0x00,0x00,0x41] +#CHECK: vleih %v0, 32767, 0 # encoding: [0xe7,0x00,0x7f,0xff,0x00,0x41] +#CHECK: vleih %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x41] +#CHECK: vleih %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x41] +#CHECK: vleih %v18, 13398, 7 # encoding: [0xe7,0x20,0x34,0x56,0x78,0x41] + + vleih %v0, 0, 0 + vleih %v0, 0, 7 + vleih %v0, -32768, 0 + vleih %v0, 32767, 0 + vleih %v15, 0, 0 + vleih %v31, 0, 0 + vleih %v18, 0x3456, 7 + +#CHECK: vlgvb %r0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x21] +#CHECK: vlgvb %r0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x21] +#CHECK: vlgvb %r0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x21] +#CHECK: vlgvb %r0, %v15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x21] +#CHECK: vlgvb %r0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x21] +#CHECK: vlgvb %r15, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x21] +#CHECK: vlgvb %r2, %v19, 1383(%r4) # encoding: [0xe7,0x23,0x45,0x67,0x04,0x21] + + vlgvb %r0, %v0, 0 + vlgvb %r0, %v0, 4095 + vlgvb %r0, %v0, 0(%r15) + vlgvb %r0, %v15, 0 + vlgvb %r0, %v31, 0 + vlgvb %r15, %v0, 0 + vlgvb %r2, %v19, 1383(%r4) + +#CHECK: vlgvf %r0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x21] +#CHECK: vlgvf %r0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x21] +#CHECK: vlgvf %r0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x21] +#CHECK: vlgvf %r0, %v15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x21] +#CHECK: vlgvf %r0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x21] +#CHECK: vlgvf %r15, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x21] +#CHECK: vlgvf %r2, %v19, 1383(%r4) # encoding: [0xe7,0x23,0x45,0x67,0x24,0x21] + + vlgvf %r0, %v0, 0 + vlgvf %r0, %v0, 4095 + vlgvf %r0, %v0, 0(%r15) + vlgvf %r0, %v15, 0 + vlgvf %r0, %v31, 0 + vlgvf %r15, %v0, 0 + vlgvf %r2, %v19, 1383(%r4) + +#CHECK: vlgvg %r0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x21] +#CHECK: vlgvg %r0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x30,0x21] +#CHECK: vlgvg %r0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x21] +#CHECK: vlgvg %r0, %v15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x21] +#CHECK: vlgvg %r0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x21] +#CHECK: vlgvg %r15, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x21] +#CHECK: vlgvg %r2, %v19, 1383(%r4) # encoding: [0xe7,0x23,0x45,0x67,0x34,0x21] + + vlgvg %r0, %v0, 0 + vlgvg %r0, %v0, 4095 + vlgvg %r0, %v0, 0(%r15) + vlgvg %r0, %v15, 0 + vlgvg %r0, %v31, 0 + vlgvg %r15, %v0, 0 + vlgvg %r2, %v19, 1383(%r4) + +#CHECK: vlgvh %r0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x21] +#CHECK: vlgvh %r0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x10,0x21] +#CHECK: vlgvh %r0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x21] +#CHECK: vlgvh %r0, %v15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x21] +#CHECK: vlgvh %r0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x21] +#CHECK: vlgvh %r15, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x21] +#CHECK: vlgvh %r2, %v19, 1383(%r4) # encoding: [0xe7,0x23,0x45,0x67,0x14,0x21] + + vlgvh %r0, %v0, 0 + vlgvh %r0, %v0, 4095 + vlgvh %r0, %v0, 0(%r15) + vlgvh %r0, %v15, 0 + vlgvh %r0, %v31, 0 + vlgvh %r15, %v0, 0 + vlgvh %r2, %v19, 1383(%r4) + +#CHECK: vll %v0, %r0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x37] +#CHECK: vll %v0, %r0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x37] +#CHECK: vll %v0, %r0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x37] +#CHECK: vll %v0, %r15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x37] +#CHECK: vll %v15, %r0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x37] +#CHECK: vll %v31, %r0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x37] +#CHECK: vll %v18, %r3, 1383(%r4) # encoding: [0xe7,0x23,0x45,0x67,0x08,0x37] + + vll %v0, %r0, 0 + vll %v0, %r0, 4095 + vll %v0, %r0, 0(%r15) + vll %v0, %r15, 0 + vll %v15, %r0, 0 + vll %v31, %r0, 0 + vll %v18, %r3, 1383(%r4) + +#CHECK: vllezb %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x04] +#CHECK: vllezb %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x04] +#CHECK: vllezb %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x04] +#CHECK: vllezb %v0, 0(%r15,%r1) # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x04] +#CHECK: vllezb %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x04] +#CHECK: vllezb %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x04] +#CHECK: vllezb %v18, 1383(%r3,%r4) # encoding: [0xe7,0x23,0x45,0x67,0x08,0x04] + + vllezb %v0, 0 + vllezb %v0, 4095 + vllezb %v0, 0(%r15) + vllezb %v0, 0(%r15,%r1) + vllezb %v15, 0 + vllezb %v31, 0 + vllezb %v18, 0x567(%r3,%r4) + +#CHECK: vllezf %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x04] +#CHECK: vllezf %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x04] +#CHECK: vllezf %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x04] +#CHECK: vllezf %v0, 0(%r15,%r1) # encoding: [0xe7,0x0f,0x10,0x00,0x20,0x04] +#CHECK: vllezf %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x04] +#CHECK: vllezf %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x04] +#CHECK: vllezf %v18, 1383(%r3,%r4) # encoding: [0xe7,0x23,0x45,0x67,0x28,0x04] + + vllezf %v0, 0 + vllezf %v0, 4095 + vllezf %v0, 0(%r15) + vllezf %v0, 0(%r15,%r1) + vllezf %v15, 0 + vllezf %v31, 0 + vllezf %v18, 0x567(%r3,%r4) + +#CHECK: vllezg %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x04] +#CHECK: vllezg %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x30,0x04] +#CHECK: vllezg %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x04] +#CHECK: vllezg %v0, 0(%r15,%r1) # encoding: [0xe7,0x0f,0x10,0x00,0x30,0x04] +#CHECK: vllezg %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x04] +#CHECK: vllezg %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x04] +#CHECK: vllezg %v18, 1383(%r3,%r4) # encoding: [0xe7,0x23,0x45,0x67,0x38,0x04] + + vllezg %v0, 0 + vllezg %v0, 4095 + vllezg %v0, 0(%r15) + vllezg %v0, 0(%r15,%r1) + vllezg %v15, 0 + vllezg %v31, 0 + vllezg %v18, 0x567(%r3,%r4) + +#CHECK: vllezh %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x04] +#CHECK: vllezh %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x10,0x04] +#CHECK: vllezh %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x04] +#CHECK: vllezh %v0, 0(%r15,%r1) # encoding: [0xe7,0x0f,0x10,0x00,0x10,0x04] +#CHECK: vllezh %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x04] +#CHECK: vllezh %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x04] +#CHECK: vllezh %v18, 1383(%r3,%r4) # encoding: [0xe7,0x23,0x45,0x67,0x18,0x04] + + vllezh %v0, 0 + vllezh %v0, 4095 + vllezh %v0, 0(%r15) + vllezh %v0, 0(%r15,%r1) + vllezh %v15, 0 + vllezh %v31, 0 + vllezh %v18, 0x567(%r3,%r4) + +#CHECK: vlm %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x36] +#CHECK: vlm %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x36] +#CHECK: vlm %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x36] +#CHECK: vlm %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x36] +#CHECK: vlm %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x36] +#CHECK: vlm %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x04,0x36] + + vlm %v0, %v0, 0 + vlm %v0, %v0, 4095 + vlm %v0, %v0, 0(%r15) + vlm %v0, %v31, 0 + vlm %v31, %v0, 0 + vlm %v14, %v17, 1074(%r5) + +#CHECK: vlpb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xdf] +#CHECK: vlpb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xdf] +#CHECK: vlpb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xdf] +#CHECK: vlpb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xdf] +#CHECK: vlpb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xdf] +#CHECK: vlpb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xdf] + + vlpb %v0, %v0 + vlpb %v0, %v15 + vlpb %v0, %v31 + vlpb %v15, %v0 + vlpb %v31, %v0 + vlpb %v14, %v17 + +#CHECK: vlpf %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xdf] +#CHECK: vlpf %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xdf] +#CHECK: vlpf %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xdf] +#CHECK: vlpf %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xdf] +#CHECK: vlpf %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xdf] +#CHECK: vlpf %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xdf] + + vlpf %v0, %v0 + vlpf %v0, %v15 + vlpf %v0, %v31 + vlpf %v15, %v0 + vlpf %v31, %v0 + vlpf %v14, %v17 + +#CHECK: vlpg %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xdf] +#CHECK: vlpg %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0xdf] +#CHECK: vlpg %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xdf] +#CHECK: vlpg %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0xdf] +#CHECK: vlpg %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xdf] +#CHECK: vlpg %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x34,0xdf] + + vlpg %v0, %v0 + vlpg %v0, %v15 + vlpg %v0, %v31 + vlpg %v15, %v0 + vlpg %v31, %v0 + vlpg %v14, %v17 + +#CHECK: vlph %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xdf] +#CHECK: vlph %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0xdf] +#CHECK: vlph %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xdf] +#CHECK: vlph %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0xdf] +#CHECK: vlph %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xdf] +#CHECK: vlph %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x14,0xdf] + + vlph %v0, %v0 + vlph %v0, %v15 + vlph %v0, %v31 + vlph %v15, %v0 + vlph %v31, %v0 + vlph %v14, %v17 + +#CHECK: vlr %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x56] +#CHECK: vlr %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x56] +#CHECK: vlr %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x56] +#CHECK: vlr %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x56] +#CHECK: vlr %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x56] +#CHECK: vlr %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0x56] + + vlr %v0, %v0 + vlr %v0, %v15 + vlr %v0, %v31 + vlr %v15, %v0 + vlr %v31, %v0 + vlr %v14, %v17 + +#CHECK: vlrepb %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x05] +#CHECK: vlrepb %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x05] +#CHECK: vlrepb %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x05] +#CHECK: vlrepb %v0, 0(%r15,%r1) # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x05] +#CHECK: vlrepb %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x05] +#CHECK: vlrepb %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x05] +#CHECK: vlrepb %v18, 1383(%r3,%r4) # encoding: [0xe7,0x23,0x45,0x67,0x08,0x05] + + vlrepb %v0, 0 + vlrepb %v0, 4095 + vlrepb %v0, 0(%r15) + vlrepb %v0, 0(%r15,%r1) + vlrepb %v15, 0 + vlrepb %v31, 0 + vlrepb %v18, 0x567(%r3,%r4) + +#CHECK: vlrepf %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x05] +#CHECK: vlrepf %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x05] +#CHECK: vlrepf %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x05] +#CHECK: vlrepf %v0, 0(%r15,%r1) # encoding: [0xe7,0x0f,0x10,0x00,0x20,0x05] +#CHECK: vlrepf %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x05] +#CHECK: vlrepf %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x05] +#CHECK: vlrepf %v18, 1383(%r3,%r4) # encoding: [0xe7,0x23,0x45,0x67,0x28,0x05] + + vlrepf %v0, 0 + vlrepf %v0, 4095 + vlrepf %v0, 0(%r15) + vlrepf %v0, 0(%r15,%r1) + vlrepf %v15, 0 + vlrepf %v31, 0 + vlrepf %v18, 0x567(%r3,%r4) + +#CHECK: vlrepg %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x05] +#CHECK: vlrepg %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x30,0x05] +#CHECK: vlrepg %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x05] +#CHECK: vlrepg %v0, 0(%r15,%r1) # encoding: [0xe7,0x0f,0x10,0x00,0x30,0x05] +#CHECK: vlrepg %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x05] +#CHECK: vlrepg %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x05] +#CHECK: vlrepg %v18, 1383(%r3,%r4) # encoding: [0xe7,0x23,0x45,0x67,0x38,0x05] + + vlrepg %v0, 0 + vlrepg %v0, 4095 + vlrepg %v0, 0(%r15) + vlrepg %v0, 0(%r15,%r1) + vlrepg %v15, 0 + vlrepg %v31, 0 + vlrepg %v18, 0x567(%r3,%r4) + +#CHECK: vlreph %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x05] +#CHECK: vlreph %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x10,0x05] +#CHECK: vlreph %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x05] +#CHECK: vlreph %v0, 0(%r15,%r1) # encoding: [0xe7,0x0f,0x10,0x00,0x10,0x05] +#CHECK: vlreph %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x05] +#CHECK: vlreph %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x05] +#CHECK: vlreph %v18, 1383(%r3,%r4) # encoding: [0xe7,0x23,0x45,0x67,0x18,0x05] + + vlreph %v0, 0 + vlreph %v0, 4095 + vlreph %v0, 0(%r15) + vlreph %v0, 0(%r15,%r1) + vlreph %v15, 0 + vlreph %v31, 0 + vlreph %v18, 0x567(%r3,%r4) + +#CHECK: vlvgb %v0, %r0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x22] +#CHECK: vlvgb %v0, %r0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x22] +#CHECK: vlvgb %v0, %r0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x22] +#CHECK: vlvgb %v0, %r15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x22] +#CHECK: vlvgb %v15, %r0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x22] +#CHECK: vlvgb %v31, %r0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x22] +#CHECK: vlvgb %v18, %r3, 1383(%r4) # encoding: [0xe7,0x23,0x45,0x67,0x08,0x22] + + vlvgb %v0, %r0, 0 + vlvgb %v0, %r0, 4095 + vlvgb %v0, %r0, 0(%r15) + vlvgb %v0, %r15, 0 + vlvgb %v15, %r0, 0 + vlvgb %v31, %r0, 0 + vlvgb %v18, %r3, 1383(%r4) + +#CHECK: vlvgf %v0, %r0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x22] +#CHECK: vlvgf %v0, %r0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x22] +#CHECK: vlvgf %v0, %r0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x22] +#CHECK: vlvgf %v0, %r15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x22] +#CHECK: vlvgf %v15, %r0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x22] +#CHECK: vlvgf %v31, %r0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x22] +#CHECK: vlvgf %v18, %r3, 1383(%r4) # encoding: [0xe7,0x23,0x45,0x67,0x28,0x22] + + vlvgf %v0, %r0, 0 + vlvgf %v0, %r0, 4095 + vlvgf %v0, %r0, 0(%r15) + vlvgf %v0, %r15, 0 + vlvgf %v15, %r0, 0 + vlvgf %v31, %r0, 0 + vlvgf %v18, %r3, 1383(%r4) + +#CHECK: vlvgg %v0, %r0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x22] +#CHECK: vlvgg %v0, %r0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x30,0x22] +#CHECK: vlvgg %v0, %r0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x22] +#CHECK: vlvgg %v0, %r15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x22] +#CHECK: vlvgg %v15, %r0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x22] +#CHECK: vlvgg %v31, %r0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x22] +#CHECK: vlvgg %v18, %r3, 1383(%r4) # encoding: [0xe7,0x23,0x45,0x67,0x38,0x22] + + vlvgg %v0, %r0, 0 + vlvgg %v0, %r0, 4095 + vlvgg %v0, %r0, 0(%r15) + vlvgg %v0, %r15, 0 + vlvgg %v15, %r0, 0 + vlvgg %v31, %r0, 0 + vlvgg %v18, %r3, 1383(%r4) + +#CHECK: vlvgh %v0, %r0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x22] +#CHECK: vlvgh %v0, %r0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x10,0x22] +#CHECK: vlvgh %v0, %r0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x22] +#CHECK: vlvgh %v0, %r15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x22] +#CHECK: vlvgh %v15, %r0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x22] +#CHECK: vlvgh %v31, %r0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x22] +#CHECK: vlvgh %v18, %r3, 1383(%r4) # encoding: [0xe7,0x23,0x45,0x67,0x18,0x22] + + vlvgh %v0, %r0, 0 + vlvgh %v0, %r0, 4095 + vlvgh %v0, %r0, 0(%r15) + vlvgh %v0, %r15, 0 + vlvgh %v15, %r0, 0 + vlvgh %v31, %r0, 0 + vlvgh %v18, %r3, 1383(%r4) + +#CHECK: vlvgp %v0, %r0, %r0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x62] +#CHECK: vlvgp %v0, %r0, %r15 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x62] +#CHECK: vlvgp %v0, %r15, %r0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x62] +#CHECK: vlvgp %v15, %r0, %r0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x62] +#CHECK: vlvgp %v31, %r0, %r0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x62] +#CHECK: vlvgp %v18, %r3, %r4 # encoding: [0xe7,0x23,0x40,0x00,0x08,0x62] + + vlvgp %v0, %r0, %r0 + vlvgp %v0, %r0, %r15 + vlvgp %v0, %r15, %r0 + vlvgp %v15, %r0, %r0 + vlvgp %v31, %r0, %r0 + vlvgp %v18, %r3, %r4 + +#CHECK: vmaeb %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xae] +#CHECK: vmaeb %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xae] +#CHECK: vmaeb %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xae] +#CHECK: vmaeb %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xae] +#CHECK: vmaeb %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xae] +#CHECK: vmaeb %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x50,0x00,0x97,0xae] + + vmaeb %v0, %v0, %v0, %v0 + vmaeb %v0, %v0, %v0, %v31 + vmaeb %v0, %v0, %v31, %v0 + vmaeb %v0, %v31, %v0, %v0 + vmaeb %v31, %v0, %v0, %v0 + vmaeb %v13, %v17, %v21, %v25 + +#CHECK: vmaef %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x02,0x00,0x00,0xae] +#CHECK: vmaef %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x02,0x00,0xf1,0xae] +#CHECK: vmaef %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf2,0x00,0x02,0xae] +#CHECK: vmaef %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x02,0x00,0x04,0xae] +#CHECK: vmaef %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x02,0x00,0x08,0xae] +#CHECK: vmaef %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x52,0x00,0x97,0xae] + + vmaef %v0, %v0, %v0, %v0 + vmaef %v0, %v0, %v0, %v31 + vmaef %v0, %v0, %v31, %v0 + vmaef %v0, %v31, %v0, %v0 + vmaef %v31, %v0, %v0, %v0 + vmaef %v13, %v17, %v21, %v25 + +#CHECK: vmaeh %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x01,0x00,0x00,0xae] +#CHECK: vmaeh %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x01,0x00,0xf1,0xae] +#CHECK: vmaeh %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf1,0x00,0x02,0xae] +#CHECK: vmaeh %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x01,0x00,0x04,0xae] +#CHECK: vmaeh %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x01,0x00,0x08,0xae] +#CHECK: vmaeh %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x51,0x00,0x97,0xae] + + vmaeh %v0, %v0, %v0, %v0 + vmaeh %v0, %v0, %v0, %v31 + vmaeh %v0, %v0, %v31, %v0 + vmaeh %v0, %v31, %v0, %v0 + vmaeh %v31, %v0, %v0, %v0 + vmaeh %v13, %v17, %v21, %v25 + +#CHECK: vmahb %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xab] +#CHECK: vmahb %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xab] +#CHECK: vmahb %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xab] +#CHECK: vmahb %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xab] +#CHECK: vmahb %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xab] +#CHECK: vmahb %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x50,0x00,0x97,0xab] + + vmahb %v0, %v0, %v0, %v0 + vmahb %v0, %v0, %v0, %v31 + vmahb %v0, %v0, %v31, %v0 + vmahb %v0, %v31, %v0, %v0 + vmahb %v31, %v0, %v0, %v0 + vmahb %v13, %v17, %v21, %v25 + +#CHECK: vmahf %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x02,0x00,0x00,0xab] +#CHECK: vmahf %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x02,0x00,0xf1,0xab] +#CHECK: vmahf %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf2,0x00,0x02,0xab] +#CHECK: vmahf %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x02,0x00,0x04,0xab] +#CHECK: vmahf %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x02,0x00,0x08,0xab] +#CHECK: vmahf %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x52,0x00,0x97,0xab] + + vmahf %v0, %v0, %v0, %v0 + vmahf %v0, %v0, %v0, %v31 + vmahf %v0, %v0, %v31, %v0 + vmahf %v0, %v31, %v0, %v0 + vmahf %v31, %v0, %v0, %v0 + vmahf %v13, %v17, %v21, %v25 + +#CHECK: vmahh %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x01,0x00,0x00,0xab] +#CHECK: vmahh %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x01,0x00,0xf1,0xab] +#CHECK: vmahh %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf1,0x00,0x02,0xab] +#CHECK: vmahh %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x01,0x00,0x04,0xab] +#CHECK: vmahh %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x01,0x00,0x08,0xab] +#CHECK: vmahh %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x51,0x00,0x97,0xab] + + vmahh %v0, %v0, %v0, %v0 + vmahh %v0, %v0, %v0, %v31 + vmahh %v0, %v0, %v31, %v0 + vmahh %v0, %v31, %v0, %v0 + vmahh %v31, %v0, %v0, %v0 + vmahh %v13, %v17, %v21, %v25 + +#CHECK: vmalb %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xaa] +#CHECK: vmalb %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xaa] +#CHECK: vmalb %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xaa] +#CHECK: vmalb %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xaa] +#CHECK: vmalb %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xaa] +#CHECK: vmalb %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x50,0x00,0x97,0xaa] + + vmalb %v0, %v0, %v0, %v0 + vmalb %v0, %v0, %v0, %v31 + vmalb %v0, %v0, %v31, %v0 + vmalb %v0, %v31, %v0, %v0 + vmalb %v31, %v0, %v0, %v0 + vmalb %v13, %v17, %v21, %v25 + +#CHECK: vmaleb %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xac] +#CHECK: vmaleb %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xac] +#CHECK: vmaleb %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xac] +#CHECK: vmaleb %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xac] +#CHECK: vmaleb %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xac] +#CHECK: vmaleb %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x50,0x00,0x97,0xac] + + vmaleb %v0, %v0, %v0, %v0 + vmaleb %v0, %v0, %v0, %v31 + vmaleb %v0, %v0, %v31, %v0 + vmaleb %v0, %v31, %v0, %v0 + vmaleb %v31, %v0, %v0, %v0 + vmaleb %v13, %v17, %v21, %v25 + +#CHECK: vmalef %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x02,0x00,0x00,0xac] +#CHECK: vmalef %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x02,0x00,0xf1,0xac] +#CHECK: vmalef %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf2,0x00,0x02,0xac] +#CHECK: vmalef %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x02,0x00,0x04,0xac] +#CHECK: vmalef %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x02,0x00,0x08,0xac] +#CHECK: vmalef %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x52,0x00,0x97,0xac] + + vmalef %v0, %v0, %v0, %v0 + vmalef %v0, %v0, %v0, %v31 + vmalef %v0, %v0, %v31, %v0 + vmalef %v0, %v31, %v0, %v0 + vmalef %v31, %v0, %v0, %v0 + vmalef %v13, %v17, %v21, %v25 + +#CHECK: vmaleh %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x01,0x00,0x00,0xac] +#CHECK: vmaleh %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x01,0x00,0xf1,0xac] +#CHECK: vmaleh %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf1,0x00,0x02,0xac] +#CHECK: vmaleh %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x01,0x00,0x04,0xac] +#CHECK: vmaleh %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x01,0x00,0x08,0xac] +#CHECK: vmaleh %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x51,0x00,0x97,0xac] + + vmaleh %v0, %v0, %v0, %v0 + vmaleh %v0, %v0, %v0, %v31 + vmaleh %v0, %v0, %v31, %v0 + vmaleh %v0, %v31, %v0, %v0 + vmaleh %v31, %v0, %v0, %v0 + vmaleh %v13, %v17, %v21, %v25 + +#CHECK: vmalf %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x02,0x00,0x00,0xaa] +#CHECK: vmalf %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x02,0x00,0xf1,0xaa] +#CHECK: vmalf %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf2,0x00,0x02,0xaa] +#CHECK: vmalf %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x02,0x00,0x04,0xaa] +#CHECK: vmalf %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x02,0x00,0x08,0xaa] +#CHECK: vmalf %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x52,0x00,0x97,0xaa] + + vmalf %v0, %v0, %v0, %v0 + vmalf %v0, %v0, %v0, %v31 + vmalf %v0, %v0, %v31, %v0 + vmalf %v0, %v31, %v0, %v0 + vmalf %v31, %v0, %v0, %v0 + vmalf %v13, %v17, %v21, %v25 + +#CHECK: vmalhb %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xa9] +#CHECK: vmalhb %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xa9] +#CHECK: vmalhb %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xa9] +#CHECK: vmalhb %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xa9] +#CHECK: vmalhb %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xa9] +#CHECK: vmalhb %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x50,0x00,0x97,0xa9] + + vmalhb %v0, %v0, %v0, %v0 + vmalhb %v0, %v0, %v0, %v31 + vmalhb %v0, %v0, %v31, %v0 + vmalhb %v0, %v31, %v0, %v0 + vmalhb %v31, %v0, %v0, %v0 + vmalhb %v13, %v17, %v21, %v25 + +#CHECK: vmalhf %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x02,0x00,0x00,0xa9] +#CHECK: vmalhf %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x02,0x00,0xf1,0xa9] +#CHECK: vmalhf %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf2,0x00,0x02,0xa9] +#CHECK: vmalhf %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x02,0x00,0x04,0xa9] +#CHECK: vmalhf %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x02,0x00,0x08,0xa9] +#CHECK: vmalhf %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x52,0x00,0x97,0xa9] + + vmalhf %v0, %v0, %v0, %v0 + vmalhf %v0, %v0, %v0, %v31 + vmalhf %v0, %v0, %v31, %v0 + vmalhf %v0, %v31, %v0, %v0 + vmalhf %v31, %v0, %v0, %v0 + vmalhf %v13, %v17, %v21, %v25 + +#CHECK: vmalhh %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x01,0x00,0x00,0xa9] +#CHECK: vmalhh %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x01,0x00,0xf1,0xa9] +#CHECK: vmalhh %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf1,0x00,0x02,0xa9] +#CHECK: vmalhh %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x01,0x00,0x04,0xa9] +#CHECK: vmalhh %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x01,0x00,0x08,0xa9] +#CHECK: vmalhh %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x51,0x00,0x97,0xa9] + + vmalhh %v0, %v0, %v0, %v0 + vmalhh %v0, %v0, %v0, %v31 + vmalhh %v0, %v0, %v31, %v0 + vmalhh %v0, %v31, %v0, %v0 + vmalhh %v31, %v0, %v0, %v0 + vmalhh %v13, %v17, %v21, %v25 + +#CHECK: vmalhw %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x01,0x00,0x00,0xaa] +#CHECK: vmalhw %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x01,0x00,0xf1,0xaa] +#CHECK: vmalhw %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf1,0x00,0x02,0xaa] +#CHECK: vmalhw %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x01,0x00,0x04,0xaa] +#CHECK: vmalhw %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x01,0x00,0x08,0xaa] +#CHECK: vmalhw %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x51,0x00,0x97,0xaa] + + vmalhw %v0, %v0, %v0, %v0 + vmalhw %v0, %v0, %v0, %v31 + vmalhw %v0, %v0, %v31, %v0 + vmalhw %v0, %v31, %v0, %v0 + vmalhw %v31, %v0, %v0, %v0 + vmalhw %v13, %v17, %v21, %v25 + +#CHECK: vmalob %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xad] +#CHECK: vmalob %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xad] +#CHECK: vmalob %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xad] +#CHECK: vmalob %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xad] +#CHECK: vmalob %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xad] +#CHECK: vmalob %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x50,0x00,0x97,0xad] + + vmalob %v0, %v0, %v0, %v0 + vmalob %v0, %v0, %v0, %v31 + vmalob %v0, %v0, %v31, %v0 + vmalob %v0, %v31, %v0, %v0 + vmalob %v31, %v0, %v0, %v0 + vmalob %v13, %v17, %v21, %v25 + +#CHECK: vmalof %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x02,0x00,0x00,0xad] +#CHECK: vmalof %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x02,0x00,0xf1,0xad] +#CHECK: vmalof %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf2,0x00,0x02,0xad] +#CHECK: vmalof %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x02,0x00,0x04,0xad] +#CHECK: vmalof %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x02,0x00,0x08,0xad] +#CHECK: vmalof %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x52,0x00,0x97,0xad] + + vmalof %v0, %v0, %v0, %v0 + vmalof %v0, %v0, %v0, %v31 + vmalof %v0, %v0, %v31, %v0 + vmalof %v0, %v31, %v0, %v0 + vmalof %v31, %v0, %v0, %v0 + vmalof %v13, %v17, %v21, %v25 + +#CHECK: vmaloh %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x01,0x00,0x00,0xad] +#CHECK: vmaloh %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x01,0x00,0xf1,0xad] +#CHECK: vmaloh %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf1,0x00,0x02,0xad] +#CHECK: vmaloh %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x01,0x00,0x04,0xad] +#CHECK: vmaloh %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x01,0x00,0x08,0xad] +#CHECK: vmaloh %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x51,0x00,0x97,0xad] + + vmaloh %v0, %v0, %v0, %v0 + vmaloh %v0, %v0, %v0, %v31 + vmaloh %v0, %v0, %v31, %v0 + vmaloh %v0, %v31, %v0, %v0 + vmaloh %v31, %v0, %v0, %v0 + vmaloh %v13, %v17, %v21, %v25 + +#CHECK: vmaob %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xaf] +#CHECK: vmaob %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xaf] +#CHECK: vmaob %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xaf] +#CHECK: vmaob %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xaf] +#CHECK: vmaob %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xaf] +#CHECK: vmaob %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x50,0x00,0x97,0xaf] + + vmaob %v0, %v0, %v0, %v0 + vmaob %v0, %v0, %v0, %v31 + vmaob %v0, %v0, %v31, %v0 + vmaob %v0, %v31, %v0, %v0 + vmaob %v31, %v0, %v0, %v0 + vmaob %v13, %v17, %v21, %v25 + +#CHECK: vmaof %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x02,0x00,0x00,0xaf] +#CHECK: vmaof %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x02,0x00,0xf1,0xaf] +#CHECK: vmaof %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf2,0x00,0x02,0xaf] +#CHECK: vmaof %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x02,0x00,0x04,0xaf] +#CHECK: vmaof %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x02,0x00,0x08,0xaf] +#CHECK: vmaof %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x52,0x00,0x97,0xaf] + + vmaof %v0, %v0, %v0, %v0 + vmaof %v0, %v0, %v0, %v31 + vmaof %v0, %v0, %v31, %v0 + vmaof %v0, %v31, %v0, %v0 + vmaof %v31, %v0, %v0, %v0 + vmaof %v13, %v17, %v21, %v25 + +#CHECK: vmaoh %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x01,0x00,0x00,0xaf] +#CHECK: vmaoh %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x01,0x00,0xf1,0xaf] +#CHECK: vmaoh %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf1,0x00,0x02,0xaf] +#CHECK: vmaoh %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x01,0x00,0x04,0xaf] +#CHECK: vmaoh %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x01,0x00,0x08,0xaf] +#CHECK: vmaoh %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x51,0x00,0x97,0xaf] + + vmaoh %v0, %v0, %v0, %v0 + vmaoh %v0, %v0, %v0, %v31 + vmaoh %v0, %v0, %v31, %v0 + vmaoh %v0, %v31, %v0, %v0 + vmaoh %v31, %v0, %v0, %v0 + vmaoh %v13, %v17, %v21, %v25 + +#CHECK: vmeb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xa6] +#CHECK: vmeb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xa6] +#CHECK: vmeb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xa6] +#CHECK: vmeb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xa6] +#CHECK: vmeb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xa6] + + vmeb %v0, %v0, %v0 + vmeb %v0, %v0, %v31 + vmeb %v0, %v31, %v0 + vmeb %v31, %v0, %v0 + vmeb %v18, %v3, %v20 + +#CHECK: vmef %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xa6] +#CHECK: vmef %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xa6] +#CHECK: vmef %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xa6] +#CHECK: vmef %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xa6] +#CHECK: vmef %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xa6] + + vmef %v0, %v0, %v0 + vmef %v0, %v0, %v31 + vmef %v0, %v31, %v0 + vmef %v31, %v0, %v0 + vmef %v18, %v3, %v20 + +#CHECK: vmeh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xa6] +#CHECK: vmeh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xa6] +#CHECK: vmeh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xa6] +#CHECK: vmeh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xa6] +#CHECK: vmeh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xa6] + + vmeh %v0, %v0, %v0 + vmeh %v0, %v0, %v31 + vmeh %v0, %v31, %v0 + vmeh %v31, %v0, %v0 + vmeh %v18, %v3, %v20 + +#CHECK: vmhb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xa3] +#CHECK: vmhb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xa3] +#CHECK: vmhb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xa3] +#CHECK: vmhb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xa3] +#CHECK: vmhb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xa3] + + vmhb %v0, %v0, %v0 + vmhb %v0, %v0, %v31 + vmhb %v0, %v31, %v0 + vmhb %v31, %v0, %v0 + vmhb %v18, %v3, %v20 + +#CHECK: vmhf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xa3] +#CHECK: vmhf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xa3] +#CHECK: vmhf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xa3] +#CHECK: vmhf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xa3] +#CHECK: vmhf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xa3] + + vmhf %v0, %v0, %v0 + vmhf %v0, %v0, %v31 + vmhf %v0, %v31, %v0 + vmhf %v31, %v0, %v0 + vmhf %v18, %v3, %v20 + +#CHECK: vmhh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xa3] +#CHECK: vmhh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xa3] +#CHECK: vmhh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xa3] +#CHECK: vmhh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xa3] +#CHECK: vmhh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xa3] + + vmhh %v0, %v0, %v0 + vmhh %v0, %v0, %v31 + vmhh %v0, %v31, %v0 + vmhh %v31, %v0, %v0 + vmhh %v18, %v3, %v20 + +#CHECK: vmlb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xa2] +#CHECK: vmlb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xa2] +#CHECK: vmlb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xa2] +#CHECK: vmlb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xa2] +#CHECK: vmlb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xa2] + + vmlb %v0, %v0, %v0 + vmlb %v0, %v0, %v31 + vmlb %v0, %v31, %v0 + vmlb %v31, %v0, %v0 + vmlb %v18, %v3, %v20 + +#CHECK: vmleb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xa4] +#CHECK: vmleb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xa4] +#CHECK: vmleb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xa4] +#CHECK: vmleb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xa4] +#CHECK: vmleb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xa4] + + vmleb %v0, %v0, %v0 + vmleb %v0, %v0, %v31 + vmleb %v0, %v31, %v0 + vmleb %v31, %v0, %v0 + vmleb %v18, %v3, %v20 + +#CHECK: vmlef %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xa4] +#CHECK: vmlef %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xa4] +#CHECK: vmlef %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xa4] +#CHECK: vmlef %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xa4] +#CHECK: vmlef %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xa4] + + vmlef %v0, %v0, %v0 + vmlef %v0, %v0, %v31 + vmlef %v0, %v31, %v0 + vmlef %v31, %v0, %v0 + vmlef %v18, %v3, %v20 + +#CHECK: vmleh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xa4] +#CHECK: vmleh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xa4] +#CHECK: vmleh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xa4] +#CHECK: vmleh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xa4] +#CHECK: vmleh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xa4] + + vmleh %v0, %v0, %v0 + vmleh %v0, %v0, %v31 + vmleh %v0, %v31, %v0 + vmleh %v31, %v0, %v0 + vmleh %v18, %v3, %v20 + +#CHECK: vmlf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xa2] +#CHECK: vmlf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xa2] +#CHECK: vmlf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xa2] +#CHECK: vmlf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xa2] +#CHECK: vmlf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xa2] + + vmlf %v0, %v0, %v0 + vmlf %v0, %v0, %v31 + vmlf %v0, %v31, %v0 + vmlf %v31, %v0, %v0 + vmlf %v18, %v3, %v20 + +#CHECK: vmlhb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xa1] +#CHECK: vmlhb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xa1] +#CHECK: vmlhb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xa1] +#CHECK: vmlhb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xa1] +#CHECK: vmlhb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xa1] + + vmlhb %v0, %v0, %v0 + vmlhb %v0, %v0, %v31 + vmlhb %v0, %v31, %v0 + vmlhb %v31, %v0, %v0 + vmlhb %v18, %v3, %v20 + +#CHECK: vmlhf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xa1] +#CHECK: vmlhf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xa1] +#CHECK: vmlhf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xa1] +#CHECK: vmlhf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xa1] +#CHECK: vmlhf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xa1] + + vmlhf %v0, %v0, %v0 + vmlhf %v0, %v0, %v31 + vmlhf %v0, %v31, %v0 + vmlhf %v31, %v0, %v0 + vmlhf %v18, %v3, %v20 + +#CHECK: vmlhh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xa1] +#CHECK: vmlhh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xa1] +#CHECK: vmlhh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xa1] +#CHECK: vmlhh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xa1] +#CHECK: vmlhh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xa1] + + vmlhh %v0, %v0, %v0 + vmlhh %v0, %v0, %v31 + vmlhh %v0, %v31, %v0 + vmlhh %v31, %v0, %v0 + vmlhh %v18, %v3, %v20 + +#CHECK: vmlhw %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xa2] +#CHECK: vmlhw %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xa2] +#CHECK: vmlhw %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xa2] +#CHECK: vmlhw %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xa2] +#CHECK: vmlhw %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xa2] + + vmlhw %v0, %v0, %v0 + vmlhw %v0, %v0, %v31 + vmlhw %v0, %v31, %v0 + vmlhw %v31, %v0, %v0 + vmlhw %v18, %v3, %v20 + +#CHECK: vmlob %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xa5] +#CHECK: vmlob %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xa5] +#CHECK: vmlob %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xa5] +#CHECK: vmlob %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xa5] +#CHECK: vmlob %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xa5] + + vmlob %v0, %v0, %v0 + vmlob %v0, %v0, %v31 + vmlob %v0, %v31, %v0 + vmlob %v31, %v0, %v0 + vmlob %v18, %v3, %v20 + +#CHECK: vmlof %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xa5] +#CHECK: vmlof %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xa5] +#CHECK: vmlof %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xa5] +#CHECK: vmlof %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xa5] +#CHECK: vmlof %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xa5] + + vmlof %v0, %v0, %v0 + vmlof %v0, %v0, %v31 + vmlof %v0, %v31, %v0 + vmlof %v31, %v0, %v0 + vmlof %v18, %v3, %v20 + +#CHECK: vmloh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xa5] +#CHECK: vmloh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xa5] +#CHECK: vmloh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xa5] +#CHECK: vmloh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xa5] +#CHECK: vmloh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xa5] + + vmloh %v0, %v0, %v0 + vmloh %v0, %v0, %v31 + vmloh %v0, %v31, %v0 + vmloh %v31, %v0, %v0 + vmloh %v18, %v3, %v20 + +#CHECK: vmnb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xfe] +#CHECK: vmnb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xfe] +#CHECK: vmnb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xfe] +#CHECK: vmnb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xfe] +#CHECK: vmnb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xfe] + + vmnb %v0, %v0, %v0 + vmnb %v0, %v0, %v31 + vmnb %v0, %v31, %v0 + vmnb %v31, %v0, %v0 + vmnb %v18, %v3, %v20 + +#CHECK: vmnf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xfe] +#CHECK: vmnf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xfe] +#CHECK: vmnf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xfe] +#CHECK: vmnf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xfe] +#CHECK: vmnf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xfe] + + vmnf %v0, %v0, %v0 + vmnf %v0, %v0, %v31 + vmnf %v0, %v31, %v0 + vmnf %v31, %v0, %v0 + vmnf %v18, %v3, %v20 + +#CHECK: vmng %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xfe] +#CHECK: vmng %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xfe] +#CHECK: vmng %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xfe] +#CHECK: vmng %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xfe] +#CHECK: vmng %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xfe] + + vmng %v0, %v0, %v0 + vmng %v0, %v0, %v31 + vmng %v0, %v31, %v0 + vmng %v31, %v0, %v0 + vmng %v18, %v3, %v20 + +#CHECK: vmnh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xfe] +#CHECK: vmnh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xfe] +#CHECK: vmnh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xfe] +#CHECK: vmnh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xfe] +#CHECK: vmnh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xfe] + + vmnh %v0, %v0, %v0 + vmnh %v0, %v0, %v31 + vmnh %v0, %v31, %v0 + vmnh %v31, %v0, %v0 + vmnh %v18, %v3, %v20 + +#CHECK: vmnlb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xfc] +#CHECK: vmnlb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xfc] +#CHECK: vmnlb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xfc] +#CHECK: vmnlb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xfc] +#CHECK: vmnlb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xfc] + + vmnlb %v0, %v0, %v0 + vmnlb %v0, %v0, %v31 + vmnlb %v0, %v31, %v0 + vmnlb %v31, %v0, %v0 + vmnlb %v18, %v3, %v20 + +#CHECK: vmnlf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xfc] +#CHECK: vmnlf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xfc] +#CHECK: vmnlf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xfc] +#CHECK: vmnlf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xfc] +#CHECK: vmnlf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xfc] + + vmnlf %v0, %v0, %v0 + vmnlf %v0, %v0, %v31 + vmnlf %v0, %v31, %v0 + vmnlf %v31, %v0, %v0 + vmnlf %v18, %v3, %v20 + +#CHECK: vmnlg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xfc] +#CHECK: vmnlg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xfc] +#CHECK: vmnlg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xfc] +#CHECK: vmnlg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xfc] +#CHECK: vmnlg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xfc] + + vmnlg %v0, %v0, %v0 + vmnlg %v0, %v0, %v31 + vmnlg %v0, %v31, %v0 + vmnlg %v31, %v0, %v0 + vmnlg %v18, %v3, %v20 + +#CHECK: vmnlh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xfc] +#CHECK: vmnlh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xfc] +#CHECK: vmnlh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xfc] +#CHECK: vmnlh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xfc] +#CHECK: vmnlh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xfc] + + vmnlh %v0, %v0, %v0 + vmnlh %v0, %v0, %v31 + vmnlh %v0, %v31, %v0 + vmnlh %v31, %v0, %v0 + vmnlh %v18, %v3, %v20 + +#CHECK: vmob %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xa7] +#CHECK: vmob %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xa7] +#CHECK: vmob %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xa7] +#CHECK: vmob %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xa7] +#CHECK: vmob %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xa7] + + vmob %v0, %v0, %v0 + vmob %v0, %v0, %v31 + vmob %v0, %v31, %v0 + vmob %v31, %v0, %v0 + vmob %v18, %v3, %v20 + +#CHECK: vmof %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xa7] +#CHECK: vmof %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xa7] +#CHECK: vmof %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xa7] +#CHECK: vmof %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xa7] +#CHECK: vmof %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xa7] + + vmof %v0, %v0, %v0 + vmof %v0, %v0, %v31 + vmof %v0, %v31, %v0 + vmof %v31, %v0, %v0 + vmof %v18, %v3, %v20 + +#CHECK: vmoh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xa7] +#CHECK: vmoh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xa7] +#CHECK: vmoh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xa7] +#CHECK: vmoh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xa7] +#CHECK: vmoh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xa7] + + vmoh %v0, %v0, %v0 + vmoh %v0, %v0, %v31 + vmoh %v0, %v31, %v0 + vmoh %v31, %v0, %v0 + vmoh %v18, %v3, %v20 + +#CHECK: vmrhb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x61] +#CHECK: vmrhb %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x61] +#CHECK: vmrhb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x61] +#CHECK: vmrhb %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x61] +#CHECK: vmrhb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x61] +#CHECK: vmrhb %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x61] +#CHECK: vmrhb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x61] +#CHECK: vmrhb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x61] + + vmrhb %v0, %v0, %v0 + vmrhb %v0, %v0, %v15 + vmrhb %v0, %v0, %v31 + vmrhb %v0, %v15, %v0 + vmrhb %v0, %v31, %v0 + vmrhb %v15, %v0, %v0 + vmrhb %v31, %v0, %v0 + vmrhb %v18, %v3, %v20 + +#CHECK: vmrhf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x61] +#CHECK: vmrhf %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x61] +#CHECK: vmrhf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x61] +#CHECK: vmrhf %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x61] +#CHECK: vmrhf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x61] +#CHECK: vmrhf %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x61] +#CHECK: vmrhf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x61] +#CHECK: vmrhf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x61] + + vmrhf %v0, %v0, %v0 + vmrhf %v0, %v0, %v15 + vmrhf %v0, %v0, %v31 + vmrhf %v0, %v15, %v0 + vmrhf %v0, %v31, %v0 + vmrhf %v15, %v0, %v0 + vmrhf %v31, %v0, %v0 + vmrhf %v18, %v3, %v20 + +#CHECK: vmrhg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x61] +#CHECK: vmrhg %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x61] +#CHECK: vmrhg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x61] +#CHECK: vmrhg %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x61] +#CHECK: vmrhg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x61] +#CHECK: vmrhg %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x61] +#CHECK: vmrhg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x61] +#CHECK: vmrhg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x61] + + vmrhg %v0, %v0, %v0 + vmrhg %v0, %v0, %v15 + vmrhg %v0, %v0, %v31 + vmrhg %v0, %v15, %v0 + vmrhg %v0, %v31, %v0 + vmrhg %v15, %v0, %v0 + vmrhg %v31, %v0, %v0 + vmrhg %v18, %v3, %v20 + +#CHECK: vmrhh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x61] +#CHECK: vmrhh %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x61] +#CHECK: vmrhh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x61] +#CHECK: vmrhh %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x61] +#CHECK: vmrhh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x61] +#CHECK: vmrhh %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x61] +#CHECK: vmrhh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x61] +#CHECK: vmrhh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x61] + + vmrhh %v0, %v0, %v0 + vmrhh %v0, %v0, %v15 + vmrhh %v0, %v0, %v31 + vmrhh %v0, %v15, %v0 + vmrhh %v0, %v31, %v0 + vmrhh %v15, %v0, %v0 + vmrhh %v31, %v0, %v0 + vmrhh %v18, %v3, %v20 + +#CHECK: vmrlb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x60] +#CHECK: vmrlb %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x60] +#CHECK: vmrlb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x60] +#CHECK: vmrlb %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x60] +#CHECK: vmrlb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x60] +#CHECK: vmrlb %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x60] +#CHECK: vmrlb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x60] +#CHECK: vmrlb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x60] + + vmrlb %v0, %v0, %v0 + vmrlb %v0, %v0, %v15 + vmrlb %v0, %v0, %v31 + vmrlb %v0, %v15, %v0 + vmrlb %v0, %v31, %v0 + vmrlb %v15, %v0, %v0 + vmrlb %v31, %v0, %v0 + vmrlb %v18, %v3, %v20 + +#CHECK: vmrlf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x60] +#CHECK: vmrlf %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x60] +#CHECK: vmrlf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x60] +#CHECK: vmrlf %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x60] +#CHECK: vmrlf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x60] +#CHECK: vmrlf %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x60] +#CHECK: vmrlf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x60] +#CHECK: vmrlf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x60] + + vmrlf %v0, %v0, %v0 + vmrlf %v0, %v0, %v15 + vmrlf %v0, %v0, %v31 + vmrlf %v0, %v15, %v0 + vmrlf %v0, %v31, %v0 + vmrlf %v15, %v0, %v0 + vmrlf %v31, %v0, %v0 + vmrlf %v18, %v3, %v20 + +#CHECK: vmrlg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x60] +#CHECK: vmrlg %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x60] +#CHECK: vmrlg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x60] +#CHECK: vmrlg %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x60] +#CHECK: vmrlg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x60] +#CHECK: vmrlg %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x60] +#CHECK: vmrlg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x60] +#CHECK: vmrlg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x60] + + vmrlg %v0, %v0, %v0 + vmrlg %v0, %v0, %v15 + vmrlg %v0, %v0, %v31 + vmrlg %v0, %v15, %v0 + vmrlg %v0, %v31, %v0 + vmrlg %v15, %v0, %v0 + vmrlg %v31, %v0, %v0 + vmrlg %v18, %v3, %v20 + +#CHECK: vmrlh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x60] +#CHECK: vmrlh %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x60] +#CHECK: vmrlh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x60] +#CHECK: vmrlh %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x60] +#CHECK: vmrlh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x60] +#CHECK: vmrlh %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x60] +#CHECK: vmrlh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x60] +#CHECK: vmrlh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x60] + + vmrlh %v0, %v0, %v0 + vmrlh %v0, %v0, %v15 + vmrlh %v0, %v0, %v31 + vmrlh %v0, %v15, %v0 + vmrlh %v0, %v31, %v0 + vmrlh %v15, %v0, %v0 + vmrlh %v31, %v0, %v0 + vmrlh %v18, %v3, %v20 + +#CHECK: vmxb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xff] +#CHECK: vmxb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xff] +#CHECK: vmxb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xff] +#CHECK: vmxb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xff] +#CHECK: vmxb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xff] + + vmxb %v0, %v0, %v0 + vmxb %v0, %v0, %v31 + vmxb %v0, %v31, %v0 + vmxb %v31, %v0, %v0 + vmxb %v18, %v3, %v20 + +#CHECK: vmxf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xff] +#CHECK: vmxf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xff] +#CHECK: vmxf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xff] +#CHECK: vmxf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xff] +#CHECK: vmxf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xff] + + vmxf %v0, %v0, %v0 + vmxf %v0, %v0, %v31 + vmxf %v0, %v31, %v0 + vmxf %v31, %v0, %v0 + vmxf %v18, %v3, %v20 + +#CHECK: vmxg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xff] +#CHECK: vmxg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xff] +#CHECK: vmxg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xff] +#CHECK: vmxg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xff] +#CHECK: vmxg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xff] + + vmxg %v0, %v0, %v0 + vmxg %v0, %v0, %v31 + vmxg %v0, %v31, %v0 + vmxg %v31, %v0, %v0 + vmxg %v18, %v3, %v20 + +#CHECK: vmxh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xff] +#CHECK: vmxh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xff] +#CHECK: vmxh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xff] +#CHECK: vmxh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xff] +#CHECK: vmxh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xff] + + vmxh %v0, %v0, %v0 + vmxh %v0, %v0, %v31 + vmxh %v0, %v31, %v0 + vmxh %v31, %v0, %v0 + vmxh %v18, %v3, %v20 + +#CHECK: vmxlb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xfd] +#CHECK: vmxlb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xfd] +#CHECK: vmxlb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xfd] +#CHECK: vmxlb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xfd] +#CHECK: vmxlb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xfd] + + vmxlb %v0, %v0, %v0 + vmxlb %v0, %v0, %v31 + vmxlb %v0, %v31, %v0 + vmxlb %v31, %v0, %v0 + vmxlb %v18, %v3, %v20 + +#CHECK: vmxlf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xfd] +#CHECK: vmxlf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xfd] +#CHECK: vmxlf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xfd] +#CHECK: vmxlf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xfd] +#CHECK: vmxlf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xfd] + + vmxlf %v0, %v0, %v0 + vmxlf %v0, %v0, %v31 + vmxlf %v0, %v31, %v0 + vmxlf %v31, %v0, %v0 + vmxlf %v18, %v3, %v20 + +#CHECK: vmxlg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xfd] +#CHECK: vmxlg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xfd] +#CHECK: vmxlg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xfd] +#CHECK: vmxlg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xfd] +#CHECK: vmxlg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xfd] + + vmxlg %v0, %v0, %v0 + vmxlg %v0, %v0, %v31 + vmxlg %v0, %v31, %v0 + vmxlg %v31, %v0, %v0 + vmxlg %v18, %v3, %v20 + +#CHECK: vmxlh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xfd] +#CHECK: vmxlh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xfd] +#CHECK: vmxlh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xfd] +#CHECK: vmxlh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xfd] +#CHECK: vmxlh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xfd] + + vmxlh %v0, %v0, %v0 + vmxlh %v0, %v0, %v31 + vmxlh %v0, %v31, %v0 + vmxlh %v31, %v0, %v0 + vmxlh %v18, %v3, %v20 + +#CHECK: vn %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x68] +#CHECK: vn %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x68] +#CHECK: vn %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x68] +#CHECK: vn %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x68] +#CHECK: vn %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x68] + + vn %v0, %v0, %v0 + vn %v0, %v0, %v31 + vn %v0, %v31, %v0 + vn %v31, %v0, %v0 + vn %v18, %v3, %v20 + +#CHECK: vnc %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x69] +#CHECK: vnc %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x69] +#CHECK: vnc %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x69] +#CHECK: vnc %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x69] +#CHECK: vnc %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x69] + + vnc %v0, %v0, %v0 + vnc %v0, %v0, %v31 + vnc %v0, %v31, %v0 + vnc %v31, %v0, %v0 + vnc %v18, %v3, %v20 + +#CHECK: vno %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x6b] +#CHECK: vno %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x6b] +#CHECK: vno %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x6b] +#CHECK: vno %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x6b] +#CHECK: vno %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x6b] + + vno %v0, %v0, %v0 + vno %v0, %v0, %v31 + vno %v0, %v31, %v0 + vno %v31, %v0, %v0 + vno %v18, %v3, %v20 + +#CHECK: vo %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x6a] +#CHECK: vo %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x6a] +#CHECK: vo %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x6a] +#CHECK: vo %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x6a] +#CHECK: vo %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x6a] + + vo %v0, %v0, %v0 + vo %v0, %v0, %v31 + vo %v0, %v31, %v0 + vo %v31, %v0, %v0 + vo %v18, %v3, %v20 + +#CHECK: vone %v0 # encoding: [0xe7,0x00,0xff,0xff,0x00,0x44] +#CHECK: vone %v15 # encoding: [0xe7,0xf0,0xff,0xff,0x00,0x44] +#CHECK: vone %v22 # encoding: [0xe7,0x60,0xff,0xff,0x08,0x44] +#CHECK: vone %v31 # encoding: [0xe7,0xf0,0xff,0xff,0x08,0x44] + + vone %v0 + vone %v15 + vone %v22 + vone %v31 + +#CHECK: vpdi %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x84] +#CHECK: vpdi %v0, %v0, %v0, 5 # encoding: [0xe7,0x00,0x00,0x00,0x50,0x84] +#CHECK: vpdi %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x84] +#CHECK: vpdi %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x84] +#CHECK: vpdi %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x84] +#CHECK: vpdi %v13, %v17, %v21, 4 # encoding: [0xe7,0xd1,0x50,0x00,0x46,0x84] + + vpdi %v0, %v0, %v0, 0 + vpdi %v0, %v0, %v0, 5 + vpdi %v0, %v0, %v31, 0 + vpdi %v0, %v31, %v0, 0 + vpdi %v31, %v0, %v0, 0 + vpdi %v13, %v17, %v21, 4 + +#CHECK: vperm %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x8c] +#CHECK: vperm %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x00,0x00,0xf1,0x8c] +#CHECK: vperm %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x8c] +#CHECK: vperm %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x8c] +#CHECK: vperm %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x8c] +#CHECK: vperm %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x50,0x00,0x97,0x8c] + + vperm %v0, %v0, %v0, %v0 + vperm %v0, %v0, %v0, %v31 + vperm %v0, %v0, %v31, %v0 + vperm %v0, %v31, %v0, %v0 + vperm %v31, %v0, %v0, %v0 + vperm %v13, %v17, %v21, %v25 + +#CHECK: vpkf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x94] +#CHECK: vpkf %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x94] +#CHECK: vpkf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x94] +#CHECK: vpkf %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x94] +#CHECK: vpkf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x94] +#CHECK: vpkf %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x94] +#CHECK: vpkf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x94] +#CHECK: vpkf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x94] + + vpkf %v0, %v0, %v0 + vpkf %v0, %v0, %v15 + vpkf %v0, %v0, %v31 + vpkf %v0, %v15, %v0 + vpkf %v0, %v31, %v0 + vpkf %v15, %v0, %v0 + vpkf %v31, %v0, %v0 + vpkf %v18, %v3, %v20 + +#CHECK: vpkg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x94] +#CHECK: vpkg %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x94] +#CHECK: vpkg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x94] +#CHECK: vpkg %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x94] +#CHECK: vpkg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x94] +#CHECK: vpkg %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x94] +#CHECK: vpkg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x94] +#CHECK: vpkg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x94] + + vpkg %v0, %v0, %v0 + vpkg %v0, %v0, %v15 + vpkg %v0, %v0, %v31 + vpkg %v0, %v15, %v0 + vpkg %v0, %v31, %v0 + vpkg %v15, %v0, %v0 + vpkg %v31, %v0, %v0 + vpkg %v18, %v3, %v20 + +#CHECK: vpkh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x94] +#CHECK: vpkh %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x94] +#CHECK: vpkh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x94] +#CHECK: vpkh %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x94] +#CHECK: vpkh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x94] +#CHECK: vpkh %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x94] +#CHECK: vpkh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x94] +#CHECK: vpkh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x94] + + vpkh %v0, %v0, %v0 + vpkh %v0, %v0, %v15 + vpkh %v0, %v0, %v31 + vpkh %v0, %v15, %v0 + vpkh %v0, %v31, %v0 + vpkh %v15, %v0, %v0 + vpkh %v31, %v0, %v0 + vpkh %v18, %v3, %v20 + +#CHECK: vpklsf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x95] +#CHECK: vpklsf %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x95] +#CHECK: vpklsf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x95] +#CHECK: vpklsf %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x95] +#CHECK: vpklsf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x95] +#CHECK: vpklsf %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x95] +#CHECK: vpklsf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x95] +#CHECK: vpklsf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x95] +#CHECK: vpklsfs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x24,0x95] + + vpklsf %v0, %v0, %v0 + vpklsf %v0, %v0, %v15 + vpklsf %v0, %v0, %v31 + vpklsf %v0, %v15, %v0 + vpklsf %v0, %v31, %v0 + vpklsf %v15, %v0, %v0 + vpklsf %v31, %v0, %v0 + vpklsf %v18, %v3, %v20 + vpklsfs %v5, %v22, %v7 + +#CHECK: vpklsg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x95] +#CHECK: vpklsg %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x95] +#CHECK: vpklsg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x95] +#CHECK: vpklsg %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x95] +#CHECK: vpklsg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x95] +#CHECK: vpklsg %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x95] +#CHECK: vpklsg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x95] +#CHECK: vpklsg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x95] +#CHECK: vpklsgs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x34,0x95] + + vpklsg %v0, %v0, %v0 + vpklsg %v0, %v0, %v15 + vpklsg %v0, %v0, %v31 + vpklsg %v0, %v15, %v0 + vpklsg %v0, %v31, %v0 + vpklsg %v15, %v0, %v0 + vpklsg %v31, %v0, %v0 + vpklsg %v18, %v3, %v20 + vpklsgs %v5, %v22, %v7 + +#CHECK: vpklsh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x95] +#CHECK: vpklsh %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x95] +#CHECK: vpklsh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x95] +#CHECK: vpklsh %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x95] +#CHECK: vpklsh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x95] +#CHECK: vpklsh %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x95] +#CHECK: vpklsh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x95] +#CHECK: vpklsh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x95] +#CHECK: vpklshs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x14,0x95] + + vpklsh %v0, %v0, %v0 + vpklsh %v0, %v0, %v15 + vpklsh %v0, %v0, %v31 + vpklsh %v0, %v15, %v0 + vpklsh %v0, %v31, %v0 + vpklsh %v15, %v0, %v0 + vpklsh %v31, %v0, %v0 + vpklsh %v18, %v3, %v20 + vpklshs %v5, %v22, %v7 + +#CHECK: vpksf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x97] +#CHECK: vpksf %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x97] +#CHECK: vpksf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x97] +#CHECK: vpksf %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x97] +#CHECK: vpksf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x97] +#CHECK: vpksf %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x97] +#CHECK: vpksf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x97] +#CHECK: vpksf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x97] +#CHECK: vpksfs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x24,0x97] + + vpksf %v0, %v0, %v0 + vpksf %v0, %v0, %v15 + vpksf %v0, %v0, %v31 + vpksf %v0, %v15, %v0 + vpksf %v0, %v31, %v0 + vpksf %v15, %v0, %v0 + vpksf %v31, %v0, %v0 + vpksf %v18, %v3, %v20 + vpksfs %v5, %v22, %v7 + +#CHECK: vpksg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x97] +#CHECK: vpksg %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x97] +#CHECK: vpksg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x97] +#CHECK: vpksg %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x97] +#CHECK: vpksg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x97] +#CHECK: vpksg %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x97] +#CHECK: vpksg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x97] +#CHECK: vpksg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x97] +#CHECK: vpksgs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x34,0x97] + + vpksg %v0, %v0, %v0 + vpksg %v0, %v0, %v15 + vpksg %v0, %v0, %v31 + vpksg %v0, %v15, %v0 + vpksg %v0, %v31, %v0 + vpksg %v15, %v0, %v0 + vpksg %v31, %v0, %v0 + vpksg %v18, %v3, %v20 + vpksgs %v5, %v22, %v7 + +#CHECK: vpksh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x97] +#CHECK: vpksh %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x97] +#CHECK: vpksh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x97] +#CHECK: vpksh %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x97] +#CHECK: vpksh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x97] +#CHECK: vpksh %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x97] +#CHECK: vpksh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x97] +#CHECK: vpksh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x97] +#CHECK: vpkshs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x14,0x97] + + vpksh %v0, %v0, %v0 + vpksh %v0, %v0, %v15 + vpksh %v0, %v0, %v31 + vpksh %v0, %v15, %v0 + vpksh %v0, %v31, %v0 + vpksh %v15, %v0, %v0 + vpksh %v31, %v0, %v0 + vpksh %v18, %v3, %v20 + vpkshs %v5, %v22, %v7 + +#CHECK: vpopct %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x50] +#CHECK: vpopct %v0, %v15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x50] +#CHECK: vpopct %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x50] +#CHECK: vpopct %v15, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x50] +#CHECK: vpopct %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x50] +#CHECK: vpopct %v14, %v17, 0 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0x50] + + vpopct %v0, %v0, 0 + vpopct %v0, %v15, 0 + vpopct %v0, %v31, 0 + vpopct %v15, %v0, 0 + vpopct %v31, %v0, 0 + vpopct %v14, %v17, 0 + +#CHECK: vrepb %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x4d] +#CHECK: vrepb %v0, %v0, 65535 # encoding: [0xe7,0x00,0xff,0xff,0x00,0x4d] +#CHECK: vrepb %v0, %v15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x4d] +#CHECK: vrepb %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x4d] +#CHECK: vrepb %v15, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x4d] +#CHECK: vrepb %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x4d] +#CHECK: vrepb %v4, %v21, 26505 # encoding: [0xe7,0x45,0x67,0x89,0x04,0x4d] + + vrepb %v0, %v0, 0 + vrepb %v0, %v0, 65535 + vrepb %v0, %v15, 0 + vrepb %v0, %v31, 0 + vrepb %v15, %v0, 0 + vrepb %v31, %v0, 0 + vrepb %v4, %v21, 0x6789 + +#CHECK: vrepf %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x4d] +#CHECK: vrepf %v0, %v0, 65535 # encoding: [0xe7,0x00,0xff,0xff,0x20,0x4d] +#CHECK: vrepf %v0, %v15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x4d] +#CHECK: vrepf %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x4d] +#CHECK: vrepf %v15, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x4d] +#CHECK: vrepf %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x4d] +#CHECK: vrepf %v4, %v21, 26505 # encoding: [0xe7,0x45,0x67,0x89,0x24,0x4d] + + vrepf %v0, %v0, 0 + vrepf %v0, %v0, 65535 + vrepf %v0, %v15, 0 + vrepf %v0, %v31, 0 + vrepf %v15, %v0, 0 + vrepf %v31, %v0, 0 + vrepf %v4, %v21, 0x6789 + +#CHECK: vrepg %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x4d] +#CHECK: vrepg %v0, %v0, 65535 # encoding: [0xe7,0x00,0xff,0xff,0x30,0x4d] +#CHECK: vrepg %v0, %v15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x4d] +#CHECK: vrepg %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x4d] +#CHECK: vrepg %v15, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x4d] +#CHECK: vrepg %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x4d] +#CHECK: vrepg %v4, %v21, 26505 # encoding: [0xe7,0x45,0x67,0x89,0x34,0x4d] + + vrepg %v0, %v0, 0 + vrepg %v0, %v0, 65535 + vrepg %v0, %v15, 0 + vrepg %v0, %v31, 0 + vrepg %v15, %v0, 0 + vrepg %v31, %v0, 0 + vrepg %v4, %v21, 0x6789 + +#CHECK: vreph %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x4d] +#CHECK: vreph %v0, %v0, 65535 # encoding: [0xe7,0x00,0xff,0xff,0x10,0x4d] +#CHECK: vreph %v0, %v15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x4d] +#CHECK: vreph %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x4d] +#CHECK: vreph %v15, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x4d] +#CHECK: vreph %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x4d] +#CHECK: vreph %v4, %v21, 26505 # encoding: [0xe7,0x45,0x67,0x89,0x14,0x4d] + + vreph %v0, %v0, 0 + vreph %v0, %v0, 65535 + vreph %v0, %v15, 0 + vreph %v0, %v31, 0 + vreph %v15, %v0, 0 + vreph %v31, %v0, 0 + vreph %v4, %v21, 0x6789 + +#CHECK: vrepib %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x45] +#CHECK: vrepib %v0, -32768 # encoding: [0xe7,0x00,0x80,0x00,0x00,0x45] +#CHECK: vrepib %v0, 32767 # encoding: [0xe7,0x00,0x7f,0xff,0x00,0x45] +#CHECK: vrepib %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x45] +#CHECK: vrepib %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x45] +#CHECK: vrepib %v18, 13398 # encoding: [0xe7,0x20,0x34,0x56,0x08,0x45] + + vrepib %v0, 0 + vrepib %v0, -32768 + vrepib %v0, 32767 + vrepib %v15, 0 + vrepib %v31, 0 + vrepib %v18, 0x3456 + +#CHECK: vrepif %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x45] +#CHECK: vrepif %v0, -32768 # encoding: [0xe7,0x00,0x80,0x00,0x20,0x45] +#CHECK: vrepif %v0, 32767 # encoding: [0xe7,0x00,0x7f,0xff,0x20,0x45] +#CHECK: vrepif %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x45] +#CHECK: vrepif %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x45] +#CHECK: vrepif %v18, 13398 # encoding: [0xe7,0x20,0x34,0x56,0x28,0x45] + + vrepif %v0, 0 + vrepif %v0, -32768 + vrepif %v0, 32767 + vrepif %v15, 0 + vrepif %v31, 0 + vrepif %v18, 0x3456 + +#CHECK: vrepig %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x45] +#CHECK: vrepig %v0, -32768 # encoding: [0xe7,0x00,0x80,0x00,0x30,0x45] +#CHECK: vrepig %v0, 32767 # encoding: [0xe7,0x00,0x7f,0xff,0x30,0x45] +#CHECK: vrepig %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x45] +#CHECK: vrepig %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x45] +#CHECK: vrepig %v18, 13398 # encoding: [0xe7,0x20,0x34,0x56,0x38,0x45] + + vrepig %v0, 0 + vrepig %v0, -32768 + vrepig %v0, 32767 + vrepig %v15, 0 + vrepig %v31, 0 + vrepig %v18, 0x3456 + +#CHECK: vrepih %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x45] +#CHECK: vrepih %v0, -32768 # encoding: [0xe7,0x00,0x80,0x00,0x10,0x45] +#CHECK: vrepih %v0, 32767 # encoding: [0xe7,0x00,0x7f,0xff,0x10,0x45] +#CHECK: vrepih %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x45] +#CHECK: vrepih %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x45] +#CHECK: vrepih %v18, 13398 # encoding: [0xe7,0x20,0x34,0x56,0x18,0x45] + + vrepih %v0, 0 + vrepih %v0, -32768 + vrepih %v0, 32767 + vrepih %v15, 0 + vrepih %v31, 0 + vrepih %v18, 0x3456 + +#CHECK: vsb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf7] +#CHECK: vsb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf7] +#CHECK: vsb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf7] +#CHECK: vsb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf7] +#CHECK: vsb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xf7] + + vsb %v0, %v0, %v0 + vsb %v0, %v0, %v31 + vsb %v0, %v31, %v0 + vsb %v31, %v0, %v0 + vsb %v18, %v3, %v20 + +#CHECK: vsbcbiq %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x04,0x00,0x00,0xbd] +#CHECK: vsbcbiq %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x04,0x00,0xf1,0xbd] +#CHECK: vsbcbiq %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf4,0x00,0x02,0xbd] +#CHECK: vsbcbiq %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x04,0x00,0x04,0xbd] +#CHECK: vsbcbiq %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x04,0x00,0x08,0xbd] +#CHECK: vsbcbiq %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x54,0x00,0x97,0xbd] + + vsbcbiq %v0, %v0, %v0, %v0 + vsbcbiq %v0, %v0, %v0, %v31 + vsbcbiq %v0, %v0, %v31, %v0 + vsbcbiq %v0, %v31, %v0, %v0 + vsbcbiq %v31, %v0, %v0, %v0 + vsbcbiq %v13, %v17, %v21, %v25 + +#CHECK: vsbiq %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x04,0x00,0x00,0xbf] +#CHECK: vsbiq %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x04,0x00,0xf1,0xbf] +#CHECK: vsbiq %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf4,0x00,0x02,0xbf] +#CHECK: vsbiq %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x04,0x00,0x04,0xbf] +#CHECK: vsbiq %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x04,0x00,0x08,0xbf] +#CHECK: vsbiq %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x54,0x00,0x97,0xbf] + + vsbiq %v0, %v0, %v0, %v0 + vsbiq %v0, %v0, %v0, %v31 + vsbiq %v0, %v0, %v31, %v0 + vsbiq %v0, %v31, %v0, %v0 + vsbiq %v31, %v0, %v0, %v0 + vsbiq %v13, %v17, %v21, %v25 + +#CHECK: vscbib %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf5] +#CHECK: vscbib %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf5] +#CHECK: vscbib %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf5] +#CHECK: vscbib %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf5] +#CHECK: vscbib %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0xf5] + + vscbib %v0, %v0, %v0 + vscbib %v0, %v0, %v31 + vscbib %v0, %v31, %v0 + vscbib %v31, %v0, %v0 + vscbib %v18, %v3, %v20 + +#CHECK: vscbif %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xf5] +#CHECK: vscbif %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xf5] +#CHECK: vscbif %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xf5] +#CHECK: vscbif %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xf5] +#CHECK: vscbif %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xf5] + + vscbif %v0, %v0, %v0 + vscbif %v0, %v0, %v31 + vscbif %v0, %v31, %v0 + vscbif %v31, %v0, %v0 + vscbif %v18, %v3, %v20 + +#CHECK: vscbig %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xf5] +#CHECK: vscbig %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xf5] +#CHECK: vscbig %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xf5] +#CHECK: vscbig %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xf5] +#CHECK: vscbig %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xf5] + + vscbig %v0, %v0, %v0 + vscbig %v0, %v0, %v31 + vscbig %v0, %v31, %v0 + vscbig %v31, %v0, %v0 + vscbig %v18, %v3, %v20 + +#CHECK: vscbih %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xf5] +#CHECK: vscbih %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xf5] +#CHECK: vscbih %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xf5] +#CHECK: vscbih %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xf5] +#CHECK: vscbih %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xf5] + + vscbih %v0, %v0, %v0 + vscbih %v0, %v0, %v31 + vscbih %v0, %v31, %v0 + vscbih %v31, %v0, %v0 + vscbih %v18, %v3, %v20 + +#CHECK: vscbiq %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x40,0xf5] +#CHECK: vscbiq %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x42,0xf5] +#CHECK: vscbiq %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x44,0xf5] +#CHECK: vscbiq %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x48,0xf5] +#CHECK: vscbiq %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x4a,0xf5] + + vscbiq %v0, %v0, %v0 + vscbiq %v0, %v0, %v31 + vscbiq %v0, %v31, %v0 + vscbiq %v31, %v0, %v0 + vscbiq %v18, %v3, %v20 + +#CHECK: vscef %v0, 0(%v0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x1b] +#CHECK: vscef %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x1b] +#CHECK: vscef %v0, 0(%v0,%r1), 3 # encoding: [0xe7,0x00,0x10,0x00,0x30,0x1b] +#CHECK: vscef %v0, 0(%v0,%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x1b] +#CHECK: vscef %v0, 0(%v15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x1b] +#CHECK: vscef %v0, 0(%v31,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x04,0x1b] +#CHECK: vscef %v0, 4095(%v0,%r1), 0 # encoding: [0xe7,0x00,0x1f,0xff,0x00,0x1b] +#CHECK: vscef %v15, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x00,0x1b] +#CHECK: vscef %v31, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x1b] +#CHECK: vscef %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x1b] + + vscef %v0, 0(%v0), 0 + vscef %v0, 0(%v0,%r1), 0 + vscef %v0, 0(%v0,%r1), 3 + vscef %v0, 0(%v0,%r15), 0 + vscef %v0, 0(%v15,%r1), 0 + vscef %v0, 0(%v31,%r1), 0 + vscef %v0, 4095(%v0, %r1), 0 + vscef %v15, 0(%v0,%r1), 0 + vscef %v31, 0(%v0,%r1), 0 + vscef %v10, 1000(%v19,%r7), 1 + +#CHECK: vsceg %v0, 0(%v0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x1a] +#CHECK: vsceg %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x1a] +#CHECK: vsceg %v0, 0(%v0,%r1), 1 # encoding: [0xe7,0x00,0x10,0x00,0x10,0x1a] +#CHECK: vsceg %v0, 0(%v0,%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x1a] +#CHECK: vsceg %v0, 0(%v15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x1a] +#CHECK: vsceg %v0, 0(%v31,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x04,0x1a] +#CHECK: vsceg %v0, 4095(%v0,%r1), 0 # encoding: [0xe7,0x00,0x1f,0xff,0x00,0x1a] +#CHECK: vsceg %v15, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x00,0x1a] +#CHECK: vsceg %v31, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x1a] +#CHECK: vsceg %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x1a] + + vsceg %v0, 0(%v0), 0 + vsceg %v0, 0(%v0,%r1), 0 + vsceg %v0, 0(%v0,%r1), 1 + vsceg %v0, 0(%v0,%r15), 0 + vsceg %v0, 0(%v15,%r1), 0 + vsceg %v0, 0(%v31,%r1), 0 + vsceg %v0, 4095(%v0,%r1), 0 + vsceg %v15, 0(%v0,%r1), 0 + vsceg %v31, 0(%v0,%r1), 0 + vsceg %v10, 1000(%v19,%r7), 1 + +#CHECK: vsel %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x8d] +#CHECK: vsel %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x00,0x00,0xf1,0x8d] +#CHECK: vsel %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x8d] +#CHECK: vsel %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x8d] +#CHECK: vsel %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x8d] +#CHECK: vsel %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x50,0x00,0x97,0x8d] + + vsel %v0, %v0, %v0, %v0 + vsel %v0, %v0, %v0, %v31 + vsel %v0, %v0, %v31, %v0 + vsel %v0, %v31, %v0, %v0 + vsel %v31, %v0, %v0, %v0 + vsel %v13, %v17, %v21, %v25 + +#CHECK: vsegb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x5f] +#CHECK: vsegb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x5f] +#CHECK: vsegb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x5f] +#CHECK: vsegb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x5f] +#CHECK: vsegb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x5f] +#CHECK: vsegb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0x5f] + + vsegb %v0, %v0 + vsegb %v0, %v15 + vsegb %v0, %v31 + vsegb %v15, %v0 + vsegb %v31, %v0 + vsegb %v14, %v17 + +#CHECK: vsegf %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x5f] +#CHECK: vsegf %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x5f] +#CHECK: vsegf %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x5f] +#CHECK: vsegf %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x5f] +#CHECK: vsegf %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x5f] +#CHECK: vsegf %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x24,0x5f] + + vsegf %v0, %v0 + vsegf %v0, %v15 + vsegf %v0, %v31 + vsegf %v15, %v0 + vsegf %v31, %v0 + vsegf %v14, %v17 + +#CHECK: vsegh %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x5f] +#CHECK: vsegh %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x5f] +#CHECK: vsegh %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x5f] +#CHECK: vsegh %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x5f] +#CHECK: vsegh %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x5f] +#CHECK: vsegh %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x14,0x5f] + + vsegh %v0, %v0 + vsegh %v0, %v15 + vsegh %v0, %v31 + vsegh %v15, %v0 + vsegh %v31, %v0 + vsegh %v14, %v17 + +#CHECK: vsf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xf7] +#CHECK: vsf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0xf7] +#CHECK: vsf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xf7] +#CHECK: vsf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xf7] +#CHECK: vsf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0xf7] + + vsf %v0, %v0, %v0 + vsf %v0, %v0, %v31 + vsf %v0, %v31, %v0 + vsf %v31, %v0, %v0 + vsf %v18, %v3, %v20 + +#CHECK: vsg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xf7] +#CHECK: vsg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xf7] +#CHECK: vsg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xf7] +#CHECK: vsg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xf7] +#CHECK: vsg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0xf7] + + vsg %v0, %v0, %v0 + vsg %v0, %v0, %v31 + vsg %v0, %v31, %v0 + vsg %v31, %v0, %v0 + vsg %v18, %v3, %v20 + +#CHECK: vsh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xf7] +#CHECK: vsh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0xf7] +#CHECK: vsh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xf7] +#CHECK: vsh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xf7] +#CHECK: vsh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0xf7] + + vsh %v0, %v0, %v0 + vsh %v0, %v0, %v31 + vsh %v0, %v31, %v0 + vsh %v31, %v0, %v0 + vsh %v18, %v3, %v20 + +#CHECK: vsl %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x74] +#CHECK: vsl %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x74] +#CHECK: vsl %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x74] +#CHECK: vsl %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x74] +#CHECK: vsl %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x74] + + vsl %v0, %v0, %v0 + vsl %v0, %v0, %v31 + vsl %v0, %v31, %v0 + vsl %v31, %v0, %v0 + vsl %v18, %v3, %v20 + +#CHECK: vslb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x75] +#CHECK: vslb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x75] +#CHECK: vslb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x75] +#CHECK: vslb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x75] +#CHECK: vslb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x75] + + vslb %v0, %v0, %v0 + vslb %v0, %v0, %v31 + vslb %v0, %v31, %v0 + vslb %v31, %v0, %v0 + vslb %v18, %v3, %v20 + +#CHECK: vsldb %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x77] +#CHECK: vsldb %v0, %v0, %v0, 255 # encoding: [0xe7,0x00,0x00,0xff,0x00,0x77] +#CHECK: vsldb %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x77] +#CHECK: vsldb %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x77] +#CHECK: vsldb %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x77] +#CHECK: vsldb %v13, %v17, %v21, 121 # encoding: [0xe7,0xd1,0x50,0x79,0x06,0x77] + + vsldb %v0, %v0, %v0, 0 + vsldb %v0, %v0, %v0, 255 + vsldb %v0, %v0, %v31, 0 + vsldb %v0, %v31, %v0, 0 + vsldb %v31, %v0, %v0, 0 + vsldb %v13, %v17, %v21, 0x79 + +#CHECK: vsq %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x40,0xf7] +#CHECK: vsq %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x42,0xf7] +#CHECK: vsq %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x44,0xf7] +#CHECK: vsq %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x48,0xf7] +#CHECK: vsq %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x4a,0xf7] + + vsq %v0, %v0, %v0 + vsq %v0, %v0, %v31 + vsq %v0, %v31, %v0 + vsq %v31, %v0, %v0 + vsq %v18, %v3, %v20 + +#CHECK: vsra %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x7e] +#CHECK: vsra %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x7e] +#CHECK: vsra %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x7e] +#CHECK: vsra %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x7e] +#CHECK: vsra %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x7e] + + vsra %v0, %v0, %v0 + vsra %v0, %v0, %v31 + vsra %v0, %v31, %v0 + vsra %v31, %v0, %v0 + vsra %v18, %v3, %v20 + +#CHECK: vsrab %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x7f] +#CHECK: vsrab %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x7f] +#CHECK: vsrab %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x7f] +#CHECK: vsrab %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x7f] +#CHECK: vsrab %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x7f] + + vsrab %v0, %v0, %v0 + vsrab %v0, %v0, %v31 + vsrab %v0, %v31, %v0 + vsrab %v31, %v0, %v0 + vsrab %v18, %v3, %v20 + +#CHECK: vsrl %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x7c] +#CHECK: vsrl %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x7c] +#CHECK: vsrl %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x7c] +#CHECK: vsrl %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x7c] +#CHECK: vsrl %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x7c] + + vsrl %v0, %v0, %v0 + vsrl %v0, %v0, %v31 + vsrl %v0, %v31, %v0 + vsrl %v31, %v0, %v0 + vsrl %v18, %v3, %v20 + +#CHECK: vsrlb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x7d] +#CHECK: vsrlb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x7d] +#CHECK: vsrlb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x7d] +#CHECK: vsrlb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x7d] +#CHECK: vsrlb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x7d] + + vsrlb %v0, %v0, %v0 + vsrlb %v0, %v0, %v31 + vsrlb %v0, %v31, %v0 + vsrlb %v31, %v0, %v0 + vsrlb %v18, %v3, %v20 + +#CHECK: vst %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x0e] +#CHECK: vst %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x0e] +#CHECK: vst %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x0e] +#CHECK: vst %v0, 0(%r15,%r1) # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x0e] +#CHECK: vst %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x0e] +#CHECK: vst %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x0e] +#CHECK: vst %v18, 1383(%r3,%r4) # encoding: [0xe7,0x23,0x45,0x67,0x08,0x0e] + + vst %v0, 0 + vst %v0, 4095 + vst %v0, 0(%r15) + vst %v0, 0(%r15,%r1) + vst %v15, 0 + vst %v31, 0 + vst %v18, 0x567(%r3,%r4) + +#CHECK: vsteb %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x08] +#CHECK: vsteb %v0, 0, 15 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x08] +#CHECK: vsteb %v0, 4095, 0 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x08] +#CHECK: vsteb %v0, 0(%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x08] +#CHECK: vsteb %v0, 0(%r15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x08] +#CHECK: vsteb %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x08] +#CHECK: vsteb %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x08] +#CHECK: vsteb %v18, 1383(%r3,%r4), 8 # encoding: [0xe7,0x23,0x45,0x67,0x88,0x08] + + vsteb %v0, 0, 0 + vsteb %v0, 0, 15 + vsteb %v0, 4095, 0 + vsteb %v0, 0(%r15), 0 + vsteb %v0, 0(%r15,%r1), 0 + vsteb %v15, 0, 0 + vsteb %v31, 0, 0 + vsteb %v18, 1383(%r3,%r4), 8 + +#CHECK: vstef %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x0b] +#CHECK: vstef %v0, 0, 3 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x0b] +#CHECK: vstef %v0, 4095, 0 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x0b] +#CHECK: vstef %v0, 0(%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x0b] +#CHECK: vstef %v0, 0(%r15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x0b] +#CHECK: vstef %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x0b] +#CHECK: vstef %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x0b] +#CHECK: vstef %v18, 1383(%r3,%r4), 2 # encoding: [0xe7,0x23,0x45,0x67,0x28,0x0b] + + vstef %v0, 0, 0 + vstef %v0, 0, 3 + vstef %v0, 4095, 0 + vstef %v0, 0(%r15), 0 + vstef %v0, 0(%r15,%r1), 0 + vstef %v15, 0, 0 + vstef %v31, 0, 0 + vstef %v18, 1383(%r3,%r4), 2 + +#CHECK: vsteg %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x0a] +#CHECK: vsteg %v0, 0, 1 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x0a] +#CHECK: vsteg %v0, 4095, 0 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x0a] +#CHECK: vsteg %v0, 0(%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x0a] +#CHECK: vsteg %v0, 0(%r15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x0a] +#CHECK: vsteg %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x0a] +#CHECK: vsteg %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x0a] +#CHECK: vsteg %v18, 1383(%r3,%r4), 1 # encoding: [0xe7,0x23,0x45,0x67,0x18,0x0a] + + vsteg %v0, 0, 0 + vsteg %v0, 0, 1 + vsteg %v0, 4095, 0 + vsteg %v0, 0(%r15), 0 + vsteg %v0, 0(%r15,%r1), 0 + vsteg %v15, 0, 0 + vsteg %v31, 0, 0 + vsteg %v18, 1383(%r3,%r4), 1 + +#CHECK: vsteh %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x09] +#CHECK: vsteh %v0, 0, 7 # encoding: [0xe7,0x00,0x00,0x00,0x70,0x09] +#CHECK: vsteh %v0, 4095, 0 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x09] +#CHECK: vsteh %v0, 0(%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x09] +#CHECK: vsteh %v0, 0(%r15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x09] +#CHECK: vsteh %v15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x09] +#CHECK: vsteh %v31, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x09] +#CHECK: vsteh %v18, 1383(%r3,%r4), 4 # encoding: [0xe7,0x23,0x45,0x67,0x48,0x09] + + vsteh %v0, 0, 0 + vsteh %v0, 0, 7 + vsteh %v0, 4095, 0 + vsteh %v0, 0(%r15), 0 + vsteh %v0, 0(%r15,%r1), 0 + vsteh %v15, 0, 0 + vsteh %v31, 0, 0 + vsteh %v18, 1383(%r3,%r4), 4 + +#CHECK: vstl %v0, %r0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x3f] +#CHECK: vstl %v0, %r0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x3f] +#CHECK: vstl %v0, %r0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x3f] +#CHECK: vstl %v0, %r15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x3f] +#CHECK: vstl %v15, %r0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x3f] +#CHECK: vstl %v31, %r0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x3f] +#CHECK: vstl %v18, %r3, 1383(%r4) # encoding: [0xe7,0x23,0x45,0x67,0x08,0x3f] + + vstl %v0, %r0, 0 + vstl %v0, %r0, 4095 + vstl %v0, %r0, 0(%r15) + vstl %v0, %r15, 0 + vstl %v15, %r0, 0 + vstl %v31, %r0, 0 + vstl %v18, %r3, 1383(%r4) + +#CHECK: vstm %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x3e] +#CHECK: vstm %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x3e] +#CHECK: vstm %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x3e] +#CHECK: vstm %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x3e] +#CHECK: vstm %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x3e] +#CHECK: vstm %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x04,0x3e] + + vstm %v0, %v0, 0 + vstm %v0, %v0, 4095 + vstm %v0, %v0, 0(%r15) + vstm %v0, %v31, 0 + vstm %v31, %v0, 0 + vstm %v14, %v17, 1074(%r5) + +#CHECK: vstrcb %v0, %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x8a] +#CHECK: vstrcb %v0, %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x8a] +#CHECK: vstrcb %v0, %v0, %v0, %v0, 12 # encoding: [0xe7,0x00,0x00,0xc0,0x00,0x8a] +#CHECK: vstrcb %v0, %v0, %v0, %v15, 0 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x8a] +#CHECK: vstrcb %v0, %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0x00,0x00,0xf1,0x8a] +#CHECK: vstrcb %v0, %v0, %v15, %v0, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x8a] +#CHECK: vstrcb %v0, %v0, %v31, %v0, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x8a] +#CHECK: vstrcb %v0, %v15, %v0, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x8a] +#CHECK: vstrcb %v0, %v31, %v0, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x8a] +#CHECK: vstrcb %v15, %v0, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x8a] +#CHECK: vstrcb %v31, %v0, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x8a] +#CHECK: vstrcb %v18, %v3, %v20, %v5, 4 # encoding: [0xe7,0x23,0x40,0x40,0x5a,0x8a] +#CHECK: vstrcb %v18, %v3, %v20, %v5, 15 # encoding: [0xe7,0x23,0x40,0xf0,0x5a,0x8a] +#CHECK: vstrcbs %v18, %v3, %v20, %v5, 8 # encoding: [0xe7,0x23,0x40,0x90,0x5a,0x8a] +#CHECK: vstrczb %v18, %v3, %v20, %v5, 4 # encoding: [0xe7,0x23,0x40,0x60,0x5a,0x8a] +#CHECK: vstrczbs %v18, %v3, %v20, %v5, 8 # encoding: [0xe7,0x23,0x40,0xb0,0x5a,0x8a] +#CHECK: vstrczbs %v18, %v3, %v20, %v5, 15 # encoding: [0xe7,0x23,0x40,0xf0,0x5a,0x8a] + + vstrcb %v0, %v0, %v0, %v0 + vstrcb %v0, %v0, %v0, %v0, 0 + vstrcb %v0, %v0, %v0, %v0, 12 + vstrcb %v0, %v0, %v0, %v15 + vstrcb %v0, %v0, %v0, %v31 + vstrcb %v0, %v0, %v15, %v0 + vstrcb %v0, %v0, %v31, %v0 + vstrcb %v0, %v15, %v0, %v0 + vstrcb %v0, %v31, %v0, %v0 + vstrcb %v15, %v0, %v0, %v0 + vstrcb %v31, %v0, %v0, %v0 + vstrcb %v18, %v3, %v20, %v5, 4 + vstrcb %v18, %v3, %v20, %v5, 15 + vstrcbs %v18, %v3, %v20, %v5, 8 + vstrczb %v18, %v3, %v20, %v5, 4 + vstrczbs %v18, %v3, %v20, %v5, 8 + vstrczbs %v18, %v3, %v20, %v5, 15 + +#CHECK: vstrcf %v0, %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x02,0x00,0x00,0x8a] +#CHECK: vstrcf %v0, %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x02,0x00,0x00,0x8a] +#CHECK: vstrcf %v0, %v0, %v0, %v0, 12 # encoding: [0xe7,0x00,0x02,0xc0,0x00,0x8a] +#CHECK: vstrcf %v0, %v0, %v0, %v15, 0 # encoding: [0xe7,0x00,0x02,0x00,0xf0,0x8a] +#CHECK: vstrcf %v0, %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0x02,0x00,0xf1,0x8a] +#CHECK: vstrcf %v0, %v0, %v15, %v0, 0 # encoding: [0xe7,0x00,0xf2,0x00,0x00,0x8a] +#CHECK: vstrcf %v0, %v0, %v31, %v0, 0 # encoding: [0xe7,0x00,0xf2,0x00,0x02,0x8a] +#CHECK: vstrcf %v0, %v15, %v0, %v0, 0 # encoding: [0xe7,0x0f,0x02,0x00,0x00,0x8a] +#CHECK: vstrcf %v0, %v31, %v0, %v0, 0 # encoding: [0xe7,0x0f,0x02,0x00,0x04,0x8a] +#CHECK: vstrcf %v15, %v0, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x02,0x00,0x00,0x8a] +#CHECK: vstrcf %v31, %v0, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x02,0x00,0x08,0x8a] +#CHECK: vstrcf %v18, %v3, %v20, %v5, 4 # encoding: [0xe7,0x23,0x42,0x40,0x5a,0x8a] +#CHECK: vstrcf %v18, %v3, %v20, %v5, 15 # encoding: [0xe7,0x23,0x42,0xf0,0x5a,0x8a] +#CHECK: vstrcfs %v18, %v3, %v20, %v5, 8 # encoding: [0xe7,0x23,0x42,0x90,0x5a,0x8a] +#CHECK: vstrczf %v18, %v3, %v20, %v5, 4 # encoding: [0xe7,0x23,0x42,0x60,0x5a,0x8a] +#CHECK: vstrczfs %v18, %v3, %v20, %v5, 8 # encoding: [0xe7,0x23,0x42,0xb0,0x5a,0x8a] +#CHECK: vstrczfs %v18, %v3, %v20, %v5, 15 # encoding: [0xe7,0x23,0x42,0xf0,0x5a,0x8a] + + vstrcf %v0, %v0, %v0, %v0 + vstrcf %v0, %v0, %v0, %v0, 0 + vstrcf %v0, %v0, %v0, %v0, 12 + vstrcf %v0, %v0, %v0, %v15 + vstrcf %v0, %v0, %v0, %v31 + vstrcf %v0, %v0, %v15, %v0 + vstrcf %v0, %v0, %v31, %v0 + vstrcf %v0, %v15, %v0, %v0 + vstrcf %v0, %v31, %v0, %v0 + vstrcf %v15, %v0, %v0, %v0 + vstrcf %v31, %v0, %v0, %v0 + vstrcf %v18, %v3, %v20, %v5, 4 + vstrcf %v18, %v3, %v20, %v5, 15 + vstrcfs %v18, %v3, %v20, %v5, 8 + vstrczf %v18, %v3, %v20, %v5, 4 + vstrczfs %v18, %v3, %v20, %v5, 8 + vstrczfs %v18, %v3, %v20, %v5, 15 + +#CHECK: vstrch %v0, %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x01,0x00,0x00,0x8a] +#CHECK: vstrch %v0, %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x01,0x00,0x00,0x8a] +#CHECK: vstrch %v0, %v0, %v0, %v0, 12 # encoding: [0xe7,0x00,0x01,0xc0,0x00,0x8a] +#CHECK: vstrch %v0, %v0, %v0, %v15, 0 # encoding: [0xe7,0x00,0x01,0x00,0xf0,0x8a] +#CHECK: vstrch %v0, %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0x01,0x00,0xf1,0x8a] +#CHECK: vstrch %v0, %v0, %v15, %v0, 0 # encoding: [0xe7,0x00,0xf1,0x00,0x00,0x8a] +#CHECK: vstrch %v0, %v0, %v31, %v0, 0 # encoding: [0xe7,0x00,0xf1,0x00,0x02,0x8a] +#CHECK: vstrch %v0, %v15, %v0, %v0, 0 # encoding: [0xe7,0x0f,0x01,0x00,0x00,0x8a] +#CHECK: vstrch %v0, %v31, %v0, %v0, 0 # encoding: [0xe7,0x0f,0x01,0x00,0x04,0x8a] +#CHECK: vstrch %v15, %v0, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x01,0x00,0x00,0x8a] +#CHECK: vstrch %v31, %v0, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x01,0x00,0x08,0x8a] +#CHECK: vstrch %v18, %v3, %v20, %v5, 4 # encoding: [0xe7,0x23,0x41,0x40,0x5a,0x8a] +#CHECK: vstrch %v18, %v3, %v20, %v5, 15 # encoding: [0xe7,0x23,0x41,0xf0,0x5a,0x8a] +#CHECK: vstrchs %v18, %v3, %v20, %v5, 8 # encoding: [0xe7,0x23,0x41,0x90,0x5a,0x8a] +#CHECK: vstrczh %v18, %v3, %v20, %v5, 4 # encoding: [0xe7,0x23,0x41,0x60,0x5a,0x8a] +#CHECK: vstrczhs %v18, %v3, %v20, %v5, 8 # encoding: [0xe7,0x23,0x41,0xb0,0x5a,0x8a] +#CHECK: vstrczhs %v18, %v3, %v20, %v5, 15 # encoding: [0xe7,0x23,0x41,0xf0,0x5a,0x8a] + + vstrch %v0, %v0, %v0, %v0 + vstrch %v0, %v0, %v0, %v0, 0 + vstrch %v0, %v0, %v0, %v0, 12 + vstrch %v0, %v0, %v0, %v15 + vstrch %v0, %v0, %v0, %v31 + vstrch %v0, %v0, %v15, %v0 + vstrch %v0, %v0, %v31, %v0 + vstrch %v0, %v15, %v0, %v0 + vstrch %v0, %v31, %v0, %v0 + vstrch %v15, %v0, %v0, %v0 + vstrch %v31, %v0, %v0, %v0 + vstrch %v18, %v3, %v20, %v5, 4 + vstrch %v18, %v3, %v20, %v5, 15 + vstrchs %v18, %v3, %v20, %v5, 8 + vstrczh %v18, %v3, %v20, %v5, 4 + vstrczhs %v18, %v3, %v20, %v5, 8 + vstrczhs %v18, %v3, %v20, %v5, 15 + +#CHECK: vsumgh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x65] +#CHECK: vsumgh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x65] +#CHECK: vsumgh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x65] +#CHECK: vsumgh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x65] +#CHECK: vsumgh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x65] + + vsumgh %v0, %v0, %v0 + vsumgh %v0, %v0, %v31 + vsumgh %v0, %v31, %v0 + vsumgh %v31, %v0, %v0 + vsumgh %v18, %v3, %v20 + +#CHECK: vsumgf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x65] +#CHECK: vsumgf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x65] +#CHECK: vsumgf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x65] +#CHECK: vsumgf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x65] +#CHECK: vsumgf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x65] + + vsumgf %v0, %v0, %v0 + vsumgf %v0, %v0, %v31 + vsumgf %v0, %v31, %v0 + vsumgf %v31, %v0, %v0 + vsumgf %v18, %v3, %v20 + +#CHECK: vsumqf %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x67] +#CHECK: vsumqf %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x67] +#CHECK: vsumqf %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x67] +#CHECK: vsumqf %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x67] +#CHECK: vsumqf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x67] + + vsumqf %v0, %v0, %v0 + vsumqf %v0, %v0, %v31 + vsumqf %v0, %v31, %v0 + vsumqf %v31, %v0, %v0 + vsumqf %v18, %v3, %v20 + +#CHECK: vsumqg %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x67] +#CHECK: vsumqg %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0x67] +#CHECK: vsumqg %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x67] +#CHECK: vsumqg %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x67] +#CHECK: vsumqg %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x3a,0x67] + + vsumqg %v0, %v0, %v0 + vsumqg %v0, %v0, %v31 + vsumqg %v0, %v31, %v0 + vsumqg %v31, %v0, %v0 + vsumqg %v18, %v3, %v20 + +#CHECK: vsumb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x64] +#CHECK: vsumb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x64] +#CHECK: vsumb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x64] +#CHECK: vsumb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x64] +#CHECK: vsumb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x64] + + vsumb %v0, %v0, %v0 + vsumb %v0, %v0, %v31 + vsumb %v0, %v31, %v0 + vsumb %v31, %v0, %v0 + vsumb %v18, %v3, %v20 + +#CHECK: vsumh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x64] +#CHECK: vsumh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x64] +#CHECK: vsumh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x64] +#CHECK: vsumh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x64] +#CHECK: vsumh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x64] + + vsumh %v0, %v0, %v0 + vsumh %v0, %v0, %v31 + vsumh %v0, %v31, %v0 + vsumh %v31, %v0, %v0 + vsumh %v18, %v3, %v20 + +#CHECK: vtm %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xd8] +#CHECK: vtm %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xd8] +#CHECK: vtm %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xd8] +#CHECK: vtm %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xd8] +#CHECK: vtm %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xd8] +#CHECK: vtm %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xd8] + + vtm %v0, %v0 + vtm %v0, %v15 + vtm %v0, %v31 + vtm %v15, %v0 + vtm %v31, %v0 + vtm %v14, %v17 + +#CHECK: vuphb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xd7] +#CHECK: vuphb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xd7] +#CHECK: vuphb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xd7] +#CHECK: vuphb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xd7] +#CHECK: vuphb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xd7] +#CHECK: vuphb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xd7] + + vuphb %v0, %v0 + vuphb %v0, %v15 + vuphb %v0, %v31 + vuphb %v15, %v0 + vuphb %v31, %v0 + vuphb %v14, %v17 + +#CHECK: vuphf %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xd7] +#CHECK: vuphf %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xd7] +#CHECK: vuphf %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xd7] +#CHECK: vuphf %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xd7] +#CHECK: vuphf %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xd7] +#CHECK: vuphf %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xd7] + + vuphf %v0, %v0 + vuphf %v0, %v15 + vuphf %v0, %v31 + vuphf %v15, %v0 + vuphf %v31, %v0 + vuphf %v14, %v17 + +#CHECK: vuphh %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xd7] +#CHECK: vuphh %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0xd7] +#CHECK: vuphh %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xd7] +#CHECK: vuphh %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0xd7] +#CHECK: vuphh %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xd7] +#CHECK: vuphh %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x14,0xd7] + + vuphh %v0, %v0 + vuphh %v0, %v15 + vuphh %v0, %v31 + vuphh %v15, %v0 + vuphh %v31, %v0 + vuphh %v14, %v17 + +#CHECK: vuplhb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xd5] +#CHECK: vuplhb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xd5] +#CHECK: vuplhb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xd5] +#CHECK: vuplhb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xd5] +#CHECK: vuplhb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xd5] +#CHECK: vuplhb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xd5] + + vuplhb %v0, %v0 + vuplhb %v0, %v15 + vuplhb %v0, %v31 + vuplhb %v15, %v0 + vuplhb %v31, %v0 + vuplhb %v14, %v17 + +#CHECK: vuplhf %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xd5] +#CHECK: vuplhf %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xd5] +#CHECK: vuplhf %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xd5] +#CHECK: vuplhf %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xd5] +#CHECK: vuplhf %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xd5] +#CHECK: vuplhf %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xd5] + + vuplhf %v0, %v0 + vuplhf %v0, %v15 + vuplhf %v0, %v31 + vuplhf %v15, %v0 + vuplhf %v31, %v0 + vuplhf %v14, %v17 + +#CHECK: vuplhh %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xd5] +#CHECK: vuplhh %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0xd5] +#CHECK: vuplhh %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xd5] +#CHECK: vuplhh %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0xd5] +#CHECK: vuplhh %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xd5] +#CHECK: vuplhh %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x14,0xd5] + + vuplhh %v0, %v0 + vuplhh %v0, %v15 + vuplhh %v0, %v31 + vuplhh %v15, %v0 + vuplhh %v31, %v0 + vuplhh %v14, %v17 + +#CHECK: vuplb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xd6] +#CHECK: vuplb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xd6] +#CHECK: vuplb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xd6] +#CHECK: vuplb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xd6] +#CHECK: vuplb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xd6] +#CHECK: vuplb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xd6] + + vuplb %v0, %v0 + vuplb %v0, %v15 + vuplb %v0, %v31 + vuplb %v15, %v0 + vuplb %v31, %v0 + vuplb %v14, %v17 + +#CHECK: vuplf %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xd6] +#CHECK: vuplf %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xd6] +#CHECK: vuplf %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xd6] +#CHECK: vuplf %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xd6] +#CHECK: vuplf %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xd6] +#CHECK: vuplf %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xd6] + + vuplf %v0, %v0 + vuplf %v0, %v15 + vuplf %v0, %v31 + vuplf %v15, %v0 + vuplf %v31, %v0 + vuplf %v14, %v17 + +#CHECK: vuplhw %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xd6] +#CHECK: vuplhw %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0xd6] +#CHECK: vuplhw %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xd6] +#CHECK: vuplhw %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0xd6] +#CHECK: vuplhw %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xd6] +#CHECK: vuplhw %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x14,0xd6] + + vuplhw %v0, %v0 + vuplhw %v0, %v15 + vuplhw %v0, %v31 + vuplhw %v15, %v0 + vuplhw %v31, %v0 + vuplhw %v14, %v17 + +#CHECK: vupllb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xd4] +#CHECK: vupllb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xd4] +#CHECK: vupllb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xd4] +#CHECK: vupllb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xd4] +#CHECK: vupllb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xd4] +#CHECK: vupllb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0xd4] + + vupllb %v0, %v0 + vupllb %v0, %v15 + vupllb %v0, %v31 + vupllb %v15, %v0 + vupllb %v31, %v0 + vupllb %v14, %v17 + +#CHECK: vupllf %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0xd4] +#CHECK: vupllf %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0xd4] +#CHECK: vupllf %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xd4] +#CHECK: vupllf %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0xd4] +#CHECK: vupllf %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xd4] +#CHECK: vupllf %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x24,0xd4] + + vupllf %v0, %v0 + vupllf %v0, %v15 + vupllf %v0, %v31 + vupllf %v15, %v0 + vupllf %v31, %v0 + vupllf %v14, %v17 + +#CHECK: vupllh %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0xd4] +#CHECK: vupllh %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0xd4] +#CHECK: vupllh %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0xd4] +#CHECK: vupllh %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0xd4] +#CHECK: vupllh %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0xd4] +#CHECK: vupllh %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x14,0xd4] + + vupllh %v0, %v0 + vupllh %v0, %v15 + vupllh %v0, %v31 + vupllh %v15, %v0 + vupllh %v31, %v0 + vupllh %v14, %v17 + +#CHECK: vx %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x6d] +#CHECK: vx %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x6d] +#CHECK: vx %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x6d] +#CHECK: vx %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x6d] +#CHECK: vx %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x6d] + + vx %v0, %v0, %v0 + vx %v0, %v0, %v31 + vx %v0, %v31, %v0 + vx %v31, %v0, %v0 + vx %v18, %v3, %v20 + +#CHECK: vzero %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x44] +#CHECK: vzero %v11 # encoding: [0xe7,0xb0,0x00,0x00,0x00,0x44] +#CHECK: vzero %v15 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x44] +#CHECK: vzero %v31 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x44] + + vzero %v0 + vzero %v11 + vzero %v15 + vzero %v31 + +#CHECK: wcdgb %f0, %f0, 0, 0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xc3] +#CHECK: wcdgb %f0, %f0, 0, 15 # encoding: [0xe7,0x00,0x00,0xf8,0x30,0xc3] +#CHECK: wcdgb %f0, %f0, 4, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc3] +#CHECK: wcdgb %f0, %f0, 12, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc3] +#CHECK: wcdgb %f0, %v31, 0, 0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xc3] +#CHECK: wcdgb %v31, %f0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xc3] +#CHECK: wcdgb %f14, %v17, 4, 10 # encoding: [0xe7,0xe1,0x00,0xac,0x34,0xc3] + + wcdgb %v0, %v0, 0, 0 + wcdgb %v0, %v0, 0, 15 + wcdgb %v0, %v0, 4, 0 + wcdgb %v0, %v0, 12, 0 + wcdgb %v0, %v31, 0, 0 + wcdgb %v31, %v0, 0, 0 + wcdgb %v14, %v17, 4, 10 + +#CHECK: wcdlgb %f0, %f0, 0, 0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xc1] +#CHECK: wcdlgb %f0, %f0, 0, 15 # encoding: [0xe7,0x00,0x00,0xf8,0x30,0xc1] +#CHECK: wcdlgb %f0, %f0, 4, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc1] +#CHECK: wcdlgb %f0, %f0, 12, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc1] +#CHECK: wcdlgb %f0, %v31, 0, 0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xc1] +#CHECK: wcdlgb %v31, %f0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xc1] +#CHECK: wcdlgb %f14, %v17, 4, 10 # encoding: [0xe7,0xe1,0x00,0xac,0x34,0xc1] + + wcdlgb %v0, %v0, 0, 0 + wcdlgb %v0, %v0, 0, 15 + wcdlgb %v0, %v0, 4, 0 + wcdlgb %v0, %v0, 12, 0 + wcdlgb %v0, %v31, 0, 0 + wcdlgb %v31, %v0, 0, 0 + wcdlgb %v14, %v17, 4, 10 + +#CHECK: wcgdb %f0, %f0, 0, 0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xc2] +#CHECK: wcgdb %f0, %f0, 0, 15 # encoding: [0xe7,0x00,0x00,0xf8,0x30,0xc2] +#CHECK: wcgdb %f0, %f0, 4, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc2] +#CHECK: wcgdb %f0, %f0, 12, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc2] +#CHECK: wcgdb %f0, %v31, 0, 0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xc2] +#CHECK: wcgdb %v31, %f0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xc2] +#CHECK: wcgdb %f14, %v17, 4, 10 # encoding: [0xe7,0xe1,0x00,0xac,0x34,0xc2] + + wcgdb %v0, %v0, 0, 0 + wcgdb %v0, %v0, 0, 15 + wcgdb %v0, %v0, 4, 0 + wcgdb %v0, %v0, 12, 0 + wcgdb %v0, %v31, 0, 0 + wcgdb %v31, %v0, 0, 0 + wcgdb %v14, %v17, 4, 10 + +#CHECK: wclgdb %f0, %f0, 0, 0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xc0] +#CHECK: wclgdb %f0, %f0, 0, 15 # encoding: [0xe7,0x00,0x00,0xf8,0x30,0xc0] +#CHECK: wclgdb %f0, %f0, 4, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc0] +#CHECK: wclgdb %f0, %f0, 12, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc0] +#CHECK: wclgdb %f0, %v31, 0, 0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xc0] +#CHECK: wclgdb %v31, %f0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xc0] +#CHECK: wclgdb %f14, %v17, 4, 10 # encoding: [0xe7,0xe1,0x00,0xac,0x34,0xc0] + + wclgdb %v0, %v0, 0, 0 + wclgdb %v0, %v0, 0, 15 + wclgdb %v0, %v0, 4, 0 + wclgdb %v0, %v0, 12, 0 + wclgdb %v0, %v31, 0, 0 + wclgdb %v31, %v0, 0, 0 + wclgdb %v14, %v17, 4, 10 + +#CHECK: wfadb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xe3] +#CHECK: wfadb %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xe3] +#CHECK: wfadb %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xe3] +#CHECK: wfadb %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xe3] +#CHECK: wfadb %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x08,0x3a,0xe3] + + wfadb %v0, %v0, %v0 + wfadb %v0, %v0, %v31 + wfadb %v0, %v31, %v0 + wfadb %v31, %v0, %v0 + wfadb %v18, %v3, %v20 + +#CHECK: wfcdb %f0, %f0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xcb] +#CHECK: wfcdb %f0, %f15 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0xcb] +#CHECK: wfcdb %f0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xcb] +#CHECK: wfcdb %f15, %f0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0xcb] +#CHECK: wfcdb %v31, %f0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xcb] +#CHECK: wfcdb %f14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x34,0xcb] + + wfcdb %v0, %v0 + wfcdb %v0, %v15 + wfcdb %v0, %v31 + wfcdb %v15, %v0 + wfcdb %v31, %v0 + wfcdb %v14, %v17 + +#CHECK: wfcedb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xe8] +#CHECK: wfcedb %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xe8] +#CHECK: wfcedb %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xe8] +#CHECK: wfcedb %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xe8] +#CHECK: wfcedb %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x08,0x3a,0xe8] + + wfcedb %v0, %v0, %v0 + wfcedb %v0, %v0, %v31 + wfcedb %v0, %v31, %v0 + wfcedb %v31, %v0, %v0 + wfcedb %v18, %v3, %v20 + +#CHECK: wfcedbs %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x18,0x30,0xe8] +#CHECK: wfcedbs %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x18,0x32,0xe8] +#CHECK: wfcedbs %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x18,0x34,0xe8] +#CHECK: wfcedbs %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x18,0x38,0xe8] +#CHECK: wfcedbs %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x18,0x3a,0xe8] + + wfcedbs %v0, %v0, %v0 + wfcedbs %v0, %v0, %v31 + wfcedbs %v0, %v31, %v0 + wfcedbs %v31, %v0, %v0 + wfcedbs %v18, %v3, %v20 + +#CHECK: wfchdb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xeb] +#CHECK: wfchdb %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xeb] +#CHECK: wfchdb %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xeb] +#CHECK: wfchdb %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xeb] +#CHECK: wfchdb %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x08,0x3a,0xeb] + + wfchdb %v0, %v0, %v0 + wfchdb %v0, %v0, %v31 + wfchdb %v0, %v31, %v0 + wfchdb %v31, %v0, %v0 + wfchdb %v18, %v3, %v20 + +#CHECK: wfchdbs %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x18,0x30,0xeb] +#CHECK: wfchdbs %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x18,0x32,0xeb] +#CHECK: wfchdbs %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x18,0x34,0xeb] +#CHECK: wfchdbs %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x18,0x38,0xeb] +#CHECK: wfchdbs %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x18,0x3a,0xeb] + + wfchdbs %v0, %v0, %v0 + wfchdbs %v0, %v0, %v31 + wfchdbs %v0, %v31, %v0 + wfchdbs %v31, %v0, %v0 + wfchdbs %v18, %v3, %v20 + +#CHECK: wfchedb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xea] +#CHECK: wfchedb %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xea] +#CHECK: wfchedb %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xea] +#CHECK: wfchedb %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xea] +#CHECK: wfchedb %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x08,0x3a,0xea] + + wfchedb %v0, %v0, %v0 + wfchedb %v0, %v0, %v31 + wfchedb %v0, %v31, %v0 + wfchedb %v31, %v0, %v0 + wfchedb %v18, %v3, %v20 + +#CHECK: wfchedbs %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x18,0x30,0xea] +#CHECK: wfchedbs %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x18,0x32,0xea] +#CHECK: wfchedbs %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x18,0x34,0xea] +#CHECK: wfchedbs %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x18,0x38,0xea] +#CHECK: wfchedbs %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x18,0x3a,0xea] + + wfchedbs %v0, %v0, %v0 + wfchedbs %v0, %v0, %v31 + wfchedbs %v0, %v31, %v0 + wfchedbs %v31, %v0, %v0 + wfchedbs %v18, %v3, %v20 + +#CHECK: wfddb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xe5] +#CHECK: wfddb %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xe5] +#CHECK: wfddb %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xe5] +#CHECK: wfddb %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xe5] +#CHECK: wfddb %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x08,0x3a,0xe5] + + wfddb %v0, %v0, %v0 + wfddb %v0, %v0, %v31 + wfddb %v0, %v31, %v0 + wfddb %v31, %v0, %v0 + wfddb %v18, %v3, %v20 + +#CHECK: wfidb %f0, %f0, 0, 0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xc7] +#CHECK: wfidb %f0, %f0, 0, 15 # encoding: [0xe7,0x00,0x00,0xf8,0x30,0xc7] +#CHECK: wfidb %f0, %f0, 4, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc7] +#CHECK: wfidb %f0, %f0, 12, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc7] +#CHECK: wfidb %f0, %v31, 0, 0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xc7] +#CHECK: wfidb %v31, %f0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xc7] +#CHECK: wfidb %f14, %v17, 4, 10 # encoding: [0xe7,0xe1,0x00,0xac,0x34,0xc7] + + wfidb %v0, %v0, 0, 0 + wfidb %v0, %v0, 0, 15 + wfidb %v0, %v0, 4, 0 + wfidb %v0, %v0, 12, 0 + wfidb %v0, %v31, 0, 0 + wfidb %v31, %v0, 0, 0 + wfidb %v14, %v17, 4, 10 + +#CHECK: wfkdb %f0, %f0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xca] +#CHECK: wfkdb %f0, %f15 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0xca] +#CHECK: wfkdb %f0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xca] +#CHECK: wfkdb %f15, %f0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0xca] +#CHECK: wfkdb %v31, %f0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xca] +#CHECK: wfkdb %f14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x34,0xca] + + wfkdb %v0, %v0 + wfkdb %v0, %v15 + wfkdb %v0, %v31 + wfkdb %v15, %v0 + wfkdb %v31, %v0 + wfkdb %v14, %v17 + +#CHECK: wflcdb %f0, %f0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xcc] +#CHECK: wflcdb %f0, %f15 # encoding: [0xe7,0x0f,0x00,0x08,0x30,0xcc] +#CHECK: wflcdb %f0, %v31 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xcc] +#CHECK: wflcdb %f15, %f0 # encoding: [0xe7,0xf0,0x00,0x08,0x30,0xcc] +#CHECK: wflcdb %v31, %f0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xcc] +#CHECK: wflcdb %f14, %v17 # encoding: [0xe7,0xe1,0x00,0x08,0x34,0xcc] + + wflcdb %v0, %v0 + wflcdb %v0, %v15 + wflcdb %v0, %v31 + wflcdb %v15, %v0 + wflcdb %v31, %v0 + wflcdb %v14, %v17 + +#CHECK: wflndb %f0, %f0 # encoding: [0xe7,0x00,0x00,0x18,0x30,0xcc] +#CHECK: wflndb %f0, %f15 # encoding: [0xe7,0x0f,0x00,0x18,0x30,0xcc] +#CHECK: wflndb %f0, %v31 # encoding: [0xe7,0x0f,0x00,0x18,0x34,0xcc] +#CHECK: wflndb %f15, %f0 # encoding: [0xe7,0xf0,0x00,0x18,0x30,0xcc] +#CHECK: wflndb %v31, %f0 # encoding: [0xe7,0xf0,0x00,0x18,0x38,0xcc] +#CHECK: wflndb %f14, %v17 # encoding: [0xe7,0xe1,0x00,0x18,0x34,0xcc] + + wflndb %v0, %v0 + wflndb %v0, %v15 + wflndb %v0, %v31 + wflndb %v15, %v0 + wflndb %v31, %v0 + wflndb %v14, %v17 + +#CHECK: wflpdb %f0, %f0 # encoding: [0xe7,0x00,0x00,0x28,0x30,0xcc] +#CHECK: wflpdb %f0, %f15 # encoding: [0xe7,0x0f,0x00,0x28,0x30,0xcc] +#CHECK: wflpdb %f0, %v31 # encoding: [0xe7,0x0f,0x00,0x28,0x34,0xcc] +#CHECK: wflpdb %f15, %f0 # encoding: [0xe7,0xf0,0x00,0x28,0x30,0xcc] +#CHECK: wflpdb %v31, %f0 # encoding: [0xe7,0xf0,0x00,0x28,0x38,0xcc] +#CHECK: wflpdb %f14, %v17 # encoding: [0xe7,0xe1,0x00,0x28,0x34,0xcc] + + wflpdb %v0, %v0 + wflpdb %v0, %v15 + wflpdb %v0, %v31 + wflpdb %v15, %v0 + wflpdb %v31, %v0 + wflpdb %v14, %v17 + +#CHECK: wfmadb %f0, %f0, %f0, %f0 # encoding: [0xe7,0x00,0x03,0x08,0x00,0x8f] +#CHECK: wfmadb %f0, %f0, %f0, %v31 # encoding: [0xe7,0x00,0x03,0x08,0xf1,0x8f] +#CHECK: wfmadb %f0, %f0, %v31, %f0 # encoding: [0xe7,0x00,0xf3,0x08,0x02,0x8f] +#CHECK: wfmadb %f0, %v31, %f0, %f0 # encoding: [0xe7,0x0f,0x03,0x08,0x04,0x8f] +#CHECK: wfmadb %v31, %f0, %f0, %f0 # encoding: [0xe7,0xf0,0x03,0x08,0x08,0x8f] +#CHECK: wfmadb %f13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x53,0x08,0x97,0x8f] + + wfmadb %v0, %v0, %v0, %v0 + wfmadb %v0, %v0, %v0, %v31 + wfmadb %v0, %v0, %v31, %v0 + wfmadb %v0, %v31, %v0, %v0 + wfmadb %v31, %v0, %v0, %v0 + wfmadb %v13, %v17, %v21, %v25 + +#CHECK: wfmdb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xe7] +#CHECK: wfmdb %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xe7] +#CHECK: wfmdb %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xe7] +#CHECK: wfmdb %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xe7] +#CHECK: wfmdb %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x08,0x3a,0xe7] + + wfmdb %v0, %v0, %v0 + wfmdb %v0, %v0, %v31 + wfmdb %v0, %v31, %v0 + wfmdb %v31, %v0, %v0 + wfmdb %v18, %v3, %v20 + +#CHECK: wfmsdb %f0, %f0, %f0, %f0 # encoding: [0xe7,0x00,0x03,0x08,0x00,0x8e] +#CHECK: wfmsdb %f0, %f0, %f0, %v31 # encoding: [0xe7,0x00,0x03,0x08,0xf1,0x8e] +#CHECK: wfmsdb %f0, %f0, %v31, %f0 # encoding: [0xe7,0x00,0xf3,0x08,0x02,0x8e] +#CHECK: wfmsdb %f0, %v31, %f0, %f0 # encoding: [0xe7,0x0f,0x03,0x08,0x04,0x8e] +#CHECK: wfmsdb %v31, %f0, %f0, %f0 # encoding: [0xe7,0xf0,0x03,0x08,0x08,0x8e] +#CHECK: wfmsdb %f13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x53,0x08,0x97,0x8e] + + wfmsdb %v0, %v0, %v0, %v0 + wfmsdb %v0, %v0, %v0, %v31 + wfmsdb %v0, %v0, %v31, %v0 + wfmsdb %v0, %v31, %v0, %v0 + wfmsdb %v31, %v0, %v0, %v0 + wfmsdb %v13, %v17, %v21, %v25 + +#CHECK: wfsdb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xe2] +#CHECK: wfsdb %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xe2] +#CHECK: wfsdb %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xe2] +#CHECK: wfsdb %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xe2] +#CHECK: wfsdb %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x08,0x3a,0xe2] + + wfsdb %v0, %v0, %v0 + wfsdb %v0, %v0, %v31 + wfsdb %v0, %v31, %v0 + wfsdb %v31, %v0, %v0 + wfsdb %v18, %v3, %v20 + +#CHECK: wfsqdb %f0, %f0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xce] +#CHECK: wfsqdb %f0, %f15 # encoding: [0xe7,0x0f,0x00,0x08,0x30,0xce] +#CHECK: wfsqdb %f0, %v31 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xce] +#CHECK: wfsqdb %f15, %f0 # encoding: [0xe7,0xf0,0x00,0x08,0x30,0xce] +#CHECK: wfsqdb %v31, %f0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xce] +#CHECK: wfsqdb %f14, %v17 # encoding: [0xe7,0xe1,0x00,0x08,0x34,0xce] + + wfsqdb %v0, %v0 + wfsqdb %v0, %v15 + wfsqdb %v0, %v31 + wfsqdb %v15, %v0 + wfsqdb %v31, %v0 + wfsqdb %v14, %v17 + +#CHECK: wftcidb %f0, %f0, 0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0x4a] +#CHECK: wftcidb %f0, %f0, 4095 # encoding: [0xe7,0x00,0xff,0xf8,0x30,0x4a] +#CHECK: wftcidb %f0, %f15, 0 # encoding: [0xe7,0x0f,0x00,0x08,0x30,0x4a] +#CHECK: wftcidb %f0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0x4a] +#CHECK: wftcidb %f15, %f0, 0 # encoding: [0xe7,0xf0,0x00,0x08,0x30,0x4a] +#CHECK: wftcidb %v31, %f0, 0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0x4a] +#CHECK: wftcidb %f4, %v21, 1656 # encoding: [0xe7,0x45,0x67,0x88,0x34,0x4a] + + wftcidb %v0, %v0, 0 + wftcidb %v0, %v0, 4095 + wftcidb %v0, %v15, 0 + wftcidb %v0, %v31, 0 + wftcidb %v15, %v0, 0 + wftcidb %v31, %v0, 0 + wftcidb %v4, %v21, 0x678 + +#CHECK: wldeb %f0, %f0 # encoding: [0xe7,0x00,0x00,0x08,0x20,0xc4] +#CHECK: wldeb %f0, %f15 # encoding: [0xe7,0x0f,0x00,0x08,0x20,0xc4] +#CHECK: wldeb %f0, %v31 # encoding: [0xe7,0x0f,0x00,0x08,0x24,0xc4] +#CHECK: wldeb %f15, %f0 # encoding: [0xe7,0xf0,0x00,0x08,0x20,0xc4] +#CHECK: wldeb %v31, %f0 # encoding: [0xe7,0xf0,0x00,0x08,0x28,0xc4] +#CHECK: wldeb %f14, %v17 # encoding: [0xe7,0xe1,0x00,0x08,0x24,0xc4] + + wldeb %v0, %v0 + wldeb %v0, %v15 + wldeb %v0, %v31 + wldeb %v15, %v0 + wldeb %v31, %v0 + wldeb %v14, %v17 + +#CHECK: wledb %f0, %f0, 0, 0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xc5] +#CHECK: wledb %f0, %f0, 0, 15 # encoding: [0xe7,0x00,0x00,0xf8,0x30,0xc5] +#CHECK: wledb %f0, %f0, 4, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc5] +#CHECK: wledb %f0, %f0, 12, 0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xc5] +#CHECK: wledb %f0, %v31, 0, 0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xc5] +#CHECK: wledb %v31, %f0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xc5] +#CHECK: wledb %f14, %v17, 4, 10 # encoding: [0xe7,0xe1,0x00,0xac,0x34,0xc5] + + wledb %v0, %v0, 0, 0 + wledb %v0, %v0, 0, 15 + wledb %v0, %v0, 4, 0 + wledb %v0, %v0, 12, 0 + wledb %v0, %v31, 0, 0 + wledb %v31, %v0, 0, 0 + wledb %v14, %v17, 4, 10 diff --git a/llvm/test/MC/SystemZ/tokens.s b/llvm/test/MC/SystemZ/tokens.s index 2719752b736..ceadcdb4b1d 100644 --- a/llvm/test/MC/SystemZ/tokens.s +++ b/llvm/test/MC/SystemZ/tokens.s @@ -13,10 +13,16 @@ #CHECK: foo 100(200,%r0), 300 #CHECK: error: invalid instruction #CHECK: foo 100(200,%r1), 300 -#CHECK: error: invalid operand +#CHECK: error: invalid address register #CHECK: foo 100(%a0), 200 #CHECK: error: %r0 used in an address #CHECK: foo 100(%r0), 200 +#CHECK: error: %r0 used in an address +#CHECK: foo 100(%v1,%r0), 200 +#CHECK: error: invalid instruction +#CHECK: foo 100(%v0,%r1), 200 +#CHECK: error: invalid instruction +#CHECK: foo 100(%v31), 200 #CHECK: error: invalid operand #CHECK: foo 100(%r1,%a0), 200 #CHECK: error: %r0 used in an address @@ -45,6 +51,12 @@ #CHECK: foo %a15, 200 #CHECK: error: invalid register #CHECK: foo %a16, 200 +#CHECK: error: invalid instruction +#CHECK: foo %v0, 200 +#CHECK: error: invalid instruction +#CHECK: foo %v31, 200 +#CHECK: error: invalid register +#CHECK: foo %v32, 200 #CHECK: error: invalid register #CHECK: foo %c, 200 #CHECK: error: invalid register @@ -60,6 +72,9 @@ foo 100(200,%r1), 300 foo 100(%a0), 200 foo 100(%r0), 200 + foo 100(%v1,%r0), 200 + foo 100(%v0,%r1), 200 + foo 100(%v31), 200 foo 100(%r1,%a0), 200 foo 100(%r1,%r0), 200 foo 100(%r1,%r2, 200 @@ -74,6 +89,9 @@ foo %a0, 200 foo %a15, 200 foo %a16, 200 + foo %v0, 200 + foo %v31, 200 + foo %v32, 200 foo %c, 200 foo %, 200 foo {, 200 |
