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-rw-r--r--llvm/include/llvm/CodeGen/MachineRegisterInfo.h3
-rw-r--r--llvm/lib/CodeGen/PreAllocSplitting.cpp2
2 files changed, 3 insertions, 2 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
index fd7431ff0bc..dede05f85c0 100644
--- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -216,7 +216,8 @@ public:
/// getRegClassVirtRegs - Return the list of virtual registers of the given
/// target register class.
- std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) {
+ const std::vector<unsigned> &
+ getRegClassVirtRegs(const TargetRegisterClass *RC) const {
return RegClass2VRegMap[RC->getID()];
}
diff --git a/llvm/lib/CodeGen/PreAllocSplitting.cpp b/llvm/lib/CodeGen/PreAllocSplitting.cpp
index eb19be12cee..997e82f11db 100644
--- a/llvm/lib/CodeGen/PreAllocSplitting.cpp
+++ b/llvm/lib/CodeGen/PreAllocSplitting.cpp
@@ -1154,7 +1154,7 @@ PreAllocSplitting::SplitRegLiveIntervals(const TargetRegisterClass **RCs,
// codegen is not modelling. Ignore these barriers for now.
if (!TII->isSafeToMoveRegClassDefs(*RC))
continue;
- std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
+ const std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
unsigned Reg = VRs[i];
if (!LIs->hasInterval(Reg))
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