diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.td | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/machine-outliner-thunk.ll | 47 |
4 files changed, 53 insertions, 5 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp index b29a4cd0a3f..469c9c27ec4 100644 --- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp +++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp @@ -590,7 +590,8 @@ void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) { // Tail calls use pseudo instructions so they have the proper code-gen // attributes (isCall, isReturn, etc.). We lower them to the real // instruction here. - case AArch64::TCRETURNri: { + case AArch64::TCRETURNri: + case AArch64::TCRETURNriALL: { MCInst TmpInst; TmpInst.setOpcode(AArch64::BR); TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index b13f0412e92..f15a41ee468 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -5461,7 +5461,7 @@ void AArch64InstrInfo::buildOutlinedFrame( TailOpcode = AArch64::TCRETURNdi; } else { assert(Call->getOpcode() == AArch64::BLR); - TailOpcode = AArch64::TCRETURNri; + TailOpcode = AArch64::TCRETURNriALL; } MachineInstr *TC = BuildMI(MF, DebugLoc(), get(TailOpcode)) .add(Call->getOperand(0)) diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 9515175dab7..3531d1e1622 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -6635,6 +6635,12 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { Sched<[WriteBrReg]>; def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>, Sched<[WriteBrReg]>; + // Indirect tail-call with any register allowed, used by MachineOutliner when + // this is proven safe. + // FIXME: If we have to add any more hacks like this, we should instead relax + // some verifier checks for outlined functions. + def TCRETURNriALL : Pseudo<(outs), (ins GPR64:$dst, i32imm:$FPDiff), []>, + Sched<[WriteBrReg]>; } def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)), diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-thunk.ll b/llvm/test/CodeGen/AArch64/machine-outliner-thunk.ll index 819c940f78b..fb4265af2d4 100644 --- a/llvm/test/CodeGen/AArch64/machine-outliner-thunk.ll +++ b/llvm/test/CodeGen/AArch64/machine-outliner-thunk.ll @@ -12,7 +12,7 @@ define i32 @a() { ; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_offset w30, -16 -; CHECK-NEXT: bl OUTLINED_FUNCTION_0 +; CHECK-NEXT: bl [[OUTLINED_DIRECT:OUTLINED_FUNCTION_[0-9]+]] ; CHECK-NEXT: add w0, w0, #8 // =8 ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ret @@ -28,7 +28,7 @@ define i32 @b() { ; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_offset w30, -16 -; CHECK-NEXT: bl OUTLINED_FUNCTION_0 +; CHECK-NEXT: bl [[OUTLINED_DIRECT]] ; CHECK-NEXT: add w0, w0, #88 // =88 ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ret @@ -38,7 +38,48 @@ entry: ret i32 %cx } -; CHECK-LABEL: OUTLINED_FUNCTION_0: +define hidden i32 @c(i32 (i32, i32, i32, i32)* %fptr) { +; CHECK-LABEL: c: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w30, -16 +; CHECK-NEXT: bl [[OUTLINED_INDIRECT:OUTLINED_FUNCTION_[0-9]+]] +; CHECK-NEXT: add w0, w0, #8 // =8 +; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret +entry: + %call = tail call i32 %fptr(i32 1, i32 2, i32 3, i32 4) + %add = add nsw i32 %call, 8 + ret i32 %add +} + +define hidden i32 @d(i32 (i32, i32, i32, i32)* %fptr) { +; CHECK-LABEL: d: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w30, -16 +; CHECK-NEXT: bl [[OUTLINED_INDIRECT]] +; CHECK-NEXT: add w0, w0, #88 // =88 +; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret +entry: + %call = tail call i32 %fptr(i32 1, i32 2, i32 3, i32 4) + %add = add nsw i32 %call, 88 + ret i32 %add +} + +; CHECK: [[OUTLINED_INDIRECT]]: +; CHECK: // %bb.0: +; CHECK-NEXT: mov x8, x0 +; CHECK-NEXT: orr w0, wzr, #0x1 +; CHECK-NEXT: orr w1, wzr, #0x2 +; CHECK-NEXT: orr w2, wzr, #0x3 +; CHECK-NEXT: orr w3, wzr, #0x4 +; CHECK-NEXT: br x8 + +; CHECK: [[OUTLINED_DIRECT]]: ; CHECK: // %bb.0: ; CHECK-NEXT: orr w0, wzr, #0x1 ; CHECK-NEXT: orr w1, wzr, #0x2 |
