diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 3 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 25 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll | 20 |
3 files changed, 48 insertions, 0 deletions
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index 4eafe88831a..e3880f0834b 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -338,6 +338,9 @@ public: /// \return The newly created instruction. MachineInstrBuilder buildZExtOrTrunc(unsigned Res, unsigned Op); + /// Build and insert an appropriate cast between two registers of equal size. + MachineInstrBuilder buildCast(unsigned Dst, unsigned Src); + /// Build and insert G_BR \p Dest /// /// G_BR is an unconditional branch to \p Dest. diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 08f29f4621c..1b7c7a6e52b 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -362,6 +362,26 @@ MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(unsigned Res, return buildInstr(Opcode).addDef(Res).addUse(Op); } + +MachineInstrBuilder MachineIRBuilder::buildCast(unsigned Dst, unsigned Src) { + LLT SrcTy = MRI->getType(Src); + LLT DstTy = MRI->getType(Dst); + if (SrcTy == DstTy) + return buildCopy(Dst, Src); + + unsigned Opcode; + if (SrcTy.isPointer() && DstTy.isScalar()) + Opcode = TargetOpcode::G_PTRTOINT; + else if (DstTy.isPointer() && SrcTy.isScalar()) + Opcode = TargetOpcode::G_INTTOPTR; + else { + assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet"); + Opcode = TargetOpcode::G_BITCAST; + } + + return buildInstr(Opcode).addDef(Dst).addUse(Src); +} + MachineInstrBuilder MachineIRBuilder::buildExtract(ArrayRef<unsigned> Results, ArrayRef<uint64_t> Indices, unsigned Src) { @@ -462,6 +482,11 @@ MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res, MachineInstrBuilder MachineIRBuilder::buildInsert(unsigned Res, unsigned Src, unsigned Op, unsigned Index) { + if (MRI->getType(Res).getSizeInBits() == MRI->getType(Op).getSizeInBits()) { + assert(Index == 0 && "insertion past the end of a register"); + return buildCast(Res, Op); + } + return buildInstr(TargetOpcode::G_INSERT) .addDef(Res) .addUse(Src) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index a05c4a8fe41..65a1422c360 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -890,6 +890,26 @@ define void @test_insertvalue(%struct.nested* %addr, i32 %val) { ret void } +define [1 x i64] @test_trivial_insert([1 x i64] %s, i64 %val) { +; CHECK-LABEL: name: test_trivial_insert +; CHECK: [[STRUCT:%[0-9]+]](s64) = COPY %x0 +; CHECK: [[VAL:%[0-9]+]](s64) = COPY %x1 +; CHECK: [[RES:%[0-9]+]](s64) = COPY [[VAL]](s64) +; CHECK: %x0 = COPY [[RES]] + %res = insertvalue [1 x i64] %s, i64 %val, 0 + ret [1 x i64] %res +} + +define [1 x i8*] @test_trivial_insert_ptr([1 x i8*] %s, i8* %val) { +; CHECK-LABEL: name: test_trivial_insert_ptr +; CHECK: [[STRUCT:%[0-9]+]](s64) = COPY %x0 +; CHECK: [[VAL:%[0-9]+]](p0) = COPY %x1 +; CHECK: [[RES:%[0-9]+]](s64) = G_PTRTOINT [[VAL]](p0) +; CHECK: %x0 = COPY [[RES]] + %res = insertvalue [1 x i8*] %s, i8* %val, 0 + ret [1 x i8*] %res +} + ; CHECK-LABEL: name: test_insertvalue_agg ; CHECK: [[SMALLSTRUCT:%[0-9]+]](s64) = G_LOAD ; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD |
