diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrVSX.td | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vsx.ll | 36 |
3 files changed, 49 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 9690557707f..0aa76774c6d 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -567,6 +567,9 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) setCondCodeAction(ISD::SETO, MVT::v2f64, Expand); setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand); + setOperationAction(ISD::LOAD, MVT::v2f64, Legal); + setOperationAction(ISD::STORE, MVT::v2f64, Legal); + addRegisterClass(MVT::f64, &PPC::VSRCRegClass); addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass); @@ -576,6 +579,11 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) setOperationAction(ISD::ADD, MVT::v2i64, Expand); setOperationAction(ISD::SUB, MVT::v2i64, Expand); + setOperationAction(ISD::LOAD, MVT::v2i64, Promote); + AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64); + setOperationAction(ISD::STORE, MVT::v2i64, Promote); + AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64); + addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass); } } diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index 8593ad2eb19..dbd4727c04b 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -775,6 +775,11 @@ def : Pat<(v8i16 (bitconvert v2i64:$A)), def : Pat<(v16i8 (bitconvert v2i64:$A)), (COPY_TO_REGCLASS $A, VRRC)>; +def : Pat<(v2f64 (bitconvert v2i64:$A)), + (COPY_TO_REGCLASS $A, VRRC)>; +def : Pat<(v2i64 (bitconvert v2f64:$A)), + (COPY_TO_REGCLASS $A, VRRC)>; + } // AddedComplexity } // HasVSX diff --git a/llvm/test/CodeGen/PowerPC/vsx.ll b/llvm/test/CodeGen/PowerPC/vsx.ll index e2b78c7effc..7014849a758 100644 --- a/llvm/test/CodeGen/PowerPC/vsx.ll +++ b/llvm/test/CodeGen/PowerPC/vsx.ll @@ -296,3 +296,39 @@ define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) { ; CHECK: blr } +define <2 x double> @test28(<2 x double>* %a) { + %v = load <2 x double>* %a, align 16 + ret <2 x double> %v + +; CHECK-LABEL: @test28 +; CHECK: lxvd2x 34, 0, 3 +; CHECK: blr +} + +define void @test29(<2 x double>* %a, <2 x double> %b) { + store <2 x double> %b, <2 x double>* %a, align 16 + ret void + +; CHECK-LABEL: @test29 +; CHECK: stxvd2x 34, 0, 3 +; CHECK: blr +} + +define <2 x i64> @test30(<2 x i64>* %a) { + %v = load <2 x i64>* %a, align 16 + ret <2 x i64> %v + +; CHECK-LABEL: @test30 +; CHECK: lxvd2x 34, 0, 3 +; CHECK: blr +} + +define void @test31(<2 x i64>* %a, <2 x i64> %b) { + store <2 x i64> %b, <2 x i64>* %a, align 16 + ret void + +; CHECK-LABEL: @test31 +; CHECK: stxvd2x 34, 0, 3 +; CHECK: blr +} + |
