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-rw-r--r--llvm/lib/Target/AMDGPU/SIInstrFormats.td3
-rw-r--r--llvm/lib/Target/AMDGPU/SIInstrInfo.td49
-rw-r--r--llvm/test/MC/AMDGPU/vop3.s27
-rw-r--r--llvm/test/MC/AMDGPU/vopc-errs.s8
-rw-r--r--llvm/test/MC/AMDGPU/vopc.s21
5 files changed, 92 insertions, 16 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrFormats.td b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
index 27d2a9b8ef1..c0b3b51d193 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrFormats.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
@@ -86,7 +86,6 @@ class Enc64 {
}
class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
-def VOPDstVCC : VOPDstOperand <VCCReg>;
let Uses = [EXEC] in {
@@ -101,7 +100,7 @@ class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
}
class VOPCCommon <dag ins, string asm, list<dag> pattern> :
- VOPAnyCommon <(outs VOPDstVCC:$dst), ins, asm, pattern> {
+ VOPAnyCommon <(outs VCCReg:$dst), ins, asm, pattern> {
let DisableEncoding = "$dst";
let VOPC = 1;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 7ecb25a52df..f2558a68957 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1157,6 +1157,11 @@ def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
+class SIInstAlias <string asm, dag result> : InstAlias <asm, result>,
+ PredicateControl {
+ field bit isCompare;
+ field bit isCommutable;
+}
class VOP <string opName> {
string OpName = opName;
@@ -1617,36 +1622,55 @@ let isCodeGenOnly = 0 in {
class VOPC_Pseudo <dag ins, list<dag> pattern, string opName> :
VOPCCommon <ins, "", pattern>,
VOP <opName>,
- SIMCInstr<opName#"_e32", SISubtarget.NONE>,
- MnemonicAlias<opName#"_e32", opName> {
+ SIMCInstr<opName#"_e32", SISubtarget.NONE> {
let isPseudo = 1;
let isCodeGenOnly = 1;
}
-multiclass VOPC_m <vopc op, dag ins, string asm, list<dag> pattern,
- string opName, bit DefExec, string revOpName = ""> {
+multiclass VOPC_m <vopc op, dag ins, string op_asm, list<dag> pattern,
+ string opName, bit DefExec, VOPProfile p,
+ string revOpName = "", string asm = opName#"_e32 "#op_asm,
+ string alias_asm = opName#" "#op_asm> {
def "" : VOPC_Pseudo <ins, pattern, opName>;
+ let AssemblerPredicates = [isSICI] in {
+
def _si : VOPC<op.SI, ins, asm, []>,
SIMCInstr <opName#"_e32", SISubtarget.SI> {
let Defs = !if(DefExec, [EXEC], []);
let hasSideEffects = DefExec;
- let AssemblerPredicates = [isSICI];
}
+ def : SIInstAlias <
+ alias_asm,
+ (!cast<Instruction>(NAME#"_e32_si") VCCReg:$dst, p.Src0RC32:$src0, p.Src1RC32:$src1)
+ >;
+
+ } // End AssemblerPredicates = [isSICI]
+
+
+ let AssemblerPredicates = [isVI] in {
+
def _vi : VOPC<op.VI, ins, asm, []>,
SIMCInstr <opName#"_e32", SISubtarget.VI> {
let Defs = !if(DefExec, [EXEC], []);
let hasSideEffects = DefExec;
- let AssemblerPredicates = [isVI];
}
+
+ def : SIInstAlias <
+ alias_asm,
+ (!cast<Instruction>(NAME#"_e32_vi") VCCReg:$dst, p.Src0RC32:$src0, p.Src1RC32:$src1)
+ >;
+
+ } // End AssemblerPredicates = [isVI]
}
multiclass VOPC_Helper <vopc op, string opName,
dag ins32, string asm32, list<dag> pat32,
dag out64, dag ins64, string asm64, list<dag> pat64,
- bit HasMods, bit DefExec, string revOp> {
- defm _e32 : VOPC_m <op, ins32, opName#asm32, pat32, opName, DefExec>;
+ bit HasMods, bit DefExec, string revOp,
+ VOPProfile p> {
+ defm _e32 : VOPC_m <op, ins32, asm32, pat32, opName, DefExec, p>;
defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
opName, HasMods, DefExec, revOp>;
@@ -1657,8 +1681,9 @@ multiclass VOPC_Helper <vopc op, string opName,
multiclass VOPC_Class_Helper <vopc op, string opName,
dag ins32, string asm32, list<dag> pat32,
dag out64, dag ins64, string asm64, list<dag> pat64,
- bit HasMods, bit DefExec, string revOp> {
- defm _e32 : VOPC_m <op, ins32, opName#asm32, pat32, opName, DefExec>;
+ bit HasMods, bit DefExec, string revOp,
+ VOPProfile p> {
+ defm _e32 : VOPC_m <op, ins32, asm32, pat32, opName, DefExec, p>;
defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
opName, HasMods, DefExec, revOp>,
@@ -1679,7 +1704,7 @@ multiclass VOPCInst <vopc op, string opName,
(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
cond))],
[(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
- P.HasModifiers, DefExec, revOp
+ P.HasModifiers, DefExec, revOp, P
>;
multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
@@ -1691,7 +1716,7 @@ multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
[(set i1:$dst,
(AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
[(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
- P.HasModifiers, DefExec, opName
+ P.HasModifiers, DefExec, opName, P
>;
diff --git a/llvm/test/MC/AMDGPU/vop3.s b/llvm/test/MC/AMDGPU/vop3.s
index 63914675a86..8dfdf5009b3 100644
--- a/llvm/test/MC/AMDGPU/vop3.s
+++ b/llvm/test/MC/AMDGPU/vop3.s
@@ -14,6 +14,11 @@ v_cmp_lt_f32_e64 s[2:3], v4, -v6
// SICI: v_cmp_lt_f32_e64 s[2:3], v4, -v6 ; encoding: [0x02,0x00,0x02,0xd0,0x04,0x0d,0x02,0x40]
// VI: v_cmp_lt_f32_e64 s[2:3], v4, -v6 ; encoding: [0x02,0x00,0x41,0xd0,0x04,0x0d,0x02,0x40]
+// Test forcing e64 with vcc dst
+
+v_cmp_lt_f32_e64 vcc, v4, v6
+// SICI: v_cmp_lt_f32_e64 vcc, v4, v6 ; encoding: [0x6a,0x00,0x02,0xd0,0x04,0x0d,0x02,0x00]
+// VI: v_cmp_lt_f32_e64 vcc, v4, v6 ; encoding: [0x6a,0x00,0x41,0xd0,0x04,0x0d,0x02,0x00]
//
// Modifier tests:
@@ -87,7 +92,27 @@ v_cmp_ge_f32 s[2:3], v4, v6
// SICI: v_cmp_ge_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x0c,0xd0,0x04,0x0d,0x02,0x00]
// VI: v_cmp_ge_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x46,0xd0,0x04,0x0d,0x02,0x00]
-// TODO: Finish VOPC
+// TODO: Add tests for the rest of v_cmp_*_f32
+// TODO: Add tests for v_cmpx_*_f32
+
+v_cmp_f_f64 s[2:3], v[4:5], v[6:7]
+// SICI: v_cmp_f_f64_e64 s[2:3], v[4:5], v[6:7] ; encoding: [0x02,0x00,0x40,0xd0,0x04,0x0d,0x02,0x00]
+// VI: v_cmp_f_f64_e64 s[2:3], v[4:5], v[6:7] ; encoding: [0x02,0x00,0x60,0xd0,0x04,0x0d,0x02,0x00]
+
+// TODO: Add tests for the rest of v_cmp_*_f64
+// TODO: Add tests for the rest of the floating-point comparision instructions.
+
+v_cmp_f_i32 s[2:3], v4, v6
+// SICI: v_cmp_f_i32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x00,0xd1,0x04,0x0d,0x02,0x00]
+// VI: v_cmp_f_i32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0xc0,0xd0,0x04,0x0d,0x02,0x00]
+
+// TODO: Add test for the rest of v_cmp_*_i32
+
+v_cmp_f_i64 s[2:3], v[4:5], v[6:7]
+// SICI: v_cmp_f_i64_e64 s[2:3], v[4:5], v[6:7] ; encoding: [0x02,0x00,0x40,0xd1,0x04,0x0d,0x02,0x00]
+// VI: v_cmp_f_i64_e64 s[2:3], v[4:5], v[6:7] ; encoding: [0x02,0x00,0xe0,0xd0,0x04,0x0d,0x02,0x00]
+
+// TODO: Add tests for the rest of the instructions.
//===----------------------------------------------------------------------===//
// VOP1 Instructions
diff --git a/llvm/test/MC/AMDGPU/vopc-errs.s b/llvm/test/MC/AMDGPU/vopc-errs.s
new file mode 100644
index 00000000000..06c6752a844
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/vopc-errs.s
@@ -0,0 +1,8 @@
+// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck %s
+
+// Force 32-bit encoding with non-vcc result
+
+v_cmp_lt_f32_e32 s[0:1], v2, v4
+// CHECK: 18: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/vopc.s b/llvm/test/MC/AMDGPU/vopc.s
index 2d8547c5f95..0692a0e72ce 100644
--- a/llvm/test/MC/AMDGPU/vopc.s
+++ b/llvm/test/MC/AMDGPU/vopc.s
@@ -44,5 +44,24 @@ v_cmp_lt_f32 vcc, v2, v4
// SICI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c]
// VI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c]
-// TODO: Add tests for the rest of the instructions.
+// TODO: Add tests for the rest of v_cmp_*_f32
+// TODO: Add tests for v_cmpx_*_f32
+
+v_cmp_f_f64 vcc, v[2:3], v[4:5]
+// SICI: v_cmp_f_f64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0x40,0x7c]
+// VI: v_cmp_f_f64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0xc0,0x7c]
+
+// TODO: Add tests for the rest of v_cmp_*_f64
+// TODO: Add tests for the rest of the floating-point comparision instructions.
+
+v_cmp_f_i32 vcc, v2, v4
+// SICI: v_cmp_f_i32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x00,0x7d]
+// VI: v_cmp_f_i32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7d]
+// TODO: Add test for the rest of v_cmp_*_i32
+
+v_cmp_f_i64 vcc, v[2:3], v[4:5]
+// SICI: v_cmp_f_i64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0x40,0x7d]
+// VI: v_cmp_f_i64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0xc0,0x7d]
+
+// TODO: Add tests for the rest of the instructions.
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