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-rw-r--r--llvm/include/llvm/CodeGen/MachineRegionInfo.h130
-rw-r--r--llvm/include/llvm/CodeGen/MachineRegisterInfo.h98
-rw-r--r--llvm/include/llvm/CodeGen/MachineScheduler.h11
-rw-r--r--llvm/include/llvm/CodeGen/PBQP/CostAllocator.h61
-rw-r--r--llvm/include/llvm/CodeGen/PBQP/Graph.h99
-rw-r--r--llvm/include/llvm/CodeGen/PBQP/Math.h22
-rw-r--r--llvm/include/llvm/CodeGen/PBQP/ReductionRules.h36
-rw-r--r--llvm/include/llvm/CodeGen/PBQP/Solution.h2
-rw-r--r--llvm/include/llvm/CodeGen/PBQPRAConstraint.h22
-rw-r--r--llvm/include/llvm/CodeGen/RegAllocPBQP.h41
-rw-r--r--llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h66
-rw-r--r--llvm/lib/CodeGen/MachineRegionInfo.cpp46
-rw-r--r--llvm/lib/CodeGen/RegAllocPBQP.cpp40
-rw-r--r--llvm/lib/CodeGen/ScheduleDAGInstrs.cpp80
-rw-r--r--llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.h7
15 files changed, 419 insertions, 342 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineRegionInfo.h b/llvm/include/llvm/CodeGen/MachineRegionInfo.h
index 21f847c7e5b..8394b58d0a1 100644
--- a/llvm/include/llvm/CodeGen/MachineRegionInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineRegionInfo.h
@@ -10,83 +10,77 @@
#ifndef LLVM_CODEGEN_MACHINEREGIONINFO_H
#define LLVM_CODEGEN_MACHINEREGIONINFO_H
+#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/Analysis/RegionInfo.h"
#include "llvm/Analysis/RegionIterator.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominanceFrontier.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
-
+#include <cassert>
namespace llvm {
-class MachineDominatorTree;
struct MachinePostDominatorTree;
class MachineRegion;
class MachineRegionNode;
class MachineRegionInfo;
-template<>
-struct RegionTraits<MachineFunction> {
- typedef MachineFunction FuncT;
- typedef MachineBasicBlock BlockT;
- typedef MachineRegion RegionT;
- typedef MachineRegionNode RegionNodeT;
- typedef MachineRegionInfo RegionInfoT;
- typedef MachineDominatorTree DomTreeT;
- typedef MachineDomTreeNode DomTreeNodeT;
- typedef MachinePostDominatorTree PostDomTreeT;
- typedef MachineDominanceFrontier DomFrontierT;
- typedef MachineInstr InstT;
- typedef MachineLoop LoopT;
- typedef MachineLoopInfo LoopInfoT;
+template <> struct RegionTraits<MachineFunction> {
+ using FuncT = MachineFunction;
+ using BlockT = MachineBasicBlock;
+ using RegionT = MachineRegion;
+ using RegionNodeT = MachineRegionNode;
+ using RegionInfoT = MachineRegionInfo;
+ using DomTreeT = MachineDominatorTree;
+ using DomTreeNodeT = MachineDomTreeNode;
+ using PostDomTreeT = MachinePostDominatorTree;
+ using DomFrontierT = MachineDominanceFrontier;
+ using InstT = MachineInstr;
+ using LoopT = MachineLoop;
+ using LoopInfoT = MachineLoopInfo;
static unsigned getNumSuccessors(MachineBasicBlock *BB) {
return BB->succ_size();
}
};
-
class MachineRegionNode : public RegionNodeBase<RegionTraits<MachineFunction>> {
public:
- inline MachineRegionNode(MachineRegion *Parent,
- MachineBasicBlock *Entry,
+ inline MachineRegionNode(MachineRegion *Parent, MachineBasicBlock *Entry,
bool isSubRegion = false)
- : RegionNodeBase<RegionTraits<MachineFunction>>(Parent, Entry, isSubRegion) {
-
- }
+ : RegionNodeBase<RegionTraits<MachineFunction>>(Parent, Entry,
+ isSubRegion) {}
bool operator==(const MachineRegion &RN) const {
- return this == reinterpret_cast<const MachineRegionNode*>(&RN);
+ return this == reinterpret_cast<const MachineRegionNode *>(&RN);
}
};
class MachineRegion : public RegionBase<RegionTraits<MachineFunction>> {
public:
MachineRegion(MachineBasicBlock *Entry, MachineBasicBlock *Exit,
- MachineRegionInfo* RI,
- MachineDominatorTree *DT, MachineRegion *Parent = nullptr);
+ MachineRegionInfo *RI, MachineDominatorTree *DT,
+ MachineRegion *Parent = nullptr);
~MachineRegion();
bool operator==(const MachineRegionNode &RN) const {
- return &RN == reinterpret_cast<const MachineRegionNode*>(this);
+ return &RN == reinterpret_cast<const MachineRegionNode *>(this);
}
};
class MachineRegionInfo : public RegionInfoBase<RegionTraits<MachineFunction>> {
public:
explicit MachineRegionInfo();
-
~MachineRegionInfo() override;
// updateStatistics - Update statistic about created regions.
void updateStatistics(MachineRegion *R) final;
- void recalculate(MachineFunction &F,
- MachineDominatorTree *DT,
- MachinePostDominatorTree *PDT,
- MachineDominanceFrontier *DF);
+ void recalculate(MachineFunction &F, MachineDominatorTree *DT,
+ MachinePostDominatorTree *PDT, MachineDominanceFrontier *DF);
};
class MachineRegionInfoPass : public MachineFunctionPass {
@@ -94,17 +88,13 @@ class MachineRegionInfoPass : public MachineFunctionPass {
public:
static char ID;
- explicit MachineRegionInfoPass();
+ explicit MachineRegionInfoPass();
~MachineRegionInfoPass() override;
- MachineRegionInfo &getRegionInfo() {
- return RI;
- }
+ MachineRegionInfo &getRegionInfo() { return RI; }
- const MachineRegionInfo &getRegionInfo() const {
- return RI;
- }
+ const MachineRegionInfo &getRegionInfo() const { return RI; }
/// @name MachineFunctionPass interface
//@{
@@ -117,66 +107,76 @@ public:
//@}
};
-
template <>
template <>
-inline MachineBasicBlock* RegionNodeBase<RegionTraits<MachineFunction>>::getNodeAs<MachineBasicBlock>() const {
+inline MachineBasicBlock *
+RegionNodeBase<RegionTraits<MachineFunction>>::getNodeAs<MachineBasicBlock>()
+ const {
assert(!isSubRegion() && "This is not a MachineBasicBlock RegionNode!");
return getEntry();
}
-template<>
-template<>
-inline MachineRegion* RegionNodeBase<RegionTraits<MachineFunction>>::getNodeAs<MachineRegion>() const {
+template <>
+template <>
+inline MachineRegion *
+RegionNodeBase<RegionTraits<MachineFunction>>::getNodeAs<MachineRegion>()
+ const {
assert(isSubRegion() && "This is not a subregion RegionNode!");
- auto Unconst = const_cast<RegionNodeBase<RegionTraits<MachineFunction>>*>(this);
- return reinterpret_cast<MachineRegion*>(Unconst);
+ auto Unconst =
+ const_cast<RegionNodeBase<RegionTraits<MachineFunction>> *>(this);
+ return reinterpret_cast<MachineRegion *>(Unconst);
}
-
RegionNodeGraphTraits(MachineRegionNode, MachineBasicBlock, MachineRegion);
-RegionNodeGraphTraits(const MachineRegionNode, MachineBasicBlock, MachineRegion);
+RegionNodeGraphTraits(const MachineRegionNode, MachineBasicBlock,
+ MachineRegion);
RegionGraphTraits(MachineRegion, MachineRegionNode);
RegionGraphTraits(const MachineRegion, const MachineRegionNode);
-template <> struct GraphTraits<MachineRegionInfo*>
- : public GraphTraits<FlatIt<MachineRegionNode*> > {
- typedef df_iterator<NodeRef, df_iterator_default_set<NodeRef>, false,
- GraphTraits<FlatIt<NodeRef>>>
- nodes_iterator;
+template <>
+struct GraphTraits<MachineRegionInfo *>
+ : public GraphTraits<FlatIt<MachineRegionNode *>> {
+ using nodes_iterator = df_iterator<NodeRef, df_iterator_default_set<NodeRef>,
+ false, GraphTraits<FlatIt<NodeRef>>>;
static NodeRef getEntryNode(MachineRegionInfo *RI) {
- return GraphTraits<FlatIt<MachineRegion*> >::getEntryNode(RI->getTopLevelRegion());
+ return GraphTraits<FlatIt<MachineRegion *>>::getEntryNode(
+ RI->getTopLevelRegion());
}
- static nodes_iterator nodes_begin(MachineRegionInfo* RI) {
+
+ static nodes_iterator nodes_begin(MachineRegionInfo *RI) {
return nodes_iterator::begin(getEntryNode(RI));
}
+
static nodes_iterator nodes_end(MachineRegionInfo *RI) {
return nodes_iterator::end(getEntryNode(RI));
}
};
-template <> struct GraphTraits<MachineRegionInfoPass*>
- : public GraphTraits<MachineRegionInfo *> {
- typedef df_iterator<NodeRef, df_iterator_default_set<NodeRef>, false,
- GraphTraits<FlatIt<NodeRef>>>
- nodes_iterator;
+template <>
+struct GraphTraits<MachineRegionInfoPass *>
+ : public GraphTraits<MachineRegionInfo *> {
+ using nodes_iterator = df_iterator<NodeRef, df_iterator_default_set<NodeRef>,
+ false, GraphTraits<FlatIt<NodeRef>>>;
static NodeRef getEntryNode(MachineRegionInfoPass *RI) {
- return GraphTraits<MachineRegionInfo*>::getEntryNode(&RI->getRegionInfo());
+ return GraphTraits<MachineRegionInfo *>::getEntryNode(&RI->getRegionInfo());
}
- static nodes_iterator nodes_begin(MachineRegionInfoPass* RI) {
- return GraphTraits<MachineRegionInfo*>::nodes_begin(&RI->getRegionInfo());
+
+ static nodes_iterator nodes_begin(MachineRegionInfoPass *RI) {
+ return GraphTraits<MachineRegionInfo *>::nodes_begin(&RI->getRegionInfo());
}
+
static nodes_iterator nodes_end(MachineRegionInfoPass *RI) {
- return GraphTraits<MachineRegionInfo*>::nodes_end(&RI->getRegionInfo());
+ return GraphTraits<MachineRegionInfo *>::nodes_end(&RI->getRegionInfo());
}
};
extern template class RegionBase<RegionTraits<MachineFunction>>;
extern template class RegionNodeBase<RegionTraits<MachineFunction>>;
extern template class RegionInfoBase<RegionTraits<MachineFunction>>;
-}
-#endif
+} // end namespace llvm
+
+#endif // LLVM_CODEGEN_MACHINEREGIONINFO_H
diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
index 1026654da3d..c027783aae5 100644
--- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -14,11 +14,13 @@
#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
+#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/ADT/PointerUnion.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
#include "llvm/CodeGen/LowLevelType.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
@@ -41,8 +43,8 @@ namespace llvm {
class PSetIterator;
/// Convenient type to represent either a register class or a register bank.
-typedef PointerUnion<const TargetRegisterClass *, const RegisterBank *>
- RegClassOrRegBank;
+using RegClassOrRegBank =
+ PointerUnion<const TargetRegisterClass *, const RegisterBank *>;
/// MachineRegisterInfo - Keep track of information for virtual and physical
/// registers, including vreg register classes, use/def chains for registers,
@@ -125,7 +127,7 @@ private:
/// started.
BitVector ReservedRegs;
- typedef DenseMap<unsigned, LLT> VRegToTypeMap;
+ using VRegToTypeMap = DenseMap<unsigned, LLT>;
/// Map generic virtual registers to their actual size.
mutable std::unique_ptr<VRegToTypeMap> VRegToType;
@@ -266,8 +268,8 @@ public:
/// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
/// register.
- typedef defusechain_iterator<true,true,false,true,false,false>
- reg_iterator;
+ using reg_iterator =
+ defusechain_iterator<true, true, false, true, false, false>;
reg_iterator reg_begin(unsigned RegNo) const {
return reg_iterator(getRegUseDefListHead(RegNo));
}
@@ -279,8 +281,8 @@ public:
/// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
/// of the specified register, stepping by MachineInstr.
- typedef defusechain_instr_iterator<true,true,false,false,true,false>
- reg_instr_iterator;
+ using reg_instr_iterator =
+ defusechain_instr_iterator<true, true, false, false, true, false>;
reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
return reg_instr_iterator(getRegUseDefListHead(RegNo));
}
@@ -295,8 +297,8 @@ public:
/// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
/// of the specified register, stepping by bundle.
- typedef defusechain_instr_iterator<true,true,false,false,false,true>
- reg_bundle_iterator;
+ using reg_bundle_iterator =
+ defusechain_instr_iterator<true, true, false, false, false, true>;
reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
return reg_bundle_iterator(getRegUseDefListHead(RegNo));
}
@@ -314,8 +316,8 @@ public:
/// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
/// of the specified register, skipping those marked as Debug.
- typedef defusechain_iterator<true,true,true,true,false,false>
- reg_nodbg_iterator;
+ using reg_nodbg_iterator =
+ defusechain_iterator<true, true, true, true, false, false>;
reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
}
@@ -331,8 +333,8 @@ public:
/// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
/// all defs and uses of the specified register, stepping by MachineInstr,
/// skipping those marked as Debug.
- typedef defusechain_instr_iterator<true,true,true,false,true,false>
- reg_instr_nodbg_iterator;
+ using reg_instr_nodbg_iterator =
+ defusechain_instr_iterator<true, true, true, false, true, false>;
reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
}
@@ -348,8 +350,8 @@ public:
/// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
/// all defs and uses of the specified register, stepping by bundle,
/// skipping those marked as Debug.
- typedef defusechain_instr_iterator<true,true,true,false,false,true>
- reg_bundle_nodbg_iterator;
+ using reg_bundle_nodbg_iterator =
+ defusechain_instr_iterator<true, true, true, false, false, true>;
reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
}
@@ -369,8 +371,8 @@ public:
}
/// def_iterator/def_begin/def_end - Walk all defs of the specified register.
- typedef defusechain_iterator<false,true,false,true,false,false>
- def_iterator;
+ using def_iterator =
+ defusechain_iterator<false, true, false, true, false, false>;
def_iterator def_begin(unsigned RegNo) const {
return def_iterator(getRegUseDefListHead(RegNo));
}
@@ -382,8 +384,8 @@ public:
/// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
/// specified register, stepping by MachineInst.
- typedef defusechain_instr_iterator<false,true,false,false,true,false>
- def_instr_iterator;
+ using def_instr_iterator =
+ defusechain_instr_iterator<false, true, false, false, true, false>;
def_instr_iterator def_instr_begin(unsigned RegNo) const {
return def_instr_iterator(getRegUseDefListHead(RegNo));
}
@@ -398,8 +400,8 @@ public:
/// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
/// specified register, stepping by bundle.
- typedef defusechain_instr_iterator<false,true,false,false,false,true>
- def_bundle_iterator;
+ using def_bundle_iterator =
+ defusechain_instr_iterator<false, true, false, false, false, true>;
def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
return def_bundle_iterator(getRegUseDefListHead(RegNo));
}
@@ -425,8 +427,8 @@ public:
}
/// use_iterator/use_begin/use_end - Walk all uses of the specified register.
- typedef defusechain_iterator<true,false,false,true,false,false>
- use_iterator;
+ using use_iterator =
+ defusechain_iterator<true, false, false, true, false, false>;
use_iterator use_begin(unsigned RegNo) const {
return use_iterator(getRegUseDefListHead(RegNo));
}
@@ -438,8 +440,8 @@ public:
/// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
/// specified register, stepping by MachineInstr.
- typedef defusechain_instr_iterator<true,false,false,false,true,false>
- use_instr_iterator;
+ using use_instr_iterator =
+ defusechain_instr_iterator<true, false, false, false, true, false>;
use_instr_iterator use_instr_begin(unsigned RegNo) const {
return use_instr_iterator(getRegUseDefListHead(RegNo));
}
@@ -454,8 +456,8 @@ public:
/// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
/// specified register, stepping by bundle.
- typedef defusechain_instr_iterator<true,false,false,false,false,true>
- use_bundle_iterator;
+ using use_bundle_iterator =
+ defusechain_instr_iterator<true, false, false, false, false, true>;
use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
return use_bundle_iterator(getRegUseDefListHead(RegNo));
}
@@ -482,8 +484,8 @@ public:
/// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
/// specified register, skipping those marked as Debug.
- typedef defusechain_iterator<true,false,true,true,false,false>
- use_nodbg_iterator;
+ using use_nodbg_iterator =
+ defusechain_iterator<true, false, true, true, false, false>;
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
return use_nodbg_iterator(getRegUseDefListHead(RegNo));
}
@@ -499,8 +501,8 @@ public:
/// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
/// all uses of the specified register, stepping by MachineInstr, skipping
/// those marked as Debug.
- typedef defusechain_instr_iterator<true,false,true,false,true,false>
- use_instr_nodbg_iterator;
+ using use_instr_nodbg_iterator =
+ defusechain_instr_iterator<true, false, true, false, true, false>;
use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
}
@@ -516,8 +518,8 @@ public:
/// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
/// all uses of the specified register, stepping by bundle, skipping
/// those marked as Debug.
- typedef defusechain_instr_iterator<true,false,true,false,false,true>
- use_bundle_nodbg_iterator;
+ using use_bundle_nodbg_iterator =
+ defusechain_instr_iterator<true, false, true, false, false, true>;
use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
}
@@ -593,7 +595,6 @@ public:
/// Return the register class of the specified virtual register.
/// This shouldn't be used directly unless \p Reg has a register class.
/// \see getRegClassOrNull when this might happen.
- ///
const TargetRegisterClass *getRegClass(unsigned Reg) const {
assert(VRegInfo[Reg].first.is<const TargetRegisterClass *>() &&
"Register class not set, wrong accessor");
@@ -620,7 +621,6 @@ public:
/// a register bank or has been assigned a register class.
/// \note It is possible to get the register bank from the register class via
/// RegisterBankInfo::getRegBankFromRegClass.
- ///
const RegisterBank *getRegBankOrNull(unsigned Reg) const {
const RegClassOrRegBank &Val = VRegInfo[Reg].first;
return Val.dyn_cast<const RegisterBank *>();
@@ -629,17 +629,14 @@ public:
/// Return the register bank or register class of \p Reg.
/// \note Before the register bank gets assigned (i.e., before the
/// RegBankSelect pass) \p Reg may not have either.
- ///
const RegClassOrRegBank &getRegClassOrRegBank(unsigned Reg) const {
return VRegInfo[Reg].first;
}
/// setRegClass - Set the register class of the specified virtual register.
- ///
void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
/// Set the register bank to \p RegBank for \p Reg.
- ///
void setRegBank(unsigned Reg, const RegisterBank &RegBank);
void setRegClassOrRegBank(unsigned Reg,
@@ -653,7 +650,6 @@ public:
/// new register class, or NULL if no such class exists.
/// This should only be used when the constraint is known to be trivial, like
/// GR32 -> GR32_NOSP. Beware of increasing register pressure.
- ///
const TargetRegisterClass *constrainRegClass(unsigned Reg,
const TargetRegisterClass *RC,
unsigned MinNumRegs = 0);
@@ -665,12 +661,10 @@ public:
/// This method can be used after constraints have been removed from a
/// virtual register, for example after removing instructions or splitting
/// the live range.
- ///
bool recomputeRegClass(unsigned Reg);
/// createVirtualRegister - Create and return a new virtual register in the
/// function with the specified register class.
- ///
unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
/// Accessor for VRegToType. This accessor should only be used
@@ -704,7 +698,6 @@ public:
unsigned createIncompleteVirtualRegister();
/// getNumVirtRegs - Return the number of virtual registers created.
- ///
unsigned getNumVirtRegs() const { return VRegInfo.size(); }
/// clearVirtRegs - Remove all virtual registers (after physreg assignment).
@@ -810,7 +803,6 @@ public:
///
/// Reserved registers may belong to an allocatable register class, but the
/// target has explicitly requested that they are not used.
- ///
bool isReserved(unsigned PhysReg) const {
return getReservedRegs().test(PhysReg);
}
@@ -838,8 +830,8 @@ public:
// Iteration support for the live-ins set. It's kept in sorted order
// by register number.
- typedef std::vector<std::pair<unsigned,unsigned>>::const_iterator
- livein_iterator;
+ using livein_iterator =
+ std::vector<std::pair<unsigned,unsigned>>::const_iterator;
livein_iterator livein_begin() const { return LiveIns.begin(); }
livein_iterator livein_end() const { return LiveIns.end(); }
bool livein_empty() const { return LiveIns.empty(); }
@@ -910,10 +902,10 @@ public:
}
public:
- typedef std::iterator<std::forward_iterator_tag,
- MachineInstr, ptrdiff_t>::reference reference;
- typedef std::iterator<std::forward_iterator_tag,
- MachineInstr, ptrdiff_t>::pointer pointer;
+ using reference = std::iterator<std::forward_iterator_tag,
+ MachineInstr, ptrdiff_t>::reference;
+ using pointer = std::iterator<std::forward_iterator_tag,
+ MachineInstr, ptrdiff_t>::pointer;
defusechain_iterator() = default;
@@ -1016,10 +1008,10 @@ public:
}
public:
- typedef std::iterator<std::forward_iterator_tag,
- MachineInstr, ptrdiff_t>::reference reference;
- typedef std::iterator<std::forward_iterator_tag,
- MachineInstr, ptrdiff_t>::pointer pointer;
+ using reference = std::iterator<std::forward_iterator_tag,
+ MachineInstr, ptrdiff_t>::reference;
+ using pointer = std::iterator<std::forward_iterator_tag,
+ MachineInstr, ptrdiff_t>::pointer;
defusechain_instr_iterator() = default;
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index 6b2a16e1d36..3b02ec400ab 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -104,10 +104,15 @@ extern cl::opt<bool> ForceBottomUp;
class LiveIntervals;
class MachineDominatorTree;
+class MachineFunction;
+class MachineInstr;
class MachineLoopInfo;
class RegisterClassInfo;
class SchedDFSResult;
class ScheduleHazardRecognizer;
+class TargetInstrInfo;
+class TargetPassConfig;
+class TargetRegisterInfo;
/// MachineSchedContext provides enough context from the MachineScheduler pass
/// for the target to instantiate a scheduler.
@@ -129,10 +134,10 @@ struct MachineSchedContext {
/// schedulers.
class MachineSchedRegistry : public MachinePassRegistryNode {
public:
- typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedContext *);
+ using ScheduleDAGCtor = ScheduleDAGInstrs *(*)(MachineSchedContext *);
// RegisterPassParser requires a (misnamed) FunctionPassCtor type.
- typedef ScheduleDAGCtor FunctionPassCtor;
+ using FunctionPassCtor = ScheduleDAGCtor;
static MachinePassRegistry Registry;
@@ -527,7 +532,7 @@ public:
unsigned size() const { return Queue.size(); }
- typedef std::vector<SUnit*>::iterator iterator;
+ using iterator = std::vector<SUnit*>::iterator;
iterator begin() { return Queue.begin(); }
diff --git a/llvm/include/llvm/CodeGen/PBQP/CostAllocator.h b/llvm/include/llvm/CodeGen/PBQP/CostAllocator.h
index 02d39fe383f..bde451ae1fc 100644
--- a/llvm/include/llvm/CodeGen/PBQP/CostAllocator.h
+++ b/llvm/include/llvm/CodeGen/PBQP/CostAllocator.h
@@ -1,4 +1,4 @@
-//===---------- CostAllocator.h - PBQP Cost Allocator -----------*- C++ -*-===//
+//===- CostAllocator.h - PBQP Cost Allocator --------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -19,26 +19,28 @@
#define LLVM_CODEGEN_PBQP_COSTALLOCATOR_H
#include "llvm/ADT/DenseSet.h"
+#include <algorithm>
+#include <cstdint>
#include <memory>
-#include <type_traits>
namespace llvm {
namespace PBQP {
-template <typename ValueT>
-class ValuePool {
+template <typename ValueT> class ValuePool {
public:
- typedef std::shared_ptr<const ValueT> PoolRef;
+ using PoolRef = std::shared_ptr<const ValueT>;
private:
-
class PoolEntry : public std::enable_shared_from_this<PoolEntry> {
public:
template <typename ValueKeyT>
PoolEntry(ValuePool &Pool, ValueKeyT Value)
: Pool(Pool), Value(std::move(Value)) {}
+
~PoolEntry() { Pool.removeEntry(this); }
- const ValueT& getValue() const { return Value; }
+
+ const ValueT &getValue() const { return Value; }
+
private:
ValuePool &Pool;
ValueT Value;
@@ -46,10 +48,10 @@ private:
class PoolEntryDSInfo {
public:
- static inline PoolEntry* getEmptyKey() { return nullptr; }
+ static inline PoolEntry *getEmptyKey() { return nullptr; }
- static inline PoolEntry* getTombstoneKey() {
- return reinterpret_cast<PoolEntry*>(static_cast<uintptr_t>(1));
+ static inline PoolEntry *getTombstoneKey() {
+ return reinterpret_cast<PoolEntry *>(static_cast<uintptr_t>(1));
}
template <typename ValueKeyT>
@@ -66,8 +68,7 @@ private:
}
template <typename ValueKeyT1, typename ValueKeyT2>
- static
- bool isEqual(const ValueKeyT1 &C1, const ValueKeyT2 &C2) {
+ static bool isEqual(const ValueKeyT1 &C1, const ValueKeyT2 &C2) {
return C1 == C2;
}
@@ -83,10 +84,9 @@ private:
return P1 == P2;
return isEqual(P1->getValue(), P2);
}
-
};
- typedef DenseSet<PoolEntry*, PoolEntryDSInfo> EntrySetT;
+ using EntrySetT = DenseSet<PoolEntry *, PoolEntryDSInfo>;
EntrySetT EntrySet;
@@ -105,28 +105,31 @@ public:
}
};
-template <typename VectorT, typename MatrixT>
-class PoolCostAllocator {
+template <typename VectorT, typename MatrixT> class PoolCostAllocator {
private:
- typedef ValuePool<VectorT> VectorCostPool;
- typedef ValuePool<MatrixT> MatrixCostPool;
+ using VectorCostPool = ValuePool<VectorT>;
+ using MatrixCostPool = ValuePool<MatrixT>;
+
public:
- typedef VectorT Vector;
- typedef MatrixT Matrix;
- typedef typename VectorCostPool::PoolRef VectorPtr;
- typedef typename MatrixCostPool::PoolRef MatrixPtr;
+ using Vector = VectorT;
+ using Matrix = MatrixT;
+ using VectorPtr = typename VectorCostPool::PoolRef;
+ using MatrixPtr = typename MatrixCostPool::PoolRef;
+
+ template <typename VectorKeyT> VectorPtr getVector(VectorKeyT v) {
+ return VectorPool.getValue(std::move(v));
+ }
- template <typename VectorKeyT>
- VectorPtr getVector(VectorKeyT v) { return VectorPool.getValue(std::move(v)); }
+ template <typename MatrixKeyT> MatrixPtr getMatrix(MatrixKeyT m) {
+ return MatrixPool.getValue(std::move(m));
+ }
- template <typename MatrixKeyT>
- MatrixPtr getMatrix(MatrixKeyT m) { return MatrixPool.getValue(std::move(m)); }
private:
VectorCostPool VectorPool;
MatrixCostPool MatrixPool;
};
-} // namespace PBQP
-} // namespace llvm
+} // end namespace PBQP
+} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_PBQP_COSTALLOCATOR_H
diff --git a/llvm/include/llvm/CodeGen/PBQP/Graph.h b/llvm/include/llvm/CodeGen/PBQP/Graph.h
index 83487e6a808..e94878ced10 100644
--- a/llvm/include/llvm/CodeGen/PBQP/Graph.h
+++ b/llvm/include/llvm/CodeGen/PBQP/Graph.h
@@ -1,4 +1,4 @@
-//===-------------------- Graph.h - PBQP Graph ------------------*- C++ -*-===//
+//===- Graph.h - PBQP Graph -------------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -11,16 +11,14 @@
//
//===----------------------------------------------------------------------===//
-
#ifndef LLVM_CODEGEN_PBQP_GRAPH_H
#define LLVM_CODEGEN_PBQP_GRAPH_H
#include "llvm/ADT/STLExtras.h"
-#include "llvm/Support/Debug.h"
#include <algorithm>
#include <cassert>
+#include <iterator>
#include <limits>
-#include <utility>
#include <vector>
namespace llvm {
@@ -28,8 +26,8 @@ namespace PBQP {
class GraphBase {
public:
- typedef unsigned NodeId;
- typedef unsigned EdgeId;
+ using NodeId = unsigned;
+ using EdgeId = unsigned;
/// @brief Returns a value representing an invalid (non-existent) node.
static NodeId invalidNodeId() {
@@ -48,32 +46,32 @@ namespace PBQP {
template <typename SolverT>
class Graph : public GraphBase {
private:
- typedef typename SolverT::CostAllocator CostAllocator;
+ using CostAllocator = typename SolverT::CostAllocator;
+
public:
- typedef typename SolverT::RawVector RawVector;
- typedef typename SolverT::RawMatrix RawMatrix;
- typedef typename SolverT::Vector Vector;
- typedef typename SolverT::Matrix Matrix;
- typedef typename CostAllocator::VectorPtr VectorPtr;
- typedef typename CostAllocator::MatrixPtr MatrixPtr;
- typedef typename SolverT::NodeMetadata NodeMetadata;
- typedef typename SolverT::EdgeMetadata EdgeMetadata;
- typedef typename SolverT::GraphMetadata GraphMetadata;
+ using RawVector = typename SolverT::RawVector;
+ using RawMatrix = typename SolverT::RawMatrix;
+ using Vector = typename SolverT::Vector;
+ using Matrix = typename SolverT::Matrix;
+ using VectorPtr = typename CostAllocator::VectorPtr;
+ using MatrixPtr = typename CostAllocator::MatrixPtr;
+ using NodeMetadata = typename SolverT::NodeMetadata;
+ using EdgeMetadata = typename SolverT::EdgeMetadata;
+ using GraphMetadata = typename SolverT::GraphMetadata;
private:
-
class NodeEntry {
public:
- typedef std::vector<EdgeId> AdjEdgeList;
- typedef AdjEdgeList::size_type AdjEdgeIdx;
- typedef AdjEdgeList::const_iterator AdjEdgeItr;
+ using AdjEdgeList = std::vector<EdgeId>;
+ using AdjEdgeIdx = AdjEdgeList::size_type;
+ using AdjEdgeItr = AdjEdgeList::const_iterator;
+
+ NodeEntry(VectorPtr Costs) : Costs(std::move(Costs)) {}
static AdjEdgeIdx getInvalidAdjEdgeIdx() {
return std::numeric_limits<AdjEdgeIdx>::max();
}
- NodeEntry(VectorPtr Costs) : Costs(std::move(Costs)) {}
-
AdjEdgeIdx addAdjEdgeId(EdgeId EId) {
AdjEdgeIdx Idx = AdjEdgeIds.size();
AdjEdgeIds.push_back(EId);
@@ -96,6 +94,7 @@ namespace PBQP {
VectorPtr Costs;
NodeMetadata Metadata;
+
private:
AdjEdgeList AdjEdgeIds;
};
@@ -150,8 +149,10 @@ namespace PBQP {
NodeId getN1Id() const { return NIds[0]; }
NodeId getN2Id() const { return NIds[1]; }
+
MatrixPtr Costs;
EdgeMetadata Metadata;
+
private:
NodeId NIds[2];
typename NodeEntry::AdjEdgeIdx ThisEdgeAdjIdxs[2];
@@ -161,18 +162,20 @@ namespace PBQP {
GraphMetadata Metadata;
CostAllocator CostAlloc;
- SolverT *Solver;
+ SolverT *Solver = nullptr;
- typedef std::vector<NodeEntry> NodeVector;
- typedef std::vector<NodeId> FreeNodeVector;
+ using NodeVector = std::vector<NodeEntry>;
+ using FreeNodeVector = std::vector<NodeId>;
NodeVector Nodes;
FreeNodeVector FreeNodeIds;
- typedef std::vector<EdgeEntry> EdgeVector;
- typedef std::vector<EdgeId> FreeEdgeVector;
+ using EdgeVector = std::vector<EdgeEntry>;
+ using FreeEdgeVector = std::vector<EdgeId>;
EdgeVector Edges;
FreeEdgeVector FreeEdgeIds;
+ Graph(const Graph &Other) {}
+
// ----- INTERNAL METHODS -----
NodeEntry &getNode(NodeId NId) {
@@ -220,20 +223,18 @@ namespace PBQP {
return EId;
}
- Graph(const Graph &Other) {}
void operator=(const Graph &Other) {}
public:
-
- typedef typename NodeEntry::AdjEdgeItr AdjEdgeItr;
+ using AdjEdgeItr = typename NodeEntry::AdjEdgeItr;
class NodeItr {
public:
- typedef std::forward_iterator_tag iterator_category;
- typedef NodeId value_type;
- typedef int difference_type;
- typedef NodeId* pointer;
- typedef NodeId& reference;
+ using iterator_category = std::forward_iterator_tag;
+ using value_type = NodeId;
+ using difference_type = int;
+ using pointer = NodeId *;
+ using reference = NodeId &;
NodeItr(NodeId CurNId, const Graph &G)
: CurNId(CurNId), EndNId(G.Nodes.size()), FreeNodeIds(G.FreeNodeIds) {
@@ -283,53 +284,65 @@ namespace PBQP {
class NodeIdSet {
public:
- NodeIdSet(const Graph &G) : G(G) { }
+ NodeIdSet(const Graph &G) : G(G) {}
+
NodeItr begin() const { return NodeItr(0, G); }
NodeItr end() const { return NodeItr(G.Nodes.size(), G); }
+
bool empty() const { return G.Nodes.empty(); }
+
typename NodeVector::size_type size() const {
return G.Nodes.size() - G.FreeNodeIds.size();
}
+
private:
const Graph& G;
};
class EdgeIdSet {
public:
- EdgeIdSet(const Graph &G) : G(G) { }
+ EdgeIdSet(const Graph &G) : G(G) {}
+
EdgeItr begin() const { return EdgeItr(0, G); }
EdgeItr end() const { return EdgeItr(G.Edges.size(), G); }
+
bool empty() const { return G.Edges.empty(); }
+
typename NodeVector::size_type size() const {
return G.Edges.size() - G.FreeEdgeIds.size();
}
+
private:
const Graph& G;
};
class AdjEdgeIdSet {
public:
- AdjEdgeIdSet(const NodeEntry &NE) : NE(NE) { }
+ AdjEdgeIdSet(const NodeEntry &NE) : NE(NE) {}
+
typename NodeEntry::AdjEdgeItr begin() const {
return NE.getAdjEdgeIds().begin();
}
+
typename NodeEntry::AdjEdgeItr end() const {
return NE.getAdjEdgeIds().end();
}
+
bool empty() const { return NE.getAdjEdgeIds().empty(); }
+
typename NodeEntry::AdjEdgeList::size_type size() const {
return NE.getAdjEdgeIds().size();
}
+
private:
const NodeEntry &NE;
};
/// @brief Construct an empty PBQP graph.
- Graph() : Solver(nullptr) {}
+ Graph() = default;
/// @brief Construct an empty PBQP graph with the given graph metadata.
- Graph(GraphMetadata Metadata)
- : Metadata(std::move(Metadata)), Solver(nullptr) {}
+ Graph(GraphMetadata Metadata) : Metadata(std::move(Metadata)) {}
/// @brief Get a reference to the graph metadata.
GraphMetadata& getMetadata() { return Metadata; }
@@ -656,7 +669,7 @@ namespace PBQP {
}
};
-} // namespace PBQP
-} // namespace llvm
+} // end namespace PBQP
+} // end namespace llvm
#endif // LLVM_CODEGEN_PBQP_GRAPH_HPP
diff --git a/llvm/include/llvm/CodeGen/PBQP/Math.h b/llvm/include/llvm/CodeGen/PBQP/Math.h
index 278787550a4..ba405e816d1 100644
--- a/llvm/include/llvm/CodeGen/PBQP/Math.h
+++ b/llvm/include/llvm/CodeGen/PBQP/Math.h
@@ -1,4 +1,4 @@
-//===------ Math.h - PBQP Vector and Matrix classes -------------*- C++ -*-===//
+//===- Math.h - PBQP Vector and Matrix classes ------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -11,20 +11,22 @@
#define LLVM_CODEGEN_PBQP_MATH_H
#include "llvm/ADT/Hashing.h"
+#include "llvm/ADT/STLExtras.h"
#include <algorithm>
#include <cassert>
#include <functional>
+#include <memory>
namespace llvm {
namespace PBQP {
-typedef float PBQPNum;
+using PBQPNum = float;
/// \brief PBQP Vector class.
class Vector {
friend hash_code hash_value(const Vector &);
-public:
+public:
/// \brief Construct a PBQP vector of the given size.
explicit Vector(unsigned Length)
: Length(Length), Data(llvm::make_unique<PBQPNum []>(Length)) {}
@@ -120,8 +122,8 @@ OStream& operator<<(OStream &OS, const Vector &V) {
class Matrix {
private:
friend hash_code hash_value(const Matrix &);
-public:
+public:
/// \brief Construct a PBQP Matrix with the given dimensions.
Matrix(unsigned Rows, unsigned Cols) :
Rows(Rows), Cols(Cols), Data(llvm::make_unique<PBQPNum []>(Rows * Cols)) {
@@ -253,9 +255,11 @@ OStream& operator<<(OStream &OS, const Matrix &M) {
template <typename Metadata>
class MDVector : public Vector {
public:
- MDVector(const Vector &v) : Vector(v), md(*this) { }
+ MDVector(const Vector &v) : Vector(v), md(*this) {}
MDVector(Vector &&v) : Vector(std::move(v)), md(*this) { }
+
const Metadata& getMetadata() const { return md; }
+
private:
Metadata md;
};
@@ -268,9 +272,11 @@ inline hash_code hash_value(const MDVector<Metadata> &V) {
template <typename Metadata>
class MDMatrix : public Matrix {
public:
- MDMatrix(const Matrix &m) : Matrix(m), md(*this) { }
+ MDMatrix(const Matrix &m) : Matrix(m), md(*this) {}
MDMatrix(Matrix &&m) : Matrix(std::move(m)), md(*this) { }
+
const Metadata& getMetadata() const { return md; }
+
private:
Metadata md;
};
@@ -280,7 +286,7 @@ inline hash_code hash_value(const MDMatrix<Metadata> &M) {
return hash_value(static_cast<const Matrix&>(M));
}
-} // namespace PBQP
-} // namespace llvm
+} // end namespace PBQP
+} // end namespace llvm
#endif // LLVM_CODEGEN_PBQP_MATH_H
diff --git a/llvm/include/llvm/CodeGen/PBQP/ReductionRules.h b/llvm/include/llvm/CodeGen/PBQP/ReductionRules.h
index d4a544bfe72..8aeb5193676 100644
--- a/llvm/include/llvm/CodeGen/PBQP/ReductionRules.h
+++ b/llvm/include/llvm/CodeGen/PBQP/ReductionRules.h
@@ -1,4 +1,4 @@
-//===----------- ReductionRules.h - Reduction Rules -------------*- C++ -*-===//
+//===- ReductionRules.h - Reduction Rules -----------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -17,6 +17,8 @@
#include "Graph.h"
#include "Math.h"
#include "Solution.h"
+#include <cassert>
+#include <limits>
namespace llvm {
namespace PBQP {
@@ -27,11 +29,11 @@ namespace PBQP {
/// neighbor. Notify the problem domain.
template <typename GraphT>
void applyR1(GraphT &G, typename GraphT::NodeId NId) {
- typedef typename GraphT::NodeId NodeId;
- typedef typename GraphT::EdgeId EdgeId;
- typedef typename GraphT::Vector Vector;
- typedef typename GraphT::Matrix Matrix;
- typedef typename GraphT::RawVector RawVector;
+ using NodeId = typename GraphT::NodeId;
+ using EdgeId = typename GraphT::EdgeId;
+ using Vector = typename GraphT::Vector;
+ using Matrix = typename GraphT::Matrix;
+ using RawVector = typename GraphT::RawVector;
assert(G.getNodeDegree(NId) == 1 &&
"R1 applied to node with degree != 1.");
@@ -71,11 +73,11 @@ namespace PBQP {
template <typename GraphT>
void applyR2(GraphT &G, typename GraphT::NodeId NId) {
- typedef typename GraphT::NodeId NodeId;
- typedef typename GraphT::EdgeId EdgeId;
- typedef typename GraphT::Vector Vector;
- typedef typename GraphT::Matrix Matrix;
- typedef typename GraphT::RawMatrix RawMatrix;
+ using NodeId = typename GraphT::NodeId;
+ using EdgeId = typename GraphT::EdgeId;
+ using Vector = typename GraphT::Vector;
+ using Matrix = typename GraphT::Matrix;
+ using RawMatrix = typename GraphT::RawMatrix;
assert(G.getNodeDegree(NId) == 2 &&
"R2 applied to node with degree != 2.");
@@ -177,9 +179,9 @@ namespace PBQP {
// state.
template <typename GraphT, typename StackT>
Solution backpropagate(GraphT& G, StackT stack) {
- typedef GraphBase::NodeId NodeId;
- typedef typename GraphT::Matrix Matrix;
- typedef typename GraphT::RawVector RawVector;
+ using NodeId = GraphBase::NodeId;
+ using Matrix = typename GraphT::Matrix;
+ using RawVector = typename GraphT::RawVector;
Solution s;
@@ -215,7 +217,7 @@ namespace PBQP {
return s;
}
-} // namespace PBQP
-} // namespace llvm
+} // end namespace PBQP
+} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_PBQP_REDUCTIONRULES_H
diff --git a/llvm/include/llvm/CodeGen/PBQP/Solution.h b/llvm/include/llvm/CodeGen/PBQP/Solution.h
index d96b5eac452..8d5d2374679 100644
--- a/llvm/include/llvm/CodeGen/PBQP/Solution.h
+++ b/llvm/include/llvm/CodeGen/PBQP/Solution.h
@@ -26,7 +26,7 @@ namespace PBQP {
/// To get the selection for each node in the problem use the getSelection method.
class Solution {
private:
- typedef std::map<GraphBase::NodeId, unsigned> SelectionsMap;
+ using SelectionsMap = std::map<GraphBase::NodeId, unsigned>;
SelectionsMap selections;
unsigned r0Reductions = 0;
diff --git a/llvm/include/llvm/CodeGen/PBQPRAConstraint.h b/llvm/include/llvm/CodeGen/PBQPRAConstraint.h
index 833b9bad613..269b7a7b3a3 100644
--- a/llvm/include/llvm/CodeGen/PBQPRAConstraint.h
+++ b/llvm/include/llvm/CodeGen/PBQPRAConstraint.h
@@ -1,4 +1,4 @@
-//===-- RegAllocPBQP.h ------------------------------------------*- C++ -*-===//
+//===- RegAllocPBQP.h -------------------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -16,23 +16,22 @@
#ifndef LLVM_CODEGEN_PBQPRACONSTRAINT_H
#define LLVM_CODEGEN_PBQPRACONSTRAINT_H
+#include <algorithm>
#include <memory>
#include <vector>
namespace llvm {
+
namespace PBQP {
namespace RegAlloc {
+
// Forward declare PBQP graph class.
class PBQPRAGraph;
-}
-}
-class LiveIntervals;
-class MachineBlockFrequencyInfo;
-class MachineFunction;
-class TargetRegisterInfo;
+} // end namespace RegAlloc
+} // end namespace PBQP
-typedef PBQP::RegAlloc::PBQPRAGraph PBQPRAGraph;
+using PBQPRAGraph = PBQP::RegAlloc::PBQPRAGraph;
/// @brief Abstract base for classes implementing PBQP register allocation
/// constraints (e.g. Spill-costs, interference, coalescing).
@@ -40,6 +39,7 @@ class PBQPRAConstraint {
public:
virtual ~PBQPRAConstraint() = 0;
virtual void apply(PBQPRAGraph &G) = 0;
+
private:
virtual void anchor();
};
@@ -59,11 +59,13 @@ public:
if (C)
Constraints.push_back(std::move(C));
}
+
private:
std::vector<std::unique_ptr<PBQPRAConstraint>> Constraints;
+
void anchor() override;
};
-}
+} // end namespace llvm
-#endif /* LLVM_CODEGEN_PBQPRACONSTRAINT_H */
+#endif // LLVM_CODEGEN_PBQPRACONSTRAINT_H
diff --git a/llvm/include/llvm/CodeGen/RegAllocPBQP.h b/llvm/include/llvm/CodeGen/RegAllocPBQP.h
index 8872a5dc54a..5b342863eb5 100644
--- a/llvm/include/llvm/CodeGen/RegAllocPBQP.h
+++ b/llvm/include/llvm/CodeGen/RegAllocPBQP.h
@@ -130,10 +130,10 @@ inline hash_code hash_value(const AllowedRegVector &OptRegs) {
/// \brief Holds graph-level metadata relevant to PBQP RA problems.
class GraphMetadata {
private:
- typedef ValuePool<AllowedRegVector> AllowedRegVecPool;
+ using AllowedRegVecPool = ValuePool<AllowedRegVector>;
public:
- typedef AllowedRegVecPool::PoolRef AllowedRegVecRef;
+ using AllowedRegVecRef = AllowedRegVecPool::PoolRef;
GraphMetadata(MachineFunction &MF,
LiveIntervals &LIS,
@@ -167,17 +167,17 @@ private:
/// \brief Holds solver state and other metadata relevant to each PBQP RA node.
class NodeMetadata {
public:
- typedef RegAlloc::AllowedRegVector AllowedRegVector;
+ using AllowedRegVector = RegAlloc::AllowedRegVector;
// The node's reduction state. The order in this enum is important,
// as it is assumed nodes can only progress up (i.e. towards being
// optimally reducible) when reducing the graph.
- typedef enum {
+ using ReductionState = enum {
Unprocessed,
NotProvablyAllocatable,
ConservativelyAllocatable,
OptimallyReducible
- } ReductionState;
+ };
NodeMetadata() = default;
@@ -267,23 +267,23 @@ private:
class RegAllocSolverImpl {
private:
- typedef MDMatrix<MatrixMetadata> RAMatrix;
+ using RAMatrix = MDMatrix<MatrixMetadata>;
public:
- typedef PBQP::Vector RawVector;
- typedef PBQP::Matrix RawMatrix;
- typedef PBQP::Vector Vector;
- typedef RAMatrix Matrix;
- typedef PBQP::PoolCostAllocator<Vector, Matrix> CostAllocator;
+ using RawVector = PBQP::Vector;
+ using RawMatrix = PBQP::Matrix;
+ using Vector = PBQP::Vector;
+ using Matrix = RAMatrix;
+ using CostAllocator = PBQP::PoolCostAllocator<Vector, Matrix>;
- typedef GraphBase::NodeId NodeId;
- typedef GraphBase::EdgeId EdgeId;
+ using NodeId = GraphBase::NodeId;
+ using EdgeId = GraphBase::EdgeId;
- typedef RegAlloc::NodeMetadata NodeMetadata;
- struct EdgeMetadata { };
- typedef RegAlloc::GraphMetadata GraphMetadata;
+ using NodeMetadata = RegAlloc::NodeMetadata;
+ struct EdgeMetadata {};
+ using GraphMetadata = RegAlloc::GraphMetadata;
- typedef PBQP::Graph<RegAllocSolverImpl> Graph;
+ using Graph = PBQP::Graph<RegAllocSolverImpl>;
RegAllocSolverImpl(Graph &G) : G(G) {}
@@ -426,7 +426,7 @@ private:
std::vector<GraphBase::NodeId> reduce() {
assert(!G.empty() && "Cannot reduce empty graph.");
- typedef GraphBase::NodeId NodeId;
+ using NodeId = GraphBase::NodeId;
std::vector<NodeId> NodeStack;
// Consume worklists.
@@ -459,7 +459,6 @@ private:
ConservativelyAllocatableNodes.erase(NItr);
NodeStack.push_back(NId);
G.disconnectAllNeighborsFromNode(NId);
-
} else if (!NotProvablyAllocatableNodes.empty()) {
NodeSet::iterator NItr =
std::min_element(NotProvablyAllocatableNodes.begin(),
@@ -493,7 +492,7 @@ private:
};
Graph& G;
- typedef std::set<NodeId> NodeSet;
+ using NodeSet = std::set<NodeId>;
NodeSet OptimallyReducibleNodes;
NodeSet ConservativelyAllocatableNodes;
NodeSet NotProvablyAllocatableNodes;
@@ -501,7 +500,7 @@ private:
class PBQPRAGraph : public PBQP::Graph<RegAllocSolverImpl> {
private:
- typedef PBQP::Graph<RegAllocSolverImpl> BaseT;
+ using BaseT = PBQP::Graph<RegAllocSolverImpl>;
public:
PBQPRAGraph(GraphMetadata Metadata) : BaseT(std::move(Metadata)) {}
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
index f5f5bfd45e7..d62bb9bf0b7 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
@@ -1,4 +1,4 @@
-//==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
+//===- ScheduleDAGInstrs.h - MachineInstr Scheduling ------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -15,22 +15,38 @@
#ifndef LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
#define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
-#include "llvm/ADT/MapVector.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/PointerIntPair.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SparseMultiSet.h"
#include "llvm/ADT/SparseSet.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/LivePhysRegs.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/TargetSchedule.h"
-#include "llvm/Support/Compiler.h"
+#include "llvm/MC/LaneBitmask.h"
#include "llvm/Target/TargetRegisterInfo.h"
+#include <cassert>
+#include <cstdint>
#include <list>
+#include <utility>
+#include <vector>
namespace llvm {
+
+ class LiveIntervals;
class MachineFrameInfo;
+ class MachineFunction;
+ class MachineInstr;
class MachineLoopInfo;
- class MachineDominatorTree;
- class RegPressureTracker;
+ class MachineOperand;
+ struct MCSchedClassDesc;
class PressureDiffs;
+ class PseudoSourceValue;
+ class RegPressureTracker;
+ class UndefValue;
+ class Value;
/// An individual mapping from virtual register number to SUnit.
struct VReg2SUnit {
@@ -70,31 +86,34 @@ namespace llvm {
/// Use a SparseMultiSet to track physical registers. Storage is only
/// allocated once for the pass. It can be cleared in constant time and reused
/// without any frees.
- typedef SparseMultiSet<PhysRegSUOper, llvm::identity<unsigned>, uint16_t>
- Reg2SUnitsMap;
+ using Reg2SUnitsMap =
+ SparseMultiSet<PhysRegSUOper, identity<unsigned>, uint16_t>;
/// Use SparseSet as a SparseMap by relying on the fact that it never
/// compares ValueT's, only unsigned keys. This allows the set to be cleared
/// between scheduling regions in constant time as long as ValueT does not
/// require a destructor.
- typedef SparseSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMap;
+ using VReg2SUnitMap = SparseSet<VReg2SUnit, VirtReg2IndexFunctor>;
/// Track local uses of virtual registers. These uses are gathered by the DAG
/// builder and may be consulted by the scheduler to avoid iterating an entire
/// vreg use list.
- typedef SparseMultiSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMultiMap;
+ using VReg2SUnitMultiMap = SparseMultiSet<VReg2SUnit, VirtReg2IndexFunctor>;
+
+ using VReg2SUnitOperIdxMultiMap =
+ SparseMultiSet<VReg2SUnitOperIdx, VirtReg2IndexFunctor>;
- typedef SparseMultiSet<VReg2SUnitOperIdx, VirtReg2IndexFunctor>
- VReg2SUnitOperIdxMultiMap;
+ using ValueType = PointerUnion<const Value *, const PseudoSourceValue *>;
- typedef PointerUnion<const Value *, const PseudoSourceValue *> ValueType;
struct UnderlyingObject : PointerIntPair<ValueType, 1, bool> {
UnderlyingObject(ValueType V, bool MayAlias)
: PointerIntPair<ValueType, 1, bool>(V, MayAlias) {}
+
ValueType getValue() const { return getPointer(); }
bool mayAlias() const { return getInt(); }
};
- typedef SmallVector<UnderlyingObject, 4> UnderlyingObjectsVector;
+
+ using UnderlyingObjectsVector = SmallVector<UnderlyingObject, 4>;
/// A ScheduleDAG for scheduling lists of MachineInstr.
class ScheduleDAGInstrs : public ScheduleDAG {
@@ -114,10 +133,10 @@ namespace llvm {
/// reordering. A specialized scheduler can override
/// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate
/// it has taken responsibility for scheduling the terminator correctly.
- bool CanHandleTerminators;
+ bool CanHandleTerminators = false;
/// Whether lane masks should get tracked.
- bool TrackLaneMasks;
+ bool TrackLaneMasks = false;
// State specific to the current scheduling region.
// ------------------------------------------------
@@ -155,12 +174,12 @@ namespace llvm {
/// Tracks the last instructions in this region using each virtual register.
VReg2SUnitOperIdxMultiMap CurrentVRegUses;
- AliasAnalysis *AAForDep;
+ AliasAnalysis *AAForDep = nullptr;
/// Remember a generic side-effecting instruction as we proceed.
/// No other SU ever gets scheduled around it (except in the special
/// case of a huge region that gets reduced).
- SUnit *BarrierChain;
+ SUnit *BarrierChain = nullptr;
public:
/// A list of SUnits, used in Value2SUsMap, during DAG construction.
@@ -168,7 +187,7 @@ namespace llvm {
/// implementation of this data structure, such as a singly linked list
/// with a memory pool (SmallVector was tried but slow and SparseSet is not
/// applicable).
- typedef std::list<SUnit *> SUList;
+ using SUList = std::list<SUnit *>;
protected:
/// \brief A map from ValueType to SUList, used during DAG construction, as
@@ -216,13 +235,13 @@ namespace llvm {
/// For an unanalyzable memory access, this Value is used in maps.
UndefValue *UnknownValue;
- typedef std::vector<std::pair<MachineInstr *, MachineInstr *>>
- DbgValueVector;
+ using DbgValueVector =
+ std::vector<std::pair<MachineInstr *, MachineInstr *>>;
/// Remember instruction that precedes DBG_VALUE.
/// These are generated by buildSchedGraph but persist so they can be
/// referenced when emitting the final schedule.
DbgValueVector DbgValues;
- MachineInstr *FirstDbgValue;
+ MachineInstr *FirstDbgValue = nullptr;
/// Set of live physical registers for updating kill flags.
LivePhysRegs LiveRegs;
@@ -232,7 +251,7 @@ namespace llvm {
const MachineLoopInfo *mli,
bool RemoveKillFlags = false);
- ~ScheduleDAGInstrs() override {}
+ ~ScheduleDAGInstrs() override = default;
/// Gets the machine model for instruction scheduling.
const TargetSchedModel *getSchedModel() const { return &SchedModel; }
@@ -354,6 +373,7 @@ namespace llvm {
return nullptr;
return I->second;
}
+
} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
diff --git a/llvm/lib/CodeGen/MachineRegionInfo.cpp b/llvm/lib/CodeGen/MachineRegionInfo.cpp
index 71ad4e6aa7f..2402ffdbbcb 100644
--- a/llvm/lib/CodeGen/MachineRegionInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegionInfo.cpp
@@ -1,7 +1,19 @@
-#include "llvm/CodeGen/MachineRegionInfo.h"
+//===- lib/Codegen/MachineRegionInfo.cpp ----------------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/RegionInfoImpl.h"
#include "llvm/CodeGen/MachinePostDominators.h"
+#include "llvm/CodeGen/MachineRegionInfo.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/Support/Debug.h"
#define DEBUG_TYPE "machine-region-info"
@@ -11,36 +23,29 @@ STATISTIC(numMachineRegions, "The # of machine regions");
STATISTIC(numMachineSimpleRegions, "The # of simple machine regions");
namespace llvm {
+
template class RegionBase<RegionTraits<MachineFunction>>;
template class RegionNodeBase<RegionTraits<MachineFunction>>;
template class RegionInfoBase<RegionTraits<MachineFunction>>;
-}
+
+} // end namespace llvm
//===----------------------------------------------------------------------===//
// MachineRegion implementation
-//
MachineRegion::MachineRegion(MachineBasicBlock *Entry, MachineBasicBlock *Exit,
MachineRegionInfo* RI,
MachineDominatorTree *DT, MachineRegion *Parent) :
- RegionBase<RegionTraits<MachineFunction>>(Entry, Exit, RI, DT, Parent) {
+ RegionBase<RegionTraits<MachineFunction>>(Entry, Exit, RI, DT, Parent) {}
-}
-
-MachineRegion::~MachineRegion() { }
+MachineRegion::~MachineRegion() = default;
//===----------------------------------------------------------------------===//
// MachineRegionInfo implementation
-//
-
-MachineRegionInfo::MachineRegionInfo() :
- RegionInfoBase<RegionTraits<MachineFunction>>() {
-
-}
-MachineRegionInfo::~MachineRegionInfo() {
+MachineRegionInfo::MachineRegionInfo() = default;
-}
+MachineRegionInfo::~MachineRegionInfo() = default;
void MachineRegionInfo::updateStatistics(MachineRegion *R) {
++numMachineRegions;
@@ -73,9 +78,7 @@ MachineRegionInfoPass::MachineRegionInfoPass() : MachineFunctionPass(ID) {
initializeMachineRegionInfoPassPass(*PassRegistry::getPassRegistry());
}
-MachineRegionInfoPass::~MachineRegionInfoPass() {
-
-}
+MachineRegionInfoPass::~MachineRegionInfoPass() = default;
bool MachineRegionInfoPass::runOnMachineFunction(MachineFunction &F) {
releaseMemory();
@@ -137,8 +140,9 @@ INITIALIZE_PASS_END(MachineRegionInfoPass, DEBUG_TYPE,
// the link time optimization.
namespace llvm {
- FunctionPass *createMachineRegionInfoPass() {
- return new MachineRegionInfoPass();
- }
+
+FunctionPass *createMachineRegionInfoPass() {
+ return new MachineRegionInfoPass();
}
+} // end namespace llvm
diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp
index 3b5964eef55..b2dfef91add 100644
--- a/llvm/lib/CodeGen/RegAllocPBQP.cpp
+++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp
@@ -49,9 +49,11 @@
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PBQP/Graph.h"
+#include "llvm/CodeGen/PBQP/Math.h"
#include "llvm/CodeGen/PBQP/Solution.h"
#include "llvm/CodeGen/PBQPRAConstraint.h"
#include "llvm/CodeGen/RegAllocPBQP.h"
@@ -139,13 +141,13 @@ public:
}
private:
- typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
- typedef std::vector<const LiveInterval*> Node2LIMap;
- typedef std::vector<unsigned> AllowedSet;
- typedef std::vector<AllowedSet> AllowedSetMap;
- typedef std::pair<unsigned, unsigned> RegPair;
- typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
- typedef std::set<unsigned> RegSet;
+ using LI2NodeMap = std::map<const LiveInterval *, unsigned>;
+ using Node2LIMap = std::vector<const LiveInterval *>;
+ using AllowedSet = std::vector<unsigned>;
+ using AllowedSetMap = std::vector<AllowedSet>;
+ using RegPair = std::pair<unsigned, unsigned>;
+ using CoalesceMap = std::map<RegPair, PBQP::PBQPNum>;
+ using RegSet = std::set<unsigned>;
char *customPassID;
@@ -212,12 +214,12 @@ public:
/// @brief Add interference edges between overlapping vregs.
class Interference : public PBQPRAConstraint {
private:
- typedef const PBQP::RegAlloc::AllowedRegVector* AllowedRegVecPtr;
- typedef std::pair<AllowedRegVecPtr, AllowedRegVecPtr> IKey;
- typedef DenseMap<IKey, PBQPRAGraph::MatrixPtr> IMatrixCache;
- typedef DenseSet<IKey> DisjointAllowedRegsCache;
- typedef std::pair<PBQP::GraphBase::NodeId, PBQP::GraphBase::NodeId> IEdgeKey;
- typedef DenseSet<IEdgeKey> IEdgeCache;
+ using AllowedRegVecPtr = const PBQP::RegAlloc::AllowedRegVector *;
+ using IKey = std::pair<AllowedRegVecPtr, AllowedRegVecPtr>;
+ using IMatrixCache = DenseMap<IKey, PBQPRAGraph::MatrixPtr>;
+ using DisjointAllowedRegsCache = DenseSet<IKey>;
+ using IEdgeKey = std::pair<PBQP::GraphBase::NodeId, PBQP::GraphBase::NodeId>;
+ using IEdgeCache = DenseSet<IEdgeKey>;
bool haveDisjointAllowedRegs(const PBQPRAGraph &G, PBQPRAGraph::NodeId NId,
PBQPRAGraph::NodeId MId,
@@ -252,8 +254,8 @@ private:
// for the fast interference graph construction algorithm. The last is there
// to save us from looking up node ids via the VRegToNode map in the graph
// metadata.
- typedef std::tuple<LiveInterval*, size_t, PBQP::GraphBase::NodeId>
- IntervalInfo;
+ using IntervalInfo =
+ std::tuple<LiveInterval*, size_t, PBQP::GraphBase::NodeId>;
static SlotIndex getStartPoint(const IntervalInfo &I) {
return std::get<0>(I)->segments[std::get<1>(I)].start;
@@ -320,9 +322,10 @@ public:
// Cache known disjoint allowed registers pairs
DisjointAllowedRegsCache D;
- typedef std::set<IntervalInfo, decltype(&lowestEndPoint)> IntervalSet;
- typedef std::priority_queue<IntervalInfo, std::vector<IntervalInfo>,
- decltype(&lowestStartPoint)> IntervalQueue;
+ using IntervalSet = std::set<IntervalInfo, decltype(&lowestEndPoint)>;
+ using IntervalQueue =
+ std::priority_queue<IntervalInfo, std::vector<IntervalInfo>,
+ decltype(&lowestStartPoint)>;
IntervalSet Active(lowestEndPoint);
IntervalQueue Inactive(lowestStartPoint);
@@ -658,7 +661,6 @@ void RegAllocPBQP::spillVReg(unsigned VReg,
SmallVectorImpl<unsigned> &NewIntervals,
MachineFunction &MF, LiveIntervals &LIS,
VirtRegMap &VRM, Spiller &VRegSpiller) {
-
VRegsToAlloc.erase(VReg);
LiveRangeEdit LRE(&LIS.getInterval(VReg), NewIntervals, MF, LIS, &VRM,
nullptr, &DeadRemats);
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index 8035ea80364..3fdbd245936 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -12,32 +12,54 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/ADT/IntEqClasses.h"
+#include "llvm/ADT/iterator_range.h"
+#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/SmallPtrSet.h"
-#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/SparseSet.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/LivePhysRegs.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBundle.h"
#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/RegisterPressure.h"
+#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/CodeGen/ScheduleDFS.h"
+#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/IR/Constants.h"
#include "llvm/IR/Function.h"
-#include "llvm/IR/Type.h"
+#include "llvm/IR/Instruction.h"
+#include "llvm/IR/Instructions.h"
#include "llvm/IR/Operator.h"
+#include "llvm/IR/Type.h"
+#include "llvm/IR/Value.h"
+#include "llvm/MC/LaneBitmask.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
+#include <algorithm>
+#include <cassert>
+#include <iterator>
+#include <string>
+#include <utility>
+#include <vector>
using namespace llvm;
@@ -90,11 +112,9 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
const MachineLoopInfo *mli,
bool RemoveKillFlags)
: ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()),
- RemoveKillFlags(RemoveKillFlags), CanHandleTerminators(false),
- TrackLaneMasks(false), AAForDep(nullptr), BarrierChain(nullptr),
+ RemoveKillFlags(RemoveKillFlags),
UnknownValue(UndefValue::get(
- Type::getVoidTy(mf.getFunction()->getContext()))),
- FirstDbgValue(nullptr) {
+ Type::getVoidTy(mf.getFunction()->getContext()))) {
DbgValues.clear();
const TargetSubtargetInfo &ST = mf.getSubtarget();
@@ -126,7 +146,7 @@ static const Value *getUnderlyingObjectFromInt(const Value *V) {
return V;
}
assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
- } while (1);
+ } while (true);
}
/// This is a wrapper around GetUnderlyingObjects and adds support for basic
@@ -563,7 +583,7 @@ void ScheduleDAGInstrs::initSUnits() {
// which is contained within a basic block.
SUnits.reserve(NumRegionInstrs);
- for (MachineInstr &MI : llvm::make_range(RegionBegin, RegionEnd)) {
+ for (MachineInstr &MI : make_range(RegionBegin, RegionEnd)) {
if (MI.isDebugValue())
continue;
@@ -606,13 +626,13 @@ void ScheduleDAGInstrs::initSUnits() {
class ScheduleDAGInstrs::Value2SUsMap : public MapVector<ValueType, SUList> {
/// Current total number of SUs in map.
- unsigned NumNodes;
+ unsigned NumNodes = 0;
/// 1 for loads, 0 for stores. (see comment in SUList)
unsigned TrueMemOrderLatency;
public:
- Value2SUsMap(unsigned lat = 0) : NumNodes(0), TrueMemOrderLatency(lat) {}
+ Value2SUsMap(unsigned lat = 0) : TrueMemOrderLatency(lat) {}
/// To keep NumNodes up to date, insert() is used instead of
/// this operator w/ push_back().
@@ -630,7 +650,7 @@ public:
void inline clearList(ValueType V) {
iterator Itr = find(V);
if (Itr != end()) {
- assert (NumNodes >= Itr->second.size());
+ assert(NumNodes >= Itr->second.size());
NumNodes -= Itr->second.size();
Itr->second.clear();
@@ -646,7 +666,7 @@ public:
unsigned inline size() const { return NumNodes; }
/// Counts the number of SUs in this map after a reduction.
- void reComputeSize(void) {
+ void reComputeSize() {
NumNodes = 0;
for (auto &I : *this)
NumNodes += I.second.size();
@@ -676,7 +696,7 @@ void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
}
void ScheduleDAGInstrs::addBarrierChain(Value2SUsMap &map) {
- assert (BarrierChain != nullptr);
+ assert(BarrierChain != nullptr);
for (auto &I : map) {
SUList &sus = I.second;
@@ -687,7 +707,7 @@ void ScheduleDAGInstrs::addBarrierChain(Value2SUsMap &map) {
}
void ScheduleDAGInstrs::insertBarrierChain(Value2SUsMap &map) {
- assert (BarrierChain != nullptr);
+ assert(BarrierChain != nullptr);
// Go through all lists of SUs.
for (Value2SUsMap::iterator I = map.begin(), EE = map.end(); I != EE;) {
@@ -1028,7 +1048,7 @@ void ScheduleDAGInstrs::reduceHugeMemNodeMaps(Value2SUsMap &stores,
// The N last elements in NodeNums will be removed, and the SU with
// the lowest NodeNum of them will become the new BarrierChain to
// let the not yet seen SUs have a dependency to the removed SUs.
- assert (N <= NodeNums.size());
+ assert(N <= NodeNums.size());
SUnit *newBarrierChain = &SUnits[*(NodeNums.end() - N)];
if (BarrierChain) {
// The aliasing and non-aliasing maps reduce independently of each
@@ -1156,6 +1176,7 @@ std::string ScheduleDAGInstrs::getDAGName() const {
//===----------------------------------------------------------------------===//
namespace llvm {
+
/// Internal state used to compute SchedDFSResult.
class SchedDFSImpl {
SchedDFSResult &R;
@@ -1163,16 +1184,16 @@ class SchedDFSImpl {
/// Join DAG nodes into equivalence classes by their subtree.
IntEqClasses SubtreeClasses;
/// List PredSU, SuccSU pairs that represent data edges between subtrees.
- std::vector<std::pair<const SUnit*, const SUnit*> > ConnectionPairs;
+ std::vector<std::pair<const SUnit *, const SUnit*>> ConnectionPairs;
struct RootData {
unsigned NodeID;
unsigned ParentNodeID; ///< Parent node (member of the parent subtree).
- unsigned SubInstrCount; ///< Instr count in this tree only, not children.
+ unsigned SubInstrCount = 0; ///< Instr count in this tree only, not
+ /// children.
RootData(unsigned id): NodeID(id),
- ParentNodeID(SchedDFSResult::InvalidSubtreeID),
- SubInstrCount(0) {}
+ ParentNodeID(SchedDFSResult::InvalidSubtreeID) {}
unsigned getSparseSetIndex() const { return NodeID; }
};
@@ -1340,12 +1361,15 @@ protected:
} while (FromTree != SchedDFSResult::InvalidSubtreeID);
}
};
+
} // end namespace llvm
namespace {
+
/// Manage the stack used by a reverse depth-first search over the DAG.
class SchedDAGReverseDFS {
- std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack;
+ std::vector<std::pair<const SUnit *, SUnit::const_pred_iterator>> DFSStack;
+
public:
bool isComplete() const { return DFSStack.empty(); }
@@ -1367,7 +1391,8 @@ public:
return getCurr()->Preds.end();
}
};
-} // anonymous
+
+} // end anonymous namespace
static bool hasDataSucc(const SUnit *SU) {
for (const SDep &SuccDep : SU->Succs) {
@@ -1392,7 +1417,7 @@ void SchedDFSResult::compute(ArrayRef<SUnit> SUnits) {
SchedDAGReverseDFS DFS;
Impl.visitPreorder(&SU);
DFS.follow(&SU);
- for (;;) {
+ while (true) {
// Traverse the leftmost path as far as possible.
while (DFS.getPred() != DFS.getPredEnd()) {
const SDep &PredDep = *DFS.getPred();
@@ -1457,4 +1482,5 @@ raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) {
}
} // end namespace llvm
+
#endif
diff --git a/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.h b/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.h
index 4f656f94ea1..b99c1d1d6b3 100644
--- a/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.h
+++ b/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.h
@@ -1,4 +1,4 @@
-//===-- AArch64PBQPRegAlloc.h - AArch64 specific PBQP constraints -------===//
+//==- AArch64PBQPRegAlloc.h - AArch64 specific PBQP constraints --*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
@@ -15,6 +15,8 @@
namespace llvm {
+class TargetRegisterInfo;
+
/// Add the accumulator chaining constraint to a PBQP graph
class A57ChainingConstraint : public PBQPRAConstraint {
public:
@@ -33,6 +35,7 @@ private:
// Add constraints between existing chains
void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
};
-}
+
+} // end namespace llvm
#endif // LLVM_LIB_TARGET_AARCH64_AARCH64PBQPREGALOC_H
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