diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonRegisterInfo.h | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/autohvx/reg-sequence.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/mul64-sext.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/pred-absolute-store.ll | 2 |
4 files changed, 7 insertions, 5 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h index 4ead57da8fa..7102bf1ee05 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h @@ -39,6 +39,8 @@ public: BitVector getReservedRegs(const MachineFunction &MF) const override; + bool enableMultipleCopyHints() const override { return true; } + void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS = nullptr) const override; diff --git a/llvm/test/CodeGen/Hexagon/autohvx/reg-sequence.ll b/llvm/test/CodeGen/Hexagon/autohvx/reg-sequence.ll index 9ef7e41e766..3aebed035c2 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/reg-sequence.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/reg-sequence.ll @@ -99,8 +99,8 @@ b2: } ; CHECK-LABEL: test_22: -; CHECK: v3 = v2 ; CHECK: vcombine(v3,v2) +; CHECK: v1 = v0 ; Result: v1:0 = vcombine(v2,v2) define <128 x i8> @test_22(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: @@ -145,8 +145,8 @@ b2: } ; CHECK-LABEL: test_33: -; CHECK: v2 = v3 ; CHECK: vcombine(v3,v2) +; CHECK: v0 = v1 ; Result: v1:0 = vcombine(v3,v3) define <128 x i8> @test_33(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: diff --git a/llvm/test/CodeGen/Hexagon/mul64-sext.ll b/llvm/test/CodeGen/Hexagon/mul64-sext.ll index 8bbe6649a1f..b16ae9932cc 100644 --- a/llvm/test/CodeGen/Hexagon/mul64-sext.ll +++ b/llvm/test/CodeGen/Hexagon/mul64-sext.ll @@ -75,9 +75,9 @@ b3: } ; CHECK-LABEL: mul_nac_2 -; CHECK: r0 = memw(r0+#0) -; CHECK: r5:4 -= mpy(r2,r0) ; CHECK: r1:0 = combine(r5,r4) +; CHECK: r6 = memw(r0+#0) +; CHECK: r1:0 -= mpy(r2,r6) ; CHECK: jumpr r31 define i64 @mul_nac_2(i32* %a0, i64 %a1, i64 %a2) #0 { b3: diff --git a/llvm/test/CodeGen/Hexagon/pred-absolute-store.ll b/llvm/test/CodeGen/Hexagon/pred-absolute-store.ll index 2f19e9aeb7b..1ed6bb2aacb 100644 --- a/llvm/test/CodeGen/Hexagon/pred-absolute-store.ll +++ b/llvm/test/CodeGen/Hexagon/pred-absolute-store.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s ; Check that we are able to predicate instructions with absolute ; addressing mode. -; CHECK: if ({{!?}}p{{[0-3]}}) memw(##gvar) = r{{[0-9]+}} +; CHECK: if ({{!?}}p{{[0-3]}}.new) memw(##gvar) = r{{[0-9]+}} @gvar = external global i32 define i32 @test2(i32 %a, i32 %b) nounwind { |
