diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/include/llvm/IR/IntrinsicsR600.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll | 12 |
3 files changed, 9 insertions, 7 deletions
diff --git a/llvm/include/llvm/IR/IntrinsicsR600.td b/llvm/include/llvm/IR/IntrinsicsR600.td index 098ad53268f..d99c42d5029 100644 --- a/llvm/include/llvm/IR/IntrinsicsR600.td +++ b/llvm/include/llvm/IR/IntrinsicsR600.td @@ -52,7 +52,7 @@ def int_AMDGPU_div_scale : GCCBuiltin<"__builtin_amdgpu_div_scale">, def int_AMDGPU_div_fmas : GCCBuiltin<"__builtin_amdgpu_div_fmas">, Intrinsic<[llvm_anyfloat_ty], - [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], + [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, llvm_i1_ty], [IntrNoMem]>; def int_AMDGPU_div_fixup : GCCBuiltin<"__builtin_amdgpu_div_fixup">, diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp index 6eebccdf9e2..37c444d220f 100644 --- a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp @@ -844,6 +844,8 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, } case Intrinsic::AMDGPU_div_fmas: + // FIXME: Dropping bool parameter. Work is needed to support the implicit + // read from VCC. return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT, Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll b/llvm/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll index 8d76f1e662b..43bfc7cd3f0 100644 --- a/llvm/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll +++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s -declare float @llvm.AMDGPU.div.fmas.f32(float, float, float) nounwind readnone -declare double @llvm.AMDGPU.div.fmas.f64(double, double, double) nounwind readnone +declare float @llvm.AMDGPU.div.fmas.f32(float, float, float, i1) nounwind readnone +declare double @llvm.AMDGPU.div.fmas.f64(double, double, double, i1) nounwind readnone ; SI-LABEL: {{^}}test_div_fmas_f32: ; SI-DAG: S_LOAD_DWORD [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb @@ -12,16 +12,16 @@ declare double @llvm.AMDGPU.div.fmas.f64(double, double, double) nounwind readno ; SI: V_DIV_FMAS_F32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]] ; SI: BUFFER_STORE_DWORD [[RESULT]], ; SI: S_ENDPGM -define void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { - %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c) nounwind readnone +define void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind { + %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone store float %result, float addrspace(1)* %out, align 4 ret void } ; SI-LABEL: {{^}}test_div_fmas_f64: ; SI: V_DIV_FMAS_F64 -define void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c) nounwind { - %result = call double @llvm.AMDGPU.div.fmas.f64(double %a, double %b, double %c) nounwind readnone +define void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind { + %result = call double @llvm.AMDGPU.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone store double %result, double addrspace(1)* %out, align 8 ret void } |
