diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrFPU.td | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 18 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/Mips64InstrInfo.td | 203 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrFPU.td | 43 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 78 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsMSAInstrInfo.td | 13 |
7 files changed, 206 insertions, 161 deletions
diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td index 710358cdd06..f795112ae2b 100644 --- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -1732,6 +1732,11 @@ defm : SelectInt_Pats<i32, OR_MM, XORI_MMR6, SLTi_MM, SLTiu_MM, SELEQZ_MMR6, defm S_MMR6 : Cmp_Pats<f32, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6; defm D_MMR6 : Cmp_Pats<f64, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6; +def : MipsPat<(f32 fpimm0), (MTC1_MMR6 ZERO)>, ISA_MICROMIPS32R6; +def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1 ZERO))>, ISA_MICROMIPS32R6; +def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), + (TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6; + def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm), (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>, ISA_MICROMIPS32R6; diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td index a90eb1a6b2c..84ae0eddf98 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td @@ -405,6 +405,10 @@ let AddedComplexity = 40 in { def : StoreRegImmPat<SWC1_MM, f32>, ISA_MICROMIPS; } +def : MipsPat<(f32 fpimm0), (MTC1_MM ZERO)>, ISA_MICROMIPS32_NOT_MIPS32R6; +def : MipsPat<(f32 fpimm0neg), (FNEG_S_MM (MTC1_MM ZERO))>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def : MipsPat<(f32 (fpround FGR64Opnd:$src)), (CVT_S_D64_MM FGR64Opnd:$src)>, ISA_MICROMIPS, FGR_64; def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), @@ -413,6 +417,9 @@ def : MipsPat<(f32 (fpround AFGR64Opnd:$src)), (CVT_S_D32_MM AFGR64Opnd:$src)>, ISA_MICROMIPS, FGR_32; def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), (CVT_D32_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS, FGR_32; +def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), + (TRUNC_W_MM AFGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6, + FGR_32; // Selects defm : MovzPats0<GPR32, FGR32, MOVZ_I_S_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM>, diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index 171e5ed74ed..961aad4279e 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -1264,17 +1264,19 @@ def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), (TAILCALL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6; -def : MipsPat<(atomic_load_16 addr:$a), - (LH_MM addr:$a)>; - defm : BrcondPats<GPR32, BEQ_MM, BEQ_MM, BNE_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM, ZERO>, ISA_MICROMIPS32_NOT_MIPS32R6; -defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>; -defm : SetlePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>; -defm : SetgtPats<GPR32, SLT_MM, SLTu_MM>; -defm : SetgePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>; -defm : SetgeImmPats<GPR32, XORi_MM, SLTi_MM, SLTiu_MM>; +def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), + (BLEZ_MM i32:$lhs, bb:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6; +def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), + (BGEZ_MM i32:$lhs, bb:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6; + +defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>, ISA_MICROMIPS; +defm : SetlePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>, ISA_MICROMIPS; +defm : SetgtPats<GPR32, SLT_MM, SLTu_MM>, ISA_MICROMIPS; +defm : SetgePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>, ISA_MICROMIPS; +defm : SetgeImmPats<GPR32, XORi_MM, SLTi_MM, SLTiu_MM>, ISA_MICROMIPS; // Select patterns diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index 381d87dfe44..b8d7ffabb25 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -600,124 +600,138 @@ let AdditionalPredicates = [UseIndirectJumpsHazard] in //===----------------------------------------------------------------------===// // Materialize i64 constants. -defm : MaterializeImms<i64, ZERO_64, DADDiu, LUi64, ORi64>; +defm : MaterializeImms<i64, ZERO_64, DADDiu, LUi64, ORi64>, ISA_MIPS3, GPR_64; def : MipsPat<(i64 immZExt32Low16Zero:$imm), - (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16)>; + (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16)>, ISA_MIPS3, GPR_64; def : MipsPat<(i64 immZExt32:$imm), (ORi64 (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16), - (LO16 imm:$imm))>; + (LO16 imm:$imm))>, ISA_MIPS3, GPR_64; // extended loads -def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; -def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; -def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; -def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; +def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>, ISA_MIPS3, + GPR_64; +def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>, ISA_MIPS3, + GPR_64; +def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>, ISA_MIPS3, + GPR_64; +def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>, ISA_MIPS3, + GPR_64; // hi/lo relocs let AdditionalPredicates = [NotInMicroMips] in -defm : MipsHiLoRelocs<LUi64, DADDiu, ZERO_64, GPR64Opnd>, SYM_32; +defm : MipsHiLoRelocs<LUi64, DADDiu, ZERO_64, GPR64Opnd>, ISA_MIPS3, GPR_64, + SYM_32; -def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; -def : MipsPat<(MipsGotHi texternalsym:$in), (LUi64 texternalsym:$in)>; +def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>, ISA_MIPS3, + GPR_64; +def : MipsPat<(MipsGotHi texternalsym:$in), (LUi64 texternalsym:$in)>, + ISA_MIPS3, GPR_64; // highest/higher/hi/lo relocs let AdditionalPredicates = [NotInMicroMips] in { def : MipsPat<(MipsJmpLink (i64 texternalsym:$dst)), - (JAL texternalsym:$dst)>, SYM_64; + (JAL texternalsym:$dst)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(MipsHighest (i64 tglobaladdr:$in)), - (LUi64 tglobaladdr:$in)>, SYM_64; + (LUi64 tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(MipsHighest (i64 tblockaddress:$in)), - (LUi64 tblockaddress:$in)>, SYM_64; + (LUi64 tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(MipsHighest (i64 tjumptable:$in)), - (LUi64 tjumptable:$in)>, SYM_64; + (LUi64 tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(MipsHighest (i64 tconstpool:$in)), - (LUi64 tconstpool:$in)>, SYM_64; + (LUi64 tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(MipsHighest (i64 tglobaltlsaddr:$in)), - (LUi64 tglobaltlsaddr:$in)>, SYM_64; + (LUi64 tglobaltlsaddr:$in)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(MipsHighest (i64 texternalsym:$in)), - (LUi64 texternalsym:$in)>, SYM_64; + (LUi64 texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(MipsHigher (i64 tglobaladdr:$in)), - (DADDiu ZERO_64, tglobaladdr:$in)>, SYM_64; + (DADDiu ZERO_64, tglobaladdr:$in)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(MipsHigher (i64 tblockaddress:$in)), - (DADDiu ZERO_64, tblockaddress:$in)>, SYM_64; + (DADDiu ZERO_64, tblockaddress:$in)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(MipsHigher (i64 tjumptable:$in)), - (DADDiu ZERO_64, tjumptable:$in)>, SYM_64; + (DADDiu ZERO_64, tjumptable:$in)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(MipsHigher (i64 tconstpool:$in)), - (DADDiu ZERO_64, tconstpool:$in)>, SYM_64; + (DADDiu ZERO_64, tconstpool:$in)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(MipsHigher (i64 tglobaltlsaddr:$in)), - (DADDiu ZERO_64, tglobaltlsaddr:$in)>, SYM_64; + (DADDiu ZERO_64, tglobaltlsaddr:$in)>, ISA_MIPS3, GPR_64, + SYM_64; def : MipsPat<(MipsHigher (i64 texternalsym:$in)), - (DADDiu ZERO_64, texternalsym:$in)>, SYM_64; + (DADDiu ZERO_64, texternalsym:$in)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaladdr:$lo))), - (DADDiu GPR64:$hi, tglobaladdr:$lo)>, SYM_64; + (DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tblockaddress:$lo))), - (DADDiu GPR64:$hi, tblockaddress:$lo)>, SYM_64; + (DADDiu GPR64:$hi, tblockaddress:$lo)>, ISA_MIPS3, GPR_64, + SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tjumptable:$lo))), - (DADDiu GPR64:$hi, tjumptable:$lo)>, SYM_64; + (DADDiu GPR64:$hi, tjumptable:$lo)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tconstpool:$lo))), - (DADDiu GPR64:$hi, tconstpool:$lo)>, SYM_64; + (DADDiu GPR64:$hi, tconstpool:$lo)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaltlsaddr:$lo))), - (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, SYM_64; + (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, ISA_MIPS3, GPR_64, + SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaladdr:$lo))), - (DADDiu GPR64:$hi, tglobaladdr:$lo)>, SYM_64; + (DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tblockaddress:$lo))), - (DADDiu GPR64:$hi, tblockaddress:$lo)>, SYM_64; + (DADDiu GPR64:$hi, tblockaddress:$lo)>, ISA_MIPS3, GPR_64, + SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tjumptable:$lo))), - (DADDiu GPR64:$hi, tjumptable:$lo)>, SYM_64; + (DADDiu GPR64:$hi, tjumptable:$lo)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tconstpool:$lo))), - (DADDiu GPR64:$hi, tconstpool:$lo)>, SYM_64; + (DADDiu GPR64:$hi, tconstpool:$lo)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaltlsaddr:$lo))), - (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, SYM_64; + (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, ISA_MIPS3, GPR_64, + SYM_64; def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaladdr:$lo))), - (DADDiu GPR64:$hi, tglobaladdr:$lo)>, SYM_64; + (DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tblockaddress:$lo))), - (DADDiu GPR64:$hi, tblockaddress:$lo)>, SYM_64; + (DADDiu GPR64:$hi, tblockaddress:$lo)>, ISA_MIPS3, GPR_64, + SYM_64; def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tjumptable:$lo))), - (DADDiu GPR64:$hi, tjumptable:$lo)>, SYM_64; + (DADDiu GPR64:$hi, tjumptable:$lo)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tconstpool:$lo))), - (DADDiu GPR64:$hi, tconstpool:$lo)>, SYM_64; + (DADDiu GPR64:$hi, tconstpool:$lo)>, ISA_MIPS3, GPR_64, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaltlsaddr:$lo))), - (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, SYM_64; + (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, ISA_MIPS3, GPR_64, + SYM_64; } // gp_rel relocs def : MipsPat<(add GPR64:$gp, (MipsGPRel tglobaladdr:$in)), - (DADDiu GPR64:$gp, tglobaladdr:$in)>, ABI_N64; + (DADDiu GPR64:$gp, tglobaladdr:$in)>, ISA_MIPS3, ABI_N64; def : MipsPat<(add GPR64:$gp, (MipsGPRel tconstpool:$in)), - (DADDiu GPR64:$gp, tconstpool:$in)>, ABI_N64; + (DADDiu GPR64:$gp, tconstpool:$in)>, ISA_MIPS3, ABI_N64; -def : WrapperPat<tglobaladdr, DADDiu, GPR64>; -def : WrapperPat<tconstpool, DADDiu, GPR64>; -def : WrapperPat<texternalsym, DADDiu, GPR64>; -def : WrapperPat<tblockaddress, DADDiu, GPR64>; -def : WrapperPat<tjumptable, DADDiu, GPR64>; -def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>; +def : WrapperPat<tglobaladdr, DADDiu, GPR64>, ISA_MIPS3, GPR_64; +def : WrapperPat<tconstpool, DADDiu, GPR64>, ISA_MIPS3, GPR_64; +def : WrapperPat<texternalsym, DADDiu, GPR64>, ISA_MIPS3, GPR_64; +def : WrapperPat<tblockaddress, DADDiu, GPR64>, ISA_MIPS3, GPR_64; +def : WrapperPat<tjumptable, DADDiu, GPR64>, ISA_MIPS3, GPR_64; +def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>, ISA_MIPS3, GPR_64; defm : BrcondPats<GPR64, BEQ64, BEQ, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, - ZERO_64>; + ZERO_64>, ISA_MIPS3, GPR_64; def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst), - (BLEZ64 i64:$lhs, bb:$dst)>; + (BLEZ64 i64:$lhs, bb:$dst)>, ISA_MIPS3, GPR_64; def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst), - (BGEZ64 i64:$lhs, bb:$dst)>; + (BGEZ64 i64:$lhs, bb:$dst)>, ISA_MIPS3, GPR_64; // setcc patterns let AdditionalPredicates = [NotInMicroMips] in { - defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>; - defm : SetlePats<GPR64, XORi, SLT64, SLTu64>; - defm : SetgtPats<GPR64, SLT64, SLTu64>; - defm : SetgePats<GPR64, XORi, SLT64, SLTu64>; - defm : SetgeImmPats<GPR64, XORi, SLTi64, SLTiu64>; + defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>, ISA_MIPS3, GPR_64; + defm : SetlePats<GPR64, XORi, SLT64, SLTu64>, ISA_MIPS3, GPR_64; + defm : SetgtPats<GPR64, SLT64, SLTu64>, ISA_MIPS3, GPR_64; + defm : SetgePats<GPR64, XORi, SLT64, SLTu64>, ISA_MIPS3, GPR_64; + defm : SetgeImmPats<GPR64, XORi, SLTi64, SLTiu64>, ISA_MIPS3, GPR_64; } // truncate def : MipsPat<(trunc (assertsext GPR64:$src)), - (EXTRACT_SUBREG GPR64:$src, sub_32)>; + (EXTRACT_SUBREG GPR64:$src, sub_32)>, ISA_MIPS3, GPR_64; // The forward compatibility strategy employed by MIPS requires us to treat // values as being sign extended to an infinite number of bits. This allows // existing software to run without modification on any future MIPS @@ -729,39 +743,44 @@ def : MipsPat<(trunc (assertsext GPR64:$src)), // such as (trunc:i32 (assertzext:i64 X, i32)), because the sign-bit of the // lower subreg would not be replicated into the upper half. def : MipsPat<(trunc (assertzext_lt_i32 GPR64:$src)), - (EXTRACT_SUBREG GPR64:$src, sub_32)>; + (EXTRACT_SUBREG GPR64:$src, sub_32)>, ISA_MIPS3, GPR_64; def : MipsPat<(i32 (trunc GPR64:$src)), - (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>; + (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>, ISA_MIPS3, GPR_64; // variable shift instructions patterns def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))), - (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; + (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>, + ISA_MIPS3, GPR_64; def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))), - (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; + (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>, + ISA_MIPS3, GPR_64; def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))), - (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; -let AdditionalPredicates = [NotInMicroMips] in { - def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))), - (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; -} + (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>, + ISA_MIPS3, GPR_64; +def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))), + (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>, + ISA_MIPS3, GPR_64; // 32-to-64-bit extension def : MipsPat<(i64 (anyext GPR32:$src)), - (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>; -def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>; -def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>; + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>, + ISA_MIPS3, GPR_64; +def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>, + ISA_MIPS3, GPR_64; +def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>, ISA_MIPS3, + GPR_64; let AdditionalPredicates = [NotInMicroMips] in { def : MipsPat<(i64 (zext GPR32:$src)), (DEXT64_32 GPR32:$src, 0, 32)>, - ISA_MIPS64R2; + ISA_MIPS64R2, GPR_64; def : MipsPat<(i64 (zext (i32 (shl GPR32:$rt, immZExt5:$imm)))), (CINS64_32 GPR32:$rt, imm:$imm, (immZExt5To31 imm:$imm))>, - ASE_MIPS64_CNMIPS; + ISA_MIPS64R2, GPR_64, ASE_MIPS64_CNMIPS; } // Sign extend in register def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)), - (SLL64_64 GPR64:$src)>; + (SLL64_64 GPR64:$src)>, ISA_MIPS3, GPR_64; // bswap MipsPattern def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>, ISA_MIPS64R2; @@ -769,40 +788,50 @@ def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>, ISA_MIPS64R2; // Carry pattern let AdditionalPredicates = [NotInMicroMips] in { def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs), - (DSUBu GPR64:$lhs, GPR64:$rhs)>; + (DSUBu GPR64:$lhs, GPR64:$rhs)>, ISA_MIPS3, GPR_64; def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs), - (DADDu GPR64:$lhs, GPR64:$rhs)>, ASE_NOT_DSP; + (DADDu GPR64:$lhs, GPR64:$rhs)>, ISA_MIPS3, ASE_NOT_DSP, GPR_64; def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm), - (DADDiu GPR64:$lhs, imm:$imm)>, ASE_NOT_DSP; + (DADDiu GPR64:$lhs, imm:$imm)>, ISA_MIPS3, ASE_NOT_DSP, GPR_64; } // Octeon bbit0/bbit1 MipsPattern def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), - (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; + (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, + ISA_MIPS64R2, ASE_MIPS64_CNMIPS; def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), - (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; + (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, + ISA_MIPS64R2, ASE_MIPS64_CNMIPS; def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), - (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; + (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, + ISA_MIPS64R2, ASE_MIPS64_CNMIPS; def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), - (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; + (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, + ISA_MIPS64R2, ASE_MIPS64_CNMIPS; def : MipsPat<(brcond (i32 (seteq (and i32:$lhs, PowerOf2LO_i32:$mask), 0)), bb:$dst), (BBIT0 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32), - (Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; + (Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ISA_MIPS64R2, + ASE_MIPS64_CNMIPS; def : MipsPat<(brcond (i32 (setne (and i32:$lhs, PowerOf2LO_i32:$mask), 0)), bb:$dst), (BBIT1 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32), - (Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; + (Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ISA_MIPS64R2, + ASE_MIPS64_CNMIPS; // Atomic load patterns. -def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>; -def : MipsPat<(atomic_load_16 addr:$a), (LH64 addr:$a)>; -def : MipsPat<(atomic_load_32 addr:$a), (LW64 addr:$a)>; -def : MipsPat<(atomic_load_64 addr:$a), (LD addr:$a)>; +def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>, ISA_MIPS3, GPR_64; +def : MipsPat<(atomic_load_16 addr:$a), (LH64 addr:$a)>, ISA_MIPS3, GPR_64; +def : MipsPat<(atomic_load_32 addr:$a), (LW64 addr:$a)>, ISA_MIPS3, GPR_64; +def : MipsPat<(atomic_load_64 addr:$a), (LD addr:$a)>, ISA_MIPS3, GPR_64; // Atomic store patterns. -def : MipsPat<(atomic_store_8 addr:$a, GPR64:$v), (SB64 GPR64:$v, addr:$a)>; -def : MipsPat<(atomic_store_16 addr:$a, GPR64:$v), (SH64 GPR64:$v, addr:$a)>; -def : MipsPat<(atomic_store_32 addr:$a, GPR64:$v), (SW64 GPR64:$v, addr:$a)>; -def : MipsPat<(atomic_store_64 addr:$a, GPR64:$v), (SD GPR64:$v, addr:$a)>; +def : MipsPat<(atomic_store_8 addr:$a, GPR64:$v), (SB64 GPR64:$v, addr:$a)>, + ISA_MIPS3, GPR_64; +def : MipsPat<(atomic_store_16 addr:$a, GPR64:$v), (SH64 GPR64:$v, addr:$a)>, + ISA_MIPS3, GPR_64; +def : MipsPat<(atomic_store_32 addr:$a, GPR64:$v), (SW64 GPR64:$v, addr:$a)>, + ISA_MIPS3, GPR_64; +def : MipsPat<(atomic_store_64 addr:$a, GPR64:$v), (SD GPR64:$v, addr:$a)>, + ISA_MIPS3, GPR_64; //===----------------------------------------------------------------------===// // Instruction aliases diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td index 6d05731d8c4..b17a340faba 100644 --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -860,30 +860,31 @@ let AdditionalPredicates = [NotInMicroMips] in { //===----------------------------------------------------------------------===// // Floating Point Patterns //===----------------------------------------------------------------------===// -def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; -def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; +def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>, ISA_MIPS1; +def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>, ISA_MIPS1; def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)), (PseudoCVT_S_W GPR32Opnd:$src)>; def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), - (TRUNC_W_S FGR32Opnd:$src)>; + (TRUNC_W_S FGR32Opnd:$src)>, ISA_MIPS1; def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src), - (MTC1_D64 GPR32Opnd:$src)>, FGR_64; + (MTC1_D64 GPR32Opnd:$src)>, ISA_MIPS1, FGR_64; def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32; -def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), - (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32; let AdditionalPredicates = [NotInMicroMips] in { + def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), + (TRUNC_W_D32 AFGR64Opnd:$src)>, ISA_MIPS2, FGR_32; def : MipsPat<(f32 (fpround AFGR64Opnd:$src)), - (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32; + (CVT_S_D32 AFGR64Opnd:$src)>, ISA_MIPS1, FGR_32; def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), - (CVT_D32_S FGR32Opnd:$src)>, FGR_32; + (CVT_D32_S FGR32Opnd:$src)>, ISA_MIPS1, FGR_32; } -def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64; -def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64; +def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, ISA_MIPS3, GPR_64, FGR_64; +def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, ISA_MIPS3, GPR_64, + FGR_64; def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64; @@ -893,17 +894,17 @@ def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)), (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64; def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), - (TRUNC_W_D64 FGR64Opnd:$src)>, FGR_64; + (TRUNC_W_D64 FGR64Opnd:$src)>, ISA_MIPS3, FGR_64; def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), - (TRUNC_L_S FGR32Opnd:$src)>, FGR_64; + (TRUNC_L_S FGR32Opnd:$src)>, ISA_MIPS2, FGR_64; def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), - (TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64; + (TRUNC_L_D64 FGR64Opnd:$src)>, ISA_MIPS2, FGR_64; let AdditionalPredicates = [NotInMicroMips] in { def : MipsPat<(f32 (fpround FGR64Opnd:$src)), - (CVT_S_D64 FGR64Opnd:$src)>, FGR_64; + (CVT_S_D64 FGR64Opnd:$src)>, ISA_MIPS1, FGR_64; def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), - (CVT_D64_S FGR32Opnd:$src)>, FGR_64; + (CVT_D64_S FGR32Opnd:$src)>, ISA_MIPS1, FGR_64; } // To generate NMADD and NMSUB instructions when fneg node is present @@ -923,13 +924,13 @@ let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in { // Patterns for loads/stores with a reg+imm operand. let AdditionalPredicates = [NotInMicroMips] in { let AddedComplexity = 40 in { - def : LoadRegImmPat<LWC1, f32, load>; - def : StoreRegImmPat<SWC1, f32>; + def : LoadRegImmPat<LWC1, f32, load>, ISA_MIPS1; + def : StoreRegImmPat<SWC1, f32>, ISA_MIPS1; - def : LoadRegImmPat<LDC164, f64, load>, FGR_64; - def : StoreRegImmPat<SDC164, f64>, FGR_64; + def : LoadRegImmPat<LDC164, f64, load>, ISA_MIPS1, FGR_64; + def : StoreRegImmPat<SDC164, f64>, ISA_MIPS1, FGR_64; - def : LoadRegImmPat<LDC1, f64, load>, FGR_32; - def : StoreRegImmPat<SDC1, f64>, FGR_32; + def : LoadRegImmPat<LDC1, f64, load>, ISA_MIPS1, FGR_32; + def : StoreRegImmPat<SDC1, f64>, ISA_MIPS1, FGR_32; } } diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index a3ef3bea0b3..c319ab15607 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -505,9 +505,7 @@ class FPOP_FUSION_FAST { //===----------------------------------------------------------------------===// -class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl { - let EncodingPredicates = [HasStdEnc]; -} +class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl; class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> : InstAlias<Asm, Result, Emit>, PredicateControl; @@ -3034,17 +3032,17 @@ def : MipsPat<(VT immSExt16:$imm), (ADDiuOp ZEROReg, imm:$imm)>; } let AdditionalPredicates = [NotInMicroMips] in - defm : MaterializeImms<i32, ZERO, ADDiu, LUi, ORi>; + defm : MaterializeImms<i32, ZERO, ADDiu, LUi, ORi>, ISA_MIPS1; // Carry MipsPatterns let AdditionalPredicates = [NotInMicroMips] in { def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), - (SUBu GPR32:$lhs, GPR32:$rhs)>; + (SUBu GPR32:$lhs, GPR32:$rhs)>, ISA_MIPS1; } def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs), - (ADDu GPR32:$lhs, GPR32:$rhs)>, ASE_NOT_DSP; + (ADDu GPR32:$lhs, GPR32:$rhs)>, ISA_MIPS1, ASE_NOT_DSP; def : MipsPat<(addc GPR32:$src, immSExt16:$imm), - (ADDiu GPR32:$src, imm:$imm)>, ASE_NOT_DSP; + (ADDiu GPR32:$src, imm:$imm)>, ISA_MIPS1, ASE_NOT_DSP; // Support multiplication for pre-Mips32 targets that don't have // the MUL instruction. @@ -3058,16 +3056,16 @@ def : MipsPat<(MipsSync (i32 immz)), // Call def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), - (JAL texternalsym:$dst)>; + (JAL texternalsym:$dst)>, ISA_MIPS1; //def : MipsPat<(MipsJmpLink GPR32:$dst), // (JALR GPR32:$dst)>; // Tail call let AdditionalPredicates = [NotInMicroMips] in { def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), - (TAILCALL tglobaladdr:$dst)>; + (TAILCALL tglobaladdr:$dst)>, ISA_MIPS1; def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), - (TAILCALL texternalsym:$dst)>; + (TAILCALL texternalsym:$dst)>, ISA_MIPS1; } // hi/lo relocs multiclass MipsHiLoRelocs<Instruction Lui, Instruction Addiu, @@ -3132,13 +3130,13 @@ let AdditionalPredicates = [NotInMicroMips] in { // extended loads let AdditionalPredicates = [NotInMicroMips] in { - def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; - def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; - def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; -} + def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>, ISA_MIPS1; + def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>, ISA_MIPS1; + def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>, ISA_MIPS1; -// peepholes -def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; + // peepholes + def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>, ISA_MIPS1; +} // brcond patterns multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BEQOp1, @@ -3172,12 +3170,13 @@ def : MipsPat<(brcond RC:$cond, bb:$dst), (BNEOp RC:$cond, ZEROReg, bb:$dst)>; } let AdditionalPredicates = [NotInMicroMips] in { - defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; + defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>, + ISA_MIPS1; + def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), + (BLEZ i32:$lhs, bb:$dst)>, ISA_MIPS1; + def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), + (BGEZ i32:$lhs, bb:$dst)>, ISA_MIPS1; } -def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), - (BLEZ i32:$lhs, bb:$dst)>; -def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), - (BGEZ i32:$lhs, bb:$dst)>; // setcc patterns multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, @@ -3224,38 +3223,39 @@ multiclass SetgeImmPats<RegisterClass RC, Instruction XORiOp, } let AdditionalPredicates = [NotInMicroMips] in { - defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>; - defm : SetlePats<GPR32, XORi, SLT, SLTu>; - defm : SetgtPats<GPR32, SLT, SLTu>; - defm : SetgePats<GPR32, XORi, SLT, SLTu>; - defm : SetgeImmPats<GPR32, XORi, SLTi, SLTiu>; + defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>, ISA_MIPS1; + defm : SetlePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1; + defm : SetgtPats<GPR32, SLT, SLTu>, ISA_MIPS1; + defm : SetgePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1; + defm : SetgeImmPats<GPR32, XORi, SLTi, SLTiu>, ISA_MIPS1; // bswap pattern def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>, ISA_MIPS32R2; } // Load halfword/word patterns. -let AddedComplexity = 40 in { - let AdditionalPredicates = [NotInMicroMips] in { +let AdditionalPredicates = [NotInMicroMips] in { + let AddedComplexity = 40 in { def : LoadRegImmPat<LBu, i32, zextloadi8>, ISA_MIPS1; def : LoadRegImmPat<LHu, i32, zextloadi16>, ISA_MIPS1; def : LoadRegImmPat<LB, i32, sextloadi8>, ISA_MIPS1; def : LoadRegImmPat<LH, i32, sextloadi16>, ISA_MIPS1; def : LoadRegImmPat<LW, i32, load>, ISA_MIPS1; } -} -// Atomic load patterns. -def : MipsPat<(atomic_load_8 addr:$a), (LB addr:$a)>; -let AdditionalPredicates = [NotInMicroMips] in { - def : MipsPat<(atomic_load_16 addr:$a), (LH addr:$a)>; -} -def : MipsPat<(atomic_load_32 addr:$a), (LW addr:$a)>; + // Atomic load patterns. + def : MipsPat<(atomic_load_8 addr:$a), (LB addr:$a)>, ISA_MIPS1; + def : MipsPat<(atomic_load_16 addr:$a), (LH addr:$a)>, ISA_MIPS1; + def : MipsPat<(atomic_load_32 addr:$a), (LW addr:$a)>, ISA_MIPS1; -// Atomic store patterns. -def : MipsPat<(atomic_store_8 addr:$a, GPR32:$v), (SB GPR32:$v, addr:$a)>; -def : MipsPat<(atomic_store_16 addr:$a, GPR32:$v), (SH GPR32:$v, addr:$a)>; -def : MipsPat<(atomic_store_32 addr:$a, GPR32:$v), (SW GPR32:$v, addr:$a)>; + // Atomic store patterns. + def : MipsPat<(atomic_store_8 addr:$a, GPR32:$v), (SB GPR32:$v, addr:$a)>, + ISA_MIPS1; + def : MipsPat<(atomic_store_16 addr:$a, GPR32:$v), (SH GPR32:$v, addr:$a)>, + ISA_MIPS1; + def : MipsPat<(atomic_store_32 addr:$a, GPR32:$v), (SW GPR32:$v, addr:$a)>, + ISA_MIPS1; +} //===----------------------------------------------------------------------===// // Floating Point Support diff --git a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td index f43f5d74ead..d83f75ffa1c 100644 --- a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td @@ -3150,17 +3150,17 @@ def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC; def : MipsPat<(fsub MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)), (FMSUB_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>, - FPOP_FUSION_FAST; + ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; def : MipsPat<(fsub MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)), (FMSUB_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>, - FPOP_FUSION_FAST; + ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; def : MipsPat<(fadd MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)), (FMADD_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>, - FPOP_FUSION_FAST; + ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; def : MipsPat<(fadd MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)), (FMADD_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>, - FPOP_FUSION_FAST; + ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC; def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC; @@ -3792,12 +3792,13 @@ let ASEPredicate = [HasMSA] in { } def : MipsPat<(MipsTruncIntFP MSA128F16:$ws), - (TRUNC_W_D64 (MSA_FP_EXTEND_D_PSEUDO MSA128F16:$ws))>; + (TRUNC_W_D64 (MSA_FP_EXTEND_D_PSEUDO MSA128F16:$ws))>, ISA_MIPS1, + ASE_MSA; def : MipsPat<(MipsFPCmp MSA128F16:$ws, MSA128F16:$wt, imm:$cond), (FCMP_S32 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$ws), (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$wt), imm:$cond)>, - ISA_MIPS1_NOT_32R6_64R6; + ISA_MIPS1_NOT_32R6_64R6, ASE_MSA; } def vsplati64_imm_eq_63 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ |
