5 files changed, 12 insertions, 15 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index a7f155df765..e1da7f09b0c 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -294,7 +294,6 @@ def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
                                    FeatureFuseAES,
                                    FeatureNEON,
                                    FeaturePerfMon,
-                                   FeatureSlowMisaligned128Store,
                                    FeatureZCRegMove,
                                    FeatureZCZeroing,
                                    FeatureZCZeroingFPWorkaround
diff --git a/llvm/test/CodeGen/AArch64/arm64-stp.ll b/llvm/test/CodeGen/AArch64/arm64-stp.ll
index 9239077c166..d3fd87e5a89 100644
--- a/llvm/test/CodeGen/AArch64/arm64-stp.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-stp.ll
@@ -105,8 +105,8 @@ define void @splat_v4i32(i32 %v, i32 *%p) {
 entry:
 
 ; CHECK-LABEL: splat_v4i32
-; CHECK-DAG: stp w0, w0, [x1]
-; CHECK-DAG: stp w0, w0, [x1, #8]
+; CHECK-DAG: dup v0.4s, w0
+; CHECK-DAG: str q0, [x1]
 ; CHECK: ret
 
   %p17 = insertelement <4 x i32> undef, i32 %v, i32 0
@@ -129,8 +129,7 @@ entry:
 ; CHECK-DAG: mov v[[REG1]].s[1], w0
 ; CHECK-DAG: mov v[[REG1]].s[2], w0
 ; CHECK-DAG: mov v[[REG1]].s[3], w0
-; CHECK: ext v[[REG2:[0-9]+]].16b, v[[REG1]].16b, v[[REG1]].16b, #8
-; CHECK: stp d[[REG1]], d[[REG2]], [x1]
+; CHECK: str q[[REG1]], [x1]
 ; CHECK: ret
 
   %p17 = insertelement <4 x i32> undef, i32 %v, i32 %v
@@ -151,8 +150,7 @@ entry:
 ; CHECK: mov v[[REG1]].s[1], w0
 ; CHECK-DAG: mov v[[REG1]].s[2], w0
 ; CHECK-DAG: mov v[[REG1]].s[3], w0
-; CHECK: ext v[[REG2:[0-9]+]].16b, v[[REG1]].16b, v[[REG1]].16b, #8
-; CHECK: stp d[[REG1]], d[[REG2]], [x1]
+; CHECK: str q[[REG1]], [x1]
 ; CHECK: ret
 
   %p18 = insertelement <4 x i32> %vin, i32 %v, i32 1
diff --git a/llvm/test/CodeGen/AArch64/arm64-stur.ll b/llvm/test/CodeGen/AArch64/arm64-stur.ll
index 8e0736c4fba..d4ac3630bc1 100644
--- a/llvm/test/CodeGen/AArch64/arm64-stur.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-stur.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mcpu=cyclone -mattr=+slow-misaligned-128store | FileCheck %s
 %struct.X = type <{ i32, i64, i64 }>
 
 define void @foo1(i32* %p, i64 %val) nounwind {
diff --git a/llvm/test/CodeGen/AArch64/merge-store.ll b/llvm/test/CodeGen/AArch64/merge-store.ll
index 1d26e4a42b1..5e4e7432170 100644
--- a/llvm/test/CodeGen/AArch64/merge-store.ll
+++ b/llvm/test/CodeGen/AArch64/merge-store.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=cyclone | FileCheck %s --check-prefix=CYCLONE --check-prefix=CHECK
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=cyclone -mattr=+slow-misaligned-128store | FileCheck %s --check-prefix=SPLITTING --check-prefix=CHECK
 ; RUN: llc < %s -mtriple=aarch64-eabi -mattr=-slow-misaligned-128store | FileCheck %s --check-prefix=MISALIGNED --check-prefix=CHECK
 
 @g0 = external global <3 x float>, align 16
@@ -44,9 +44,9 @@ define void @merge_vec_extract_stores(<4 x float> %v1, <2 x float>* %ptr) {
 ; FIXME: Ideally we would like to use a generic target for this test, but this relies
 ; on suppressing store pairs.
 
-; CYCLONE-LABEL:    merge_vec_extract_stores
-; CYCLONE:          ext   v1.16b, v0.16b, v0.16b, #8
-; CYCLONE-NEXT:     str   d0, [x0, #24]
-; CYCLONE-NEXT:     str   d1, [x0, #32]
-; CYCLONE-NEXT:     ret
+; SPLITTING-LABEL:    merge_vec_extract_stores
+; SPLITTING:          ext   v1.16b, v0.16b, v0.16b, #8
+; SPLITTING-NEXT:     str   d0, [x0, #24]
+; SPLITTING-NEXT:     str   d1, [x0, #32]
+; SPLITTING-NEXT:     ret
 }
diff --git a/llvm/test/CodeGen/AArch64/misched-stp.ll b/llvm/test/CodeGen/AArch64/misched-stp.ll
index 1afec40f192..370bf3fb964 100644
--- a/llvm/test/CodeGen/AArch64/misched-stp.ll
+++ b/llvm/test/CodeGen/AArch64/misched-stp.ll
@@ -1,5 +1,5 @@
 ; REQUIRES: asserts
-; RUN: llc < %s -mtriple=aarch64 -mcpu=cyclone -mattr=+use-aa -enable-misched -verify-misched -o - | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -mcpu=cyclone -mattr=+use-aa,+slow-misaligned-128store -enable-misched -verify-misched -o - | FileCheck %s
 
 ; Tests to check that the scheduler dependencies derived from alias analysis are
 ; correct when we have loads that have been split up so that they can later be