diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/crbit-asm.ll | 59 |
2 files changed, 67 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 193ee3097c4..f53557319ef 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -8292,6 +8292,8 @@ PPCTargetLowering::getConstraintType(const std::string &Constraint) const { // suboptimal. return C_Memory; } + } else if (Constraint == "wc") { // individual CR bits. + return C_RegisterClass; } return TargetLowering::getConstraintType(Constraint); } @@ -8309,7 +8311,11 @@ PPCTargetLowering::getSingleConstraintMatchWeight( if (CallOperandVal == NULL) return CW_Default; Type *type = CallOperandVal->getType(); + // Look at the constraint type. + if (StringRef(constraint) == "wc" && type->isIntegerTy(1)) + return CW_Register; // an individual CR bit. + switch (*constraint) { default: weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); @@ -8365,6 +8371,8 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, case 'y': // crrc return std::make_pair(0U, &PPC::CRRCRegClass); } + } else if (Constraint == "wc") { // an individual CR bit. + return std::make_pair(0U, &PPC::CRBITRCRegClass); } std::pair<unsigned, const TargetRegisterClass*> R = diff --git a/llvm/test/CodeGen/PowerPC/crbit-asm.ll b/llvm/test/CodeGen/PowerPC/crbit-asm.ll new file mode 100644 index 00000000000..373e334f02b --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/crbit-asm.ll @@ -0,0 +1,59 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 { +entry: + %0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2) #0 + %1 = and i8 %0, 1 + %tobool3 = icmp ne i8 %1, 0 + ret i1 %tobool3 + +; CHECK-LABEL: @testi1 +; CHECK-DAG: andi. {{[0-9]+}}, 3, 1 +; CHECK-DAG: li [[REG1:[0-9]+]], 0 +; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1 +; CHECK-DAG: andi. {{[0-9]+}}, 4, 1 +; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1 +; CHECK-DAG: li [[REG4:[0-9]+]], 1 +; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]] +; CHECK: blr +} + +define signext i32 @testi32(i32 signext %b1, i32 signext %b2) #0 { +entry: + %0 = tail call i32 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i32 %b1, i32 %b2) #0 + ret i32 %0 + +; The ABI sign_extend should combine with the any_extend from the asm result, +; and the result will be 0 or -1. This highlights the fact that only the first +; bit is meaningful. +; CHECK-LABEL: @testi32 +; CHECK-DAG: andi. {{[0-9]+}}, 3, 1 +; CHECK-DAG: li [[REG1:[0-9]+]], 0 +; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1 +; CHECK-DAG: andi. {{[0-9]+}}, 4, 1 +; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1 +; CHECK-DAG: li [[REG4:[0-9]+]], -1 +; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]] +; CHECK: blr +} + +define zeroext i8 @testi8(i8 zeroext %b1, i8 zeroext %b2) #0 { +entry: + %0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i8 %b1, i8 %b2) #0 + ret i8 %0 + +; CHECK-LABEL: @testi8 +; CHECK-DAG: andi. {{[0-9]+}}, 3, 1 +; CHECK-DAG: li [[REG1:[0-9]+]], 0 +; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1 +; CHECK-DAG: andi. {{[0-9]+}}, 4, 1 +; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1 +; CHECK-DAG: li [[REG4:[0-9]+]], 1 +; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]] +; CHECK: blr +} + +attributes #0 = { nounwind } + |
