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-rw-r--r--llvm/lib/Target/ARM/ARMCodeEmitter.cpp10
1 files changed, 6 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp
index 4bc50ff6ca3..b621c41e12a 100644
--- a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -552,10 +552,12 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
default:
abort(); // FIXME:
case TargetInstrInfo::INLINEASM: {
- const char* Value = MI.getOperand(0).getSymbolName();
- /* We allow inline assembler nodes with empty bodies - they can
- implicitly define registers, which is ok for JIT. */
- assert((Value[0] == 0) && "JIT does not support inline asm!\n");
+ // We allow inline assembler nodes with empty bodies - they can
+ // implicitly define registers, which is ok for JIT.
+ if (MI.getOperand(0).getSymbolName()[0]) {
+ assert(0 && "JIT does not support inline asm!\n");
+ abort();
+ }
break;
}
case TargetInstrInfo::DBG_LABEL:
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