diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/WebAssembly/PR41149.ll | 27 |
2 files changed, 28 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index f14b2e4cfab..ab1b1c5e936 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -68,6 +68,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { case ISD::ZERO_EXTEND_VECTOR_INREG: R = ScalarizeVecRes_VecInregOp(N); break; + case ISD::ABS: case ISD::ANY_EXTEND: case ISD::BITREVERSE: case ISD::BSWAP: diff --git a/llvm/test/CodeGen/WebAssembly/PR41149.ll b/llvm/test/CodeGen/WebAssembly/PR41149.ll new file mode 100644 index 00000000000..e53adf87e89 --- /dev/null +++ b/llvm/test/CodeGen/WebAssembly/PR41149.ll @@ -0,0 +1,27 @@ +; RUN: llc < %s -mtriple=wasm32-unknown-unknown | FileCheck %s + +; Regression test for PR41149. + +define void @mod() { +; CHECK-LABEL: mod: +; CHECK-NEXT: .functype mod () -> () +; CHECK: local.get 0 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: i32.load8_s 0 +; CHECK-NEXT: local.tee 0 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: i32.const 31 +; CHECK-NEXT: i32.shr_s +; CHECK-NEXT: local.tee 0 +; CHECK-NEXT: i32.add +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: i32.xor +; CHECK-NEXT: i32.store8 0 + %tmp = load <4 x i8>, <4 x i8>* undef + %tmp2 = icmp slt <4 x i8> %tmp, zeroinitializer + %tmp3 = sub <4 x i8> zeroinitializer, %tmp + %tmp4 = select <4 x i1> %tmp2, <4 x i8> %tmp3, <4 x i8> %tmp + store <4 x i8> %tmp4, <4 x i8>* undef + ret void +} + |
