diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Thumb/cortex-m0-unaligned-access.ll | 13 |
2 files changed, 19 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 0dec1c406a4..d2f3b203fc6 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -236,7 +236,7 @@ void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) { // // ARMv6 may or may not support unaligned accesses depending on the // SCTLR.U bit, which is architecture-specific. We assume ARMv6 - // Darwin targets support unaligned accesses, and others don't. + // Darwin and NetBSD targets support unaligned accesses, and others don't. // // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit // which raises an alignment fault on unaligned accesses. Linux @@ -249,6 +249,11 @@ void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) { (hasV7Ops() && (isTargetLinux() || isTargetNaCl() || isTargetNetBSD())) || (hasV6Ops() && (isTargetMachO() || isTargetNetBSD())); + // The one exception is cortex-m0, which despite being v6, does not + // support unaligned accesses. Rather than make the above boolean + // expression even more obtuse, just override the value here. + if (isThumb1Only() && isMClass()) + AllowsUnalignedMem = false; break; case StrictAlign: AllowsUnalignedMem = false; diff --git a/llvm/test/CodeGen/Thumb/cortex-m0-unaligned-access.ll b/llvm/test/CodeGen/Thumb/cortex-m0-unaligned-access.ll new file mode 100644 index 00000000000..c4403fe7efe --- /dev/null +++ b/llvm/test/CodeGen/Thumb/cortex-m0-unaligned-access.ll @@ -0,0 +1,13 @@ +; RUN: llc -mtriple=thumbv6m-apple-unknown-macho < %s | FileCheck --check-prefix=V6M %s +; RUN: llc -mtriple=thumbv7m-apple-unknown-macho < %s | FileCheck --check-prefix=V7M %s + +define i32 @split_load(i32* %p) nounwind { +; V6M-LABEL: split_load +; V6M: ldrh +; V6M: ldrh +; V7M-LABEL: split_load +; V7M-NOT: ldrh +; V7M: bx lr + %val = load i32* %p, align 2 + ret i32 %val +} |
