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-rw-r--r--llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp6
-rw-r--r--llvm/test/Transforms/InstCombine/or.ll7
2 files changed, 8 insertions, 5 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index efe1c068300..a661156f4ca 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -878,7 +878,7 @@ Value *InstCombiner::FoldAndOfICmps(ICmpInst *LHS, ICmpInst *RHS) {
return RHS;
case ICmpInst::ICMP_NE:
// Special case to get the ordering right when the values wrap around
- // zero.
+ // zero. Ie, we assumed the constants were unsigned when swapping earlier.
if (LHSC->getValue() == 0 && RHSC->getValue().isAllOnesValue())
std::swap(LHSC, RHSC);
if (LHSC == SubOne(RHSC)) {
@@ -1785,6 +1785,10 @@ Value *InstCombiner::FoldOrOfICmps(ICmpInst *LHS, ICmpInst *RHS,
}
}
+ // Special case to get the ordering right when the values wrap around
+ // zero. Ie, we assumed the constants were unsigned when swapping earlier.
+ if (LHSC->getValue() == 0 && RHSC->getValue().isAllOnesValue())
+ std::swap(LHSC, RHSC);
if (LHSC == SubOne(RHSC)) {
// (X == 13 | X == 14) -> X-13 <=u 1
// An 'add' is the canonical IR form, so favor that over a 'sub'.
diff --git a/llvm/test/Transforms/InstCombine/or.ll b/llvm/test/Transforms/InstCombine/or.ll
index bf575418ce9..ad46023d8a5 100644
--- a/llvm/test/Transforms/InstCombine/or.ll
+++ b/llvm/test/Transforms/InstCombine/or.ll
@@ -271,10 +271,9 @@ define i1 @cmp_eq_with_diff_one(i8 %x) {
define i1 @cmp_eq_with_diff_one_signed(i32 %x) {
; CHECK-LABEL: @cmp_eq_with_diff_one_signed(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 %x, -1
-; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 %x, 0
-; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP1]], [[CMP2]]
-; CHECK-NEXT: ret i1 [[OR]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 %x, 1
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 2
+; CHECK-NEXT: ret i1 [[TMP2]]
;
%cmp1 = icmp eq i32 %x, -1
%cmp2 = icmp eq i32 %x, 0
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