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-rw-r--r--llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp4
-rw-r--r--llvm/test/CodeGen/Hexagon/bit-phi.ll1
2 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 79787463684..a155762cd4a 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -2375,7 +2375,9 @@ bool BitSimplification::simplifyExtractLow(MachineInstr *MI,
DebugLoc DL = MI->getDebugLoc();
MachineBasicBlock &B = *MI->getParent();
unsigned NewR = MRI.createVirtualRegister(FRC);
- auto MIB = BuildMI(B, MI, DL, HII.get(ExtOpc), NewR)
+ auto At = MI->isPHI() ? B.getFirstNonPHI()
+ : MachineBasicBlock::iterator(MI);
+ auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR)
.addReg(R, 0, SR);
switch (ExtOpc) {
case Hexagon::A2_sxtb:
diff --git a/llvm/test/CodeGen/Hexagon/bit-phi.ll b/llvm/test/CodeGen/Hexagon/bit-phi.ll
index 86b18d8bf25..7abfba079bb 100644
--- a/llvm/test/CodeGen/Hexagon/bit-phi.ll
+++ b/llvm/test/CodeGen/Hexagon/bit-phi.ll
@@ -1,4 +1,5 @@
; RUN: llc -march=hexagon < %s
+; RUN: llc -march=hexagon -disable-hcp < %s
; REQUIRES: asserts
target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
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