1 files changed, 3 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td
index 2bae818cfcd..872577787ac 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver1.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td
@@ -21,12 +21,6 @@ def Znver1Model : SchedMachineModel {
   let MispredictPenalty = 17;
   let HighLatency = 25;
   let PostRAScheduler = 1;
-
-  // FIXME: This variable is required for incomplete model.
-  // We haven't catered all instructions.
-  // So, we reset the value of this variable so as to
-  // say that the model is incomplete.
-  let CompleteModel = 0;
 }
 
 let SchedModel = Znver1Model in {
@@ -140,6 +134,9 @@ defm : ZnWriteResPair<WriteALU,   ZnALU, 1>;
 defm : ZnWriteResPair<WriteShift, ZnALU, 1>;
 defm : ZnWriteResPair<WriteJump,  ZnALU, 1>;
 
+// Treat misc copies as a move.
+def : InstRW<[WriteMove], (instrs COPY)>;
+
 // IDIV
 def : WriteRes<WriteIDiv, [ZnALU2, ZnDivider]> {
   let Latency = 41;