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-rw-r--r--llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp7
-rw-r--r--llvm/lib/Target/AArch64/AArch64InstrInfo.cpp19
-rw-r--r--llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp2
-rw-r--r--llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp23
-rw-r--r--llvm/lib/Transforms/Scalar/CallSiteSplitting.cpp7
-rw-r--r--llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp2
-rw-r--r--llvm/tools/llvm-exegesis/lib/Analysis.cpp10
-rw-r--r--llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp2
-rw-r--r--llvm/tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp13
-rw-r--r--llvm/utils/TableGen/AsmMatcherEmitter.cpp7
10 files changed, 40 insertions, 52 deletions
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
index af51d276634..19c350afbf1 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
@@ -254,10 +254,9 @@ bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
// Don't emit locations that cannot be expressed without DW_OP_stack_value.
if (DwarfVersion < 4)
- if (std::any_of(ExprCursor.begin(), ExprCursor.end(),
- [](DIExpression::ExprOperand Op) -> bool {
- return Op.getOp() == dwarf::DW_OP_stack_value;
- })) {
+ if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
+ return Op.getOp() == dwarf::DW_OP_stack_value;
+ })) {
DwarfRegs.clear();
LocationKind = Unknown;
return false;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index f0f5bfa351d..2452d6a0298 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -5084,12 +5084,9 @@ AArch64InstrInfo::getOutliningCandidateInfo(
unsigned FrameID = MachineOutlinerDefault;
unsigned NumBytesToCreateFrame = 4;
- bool HasBTI =
- std::any_of(RepeatedSequenceLocs.begin(), RepeatedSequenceLocs.end(),
- [](outliner::Candidate &C) {
- return C.getMF()->getFunction().hasFnAttribute(
- "branch-target-enforcement");
- });
+ bool HasBTI = any_of(RepeatedSequenceLocs, [](outliner::Candidate &C) {
+ return C.getMF()->getFunction().hasFnAttribute("branch-target-enforcement");
+ });
// If the last instruction in any candidate is a terminator, then we should
// tail call all of the candidates.
@@ -5124,10 +5121,9 @@ AArch64InstrInfo::getOutliningCandidateInfo(
// LR is live, so we need to save it. Decide whether it should be saved to
// the stack, or if it can be saved to a register.
else {
- if (std::all_of(RepeatedSequenceLocs.begin(), RepeatedSequenceLocs.end(),
- [this](outliner::Candidate &C) {
- return findRegisterToSaveLRTo(C);
- })) {
+ if (all_of(RepeatedSequenceLocs, [this](outliner::Candidate &C) {
+ return findRegisterToSaveLRTo(C);
+ })) {
// Every candidate has an available callee-saved register for the save.
// We can save LR to a register.
FrameID = MachineOutlinerRegSave;
@@ -5195,8 +5191,7 @@ AArch64InstrInfo::getMachineOutlinerMBBFlags(MachineBasicBlock &MBB) const {
unsigned Flags = 0x0;
// Check if there's a call inside this MachineBasicBlock. If there is, then
// set a flag.
- if (std::any_of(MBB.begin(), MBB.end(),
- [](MachineInstr &MI) { return MI.isCall(); }))
+ if (any_of(MBB, [](MachineInstr &MI) { return MI.isCall(); }))
Flags |= MachineOutlinerMBBFlags::HasCalls;
// Check if LR is available through all of the MBB. If it's not, then set
diff --git a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
index f38992bef69..702d68fad9b 100644
--- a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
@@ -2360,7 +2360,7 @@ bool HexagonLoopIdiomRecognize::runOnLoopBlock(Loop *CurLoop, BasicBlock *BB,
auto DominatedByBB = [this,BB] (BasicBlock *EB) -> bool {
return DT->dominates(BB, EB);
};
- if (!std::all_of(ExitBlocks.begin(), ExitBlocks.end(), DominatedByBB))
+ if (!all_of(ExitBlocks, DominatedByBB))
return false;
bool MadeChange = false;
diff --git a/llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp b/llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp
index 94745094c15..a71ebdcd346 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp
@@ -211,23 +211,20 @@ Instruction *InstCombiner::FoldIntegerTypedPHI(PHINode &PN) {
}
// If it requires a conversion for every PHI operand, do not do it.
- if (std::all_of(AvailablePtrVals.begin(), AvailablePtrVals.end(),
- [&](Value *V) {
- return (V->getType() != IntToPtr->getType()) ||
- isa<IntToPtrInst>(V);
- }))
+ if (all_of(AvailablePtrVals, [&](Value *V) {
+ return (V->getType() != IntToPtr->getType()) || isa<IntToPtrInst>(V);
+ }))
return nullptr;
// If any of the operand that requires casting is a terminator
// instruction, do not do it.
- if (std::any_of(AvailablePtrVals.begin(), AvailablePtrVals.end(),
- [&](Value *V) {
- if (V->getType() == IntToPtr->getType())
- return false;
-
- auto *Inst = dyn_cast<Instruction>(V);
- return Inst && Inst->isTerminator();
- }))
+ if (any_of(AvailablePtrVals, [&](Value *V) {
+ if (V->getType() == IntToPtr->getType())
+ return false;
+
+ auto *Inst = dyn_cast<Instruction>(V);
+ return Inst && Inst->isTerminator();
+ }))
return nullptr;
PHINode *NewPtrPHI = PHINode::Create(
diff --git a/llvm/lib/Transforms/Scalar/CallSiteSplitting.cpp b/llvm/lib/Transforms/Scalar/CallSiteSplitting.cpp
index e82682e08ab..bac6ef99f03 100644
--- a/llvm/lib/Transforms/Scalar/CallSiteSplitting.cpp
+++ b/llvm/lib/Transforms/Scalar/CallSiteSplitting.cpp
@@ -461,10 +461,9 @@ static bool tryToSplitOnPredicatedArgument(CallSite CS, DominatorTree *DT) {
PredsCS.push_back({Pred, Conditions});
}
- if (std::all_of(PredsCS.begin(), PredsCS.end(),
- [](const std::pair<BasicBlock *, ConditionsTy> &P) {
- return P.second.empty();
- }))
+ if (all_of(PredsCS, [](const std::pair<BasicBlock *, ConditionsTy> &P) {
+ return P.second.empty();
+ }))
return false;
splitCallSite(CS, PredsCS, DT);
diff --git a/llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp b/llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
index 42992641eb7..af21a41a108 100644
--- a/llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
+++ b/llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
@@ -624,7 +624,7 @@ int main(int argc, char **argv) {
if (Verify) {
// If we encountered errors during verify, exit with a non-zero exit status.
- if (!std::all_of(Objects.begin(), Objects.end(), [&](std::string Object) {
+ if (!all_of(Objects, [&](std::string Object) {
return handleFile(Object, verifyObjectFile, OS);
}))
exit(1);
diff --git a/llvm/tools/llvm-exegesis/lib/Analysis.cpp b/llvm/tools/llvm-exegesis/lib/Analysis.cpp
index eaacb5b1d65..73c54f53225 100644
--- a/llvm/tools/llvm-exegesis/lib/Analysis.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Analysis.cpp
@@ -657,11 +657,11 @@ llvm::Error Analysis::run<Analysis::PrintSchedClassInconsistencies>(
// Print any scheduling class that has at least one cluster that does not
// match the checked-in data.
- if (std::all_of(SchedClassClusters.begin(), SchedClassClusters.end(),
- [this, &RSCAndPoints](const SchedClassCluster &C) {
- return C.measurementsMatch(*SubtargetInfo_,
- RSCAndPoints.RSC, Clustering_);
- }))
+ if (llvm::all_of(SchedClassClusters,
+ [this, &RSCAndPoints](const SchedClassCluster &C) {
+ return C.measurementsMatch(
+ *SubtargetInfo_, RSCAndPoints.RSC, Clustering_);
+ }))
continue; // Nothing weird.
OS << "<div class=\"inconsistency\"><p>Sched Class <span "
diff --git a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
index 59f56520efc..6fdb5a68419 100644
--- a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
+++ b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
@@ -174,7 +174,7 @@ const Operand &Instruction::getPrimaryOperand(const Variable &Var) const {
}
bool Instruction::hasMemoryOperands() const {
- return std::any_of(Operands.begin(), Operands.end(), [](const Operand &Op) {
+ return any_of(Operands, [](const Operand &Op) {
return Op.isReg() && Op.isExplicit() && Op.isMemory();
});
}
diff --git a/llvm/tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp b/llvm/tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp
index 46a374c2102..bb6ed309c26 100644
--- a/llvm/tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp
+++ b/llvm/tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp
@@ -218,13 +218,12 @@ void ResourceManager::releaseBuffers(ArrayRef<uint64_t> Buffers) {
}
bool ResourceManager::canBeIssued(const InstrDesc &Desc) const {
- return std::all_of(Desc.Resources.begin(), Desc.Resources.end(),
- [&](const std::pair<uint64_t, const ResourceUsage> &E) {
- unsigned NumUnits =
- E.second.isReserved() ? 0U : E.second.NumUnits;
- unsigned Index = getResourceStateIndex(E.first);
- return Resources[Index]->isReady(NumUnits);
- });
+ return all_of(
+ Desc.Resources, [&](const std::pair<uint64_t, const ResourceUsage> &E) {
+ unsigned NumUnits = E.second.isReserved() ? 0U : E.second.NumUnits;
+ unsigned Index = getResourceStateIndex(E.first);
+ return Resources[Index]->isReady(NumUnits);
+ });
}
// Returns true if all resources are in-order, and there is at least one
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index e808661b7a5..5b4229e6468 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -2415,10 +2415,9 @@ static void emitOperandMatchErrorDiagStrings(AsmMatcherInfo &Info, raw_ostream &
static void emitRegisterMatchErrorFunc(AsmMatcherInfo &Info, raw_ostream &OS) {
OS << "static unsigned getDiagKindFromRegisterClass(MatchClassKind "
"RegisterClass) {\n";
- if (std::none_of(Info.Classes.begin(), Info.Classes.end(),
- [](const ClassInfo &CI) {
- return CI.isRegisterClass() && !CI.DiagnosticType.empty();
- })) {
+ if (none_of(Info.Classes, [](const ClassInfo &CI) {
+ return CI.isRegisterClass() && !CI.DiagnosticType.empty();
+ })) {
OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
} else {
OS << " switch (RegisterClass) {\n";
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