diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64FastISel.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll | 131 |
2 files changed, 136 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index 9ac7ecb9cdb..e8fcf1a0e9b 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -2827,7 +2827,7 @@ bool AArch64FastISel::selectFPToInt(const Instruction *I, bool Signed) { return false; EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true); - if (SrcVT == MVT::f128) + if (SrcVT == MVT::f128 || SrcVT == MVT::f16) return false; unsigned Opc; @@ -2854,6 +2854,10 @@ bool AArch64FastISel::selectIntToFP(const Instruction *I, bool Signed) { MVT DestVT; if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector()) return false; + // Let regular ISEL handle FP16 + if (DestVT == MVT::f16) + return false; + assert((DestVT == MVT::f32 || DestVT == MVT::f64) && "Unexpected value type."); diff --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll b/llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll new file mode 100644 index 00000000000..16a02de79a9 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll @@ -0,0 +1,131 @@ +; RUN: llc -O0 -verify-machineinstrs -mtriple=arm64-eabi < %s | FileCheck --enable-var-scope %s + +; Test fptosi +define i32 @fptosi_wh(half %a) nounwind ssp { +entry: +; CHECK-LABEL: fptosi_wh +; CHECK: fcvt s1, h0 +; CHECK: fcvtzs [[REG:w[0-9]+]], s1 +; CHECK: mov w0, [[REG]] + %conv = fptosi half %a to i32 + ret i32 %conv +} + +; Test fptoui +define i32 @fptoui_swh(half %a) nounwind ssp { +entry: +; CHECK-LABEL: fptoui_swh +; CHECK: fcvt s1, h0 +; CHECK: fcvtzu [[REG:w[0-9]+]], s1 +; CHECK: mov w0, [[REG]] + %conv = fptoui half %a to i32 + ret i32 %conv +} + +; Test sitofp +define half @sitofp_hw_i1(i1 %a) nounwind ssp { +entry: +; CHECK-LABEL: sitofp_hw_i1 +; CHECK: sbfx w0, w0, #0, #1 +; CHECK: scvtf s0, w0 +; CHECK: fcvt h0, s0 + %conv = sitofp i1 %a to half + ret half %conv +} + +; Test sitofp +define half @sitofp_hw_i8(i8 %a) nounwind ssp { +entry: +; CHECK-LABEL: sitofp_hw_i8 +; CHECK: sxtb w0, w0 +; CHECK: scvtf s0, w0 +; CHECK: fcvt h0, s0 + %conv = sitofp i8 %a to half + ret half %conv +} + +; Test sitofp +define half @sitofp_hw_i16(i16 %a) nounwind ssp { +entry: +; CHECK-LABEL: sitofp_hw_i16 +; CHECK: sxth w0, w0 +; CHECK: scvtf s0, w0 +; CHECK: fcvt h0, s0 + %conv = sitofp i16 %a to half + ret half %conv +} + +; Test sitofp +define half @sitofp_hw_i32(i32 %a) nounwind ssp { +entry: +; CHECK-LABEL: sitofp_hw_i32 +; CHECK: scvtf s0, w0 +; CHECK: fcvt h0, s0 + %conv = sitofp i32 %a to half + ret half %conv +} + +; Test sitofp +define half @sitofp_hx(i64 %a) nounwind ssp { +entry: +; CHECK-LABEL: sitofp_hx +; CHECK: scvtf s0, x0 +; CHECK: fcvt h0, s0 + %conv = sitofp i64 %a to half + ret half %conv +} + +; Test uitofp +define half @uitofp_hw_i1(i1 %a) nounwind ssp { +entry: +; CHECK-LABEL: uitofp_hw_i1 +; CHECK: and w0, w0, #0x1 +; CHECK: ucvtf s0, w0 +; CHECK: fcvt h0, s0 + %conv = uitofp i1 %a to half + ret half %conv +} + +; Test uitofp +define half @uitofp_hw_i8(i8 %a) nounwind ssp { +entry: +; CHECK-LABEL: uitofp_hw_i8 +; CHECK: and w0, w0, #0xff +; CHECK: ucvtf s0, w0 +; CHECK: fcvt h0, s0 + %conv = uitofp i8 %a to half + ret half %conv +} + +; Test uitofp +define half @uitofp_hw_i16(i16 %a) nounwind ssp { +entry: +; CHECK-LABEL: uitofp_hw_i16 +; CHECK: and w0, w0, #0xffff +; CHECK: ucvtf s0, w0 +; CHECK: fcvt h0, s0 + %conv = uitofp i16 %a to half + ret half %conv +} + +; Test uitofp +define half @uitofp_hw_i32(i32 %a) nounwind ssp { +entry: +; CHECK-LABEL: uitofp_hw_i32 +; CHECK: ucvtf s0, w0 +; CHECK: fcvt h0, s0 + %conv = uitofp i32 %a to half + ret half %conv +} + +; Test uitofp +define half @uitofp_hx(i64 %a) nounwind ssp { +entry: +; CHECK-LABEL: uitofp_hx +; CHECK: ucvtf s0, x0 +; CHECK: fcvt h0, s0 + %conv = uitofp i64 %a to half + ret half %conv +} + + |
