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-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp4
-rw-r--r--llvm/test/Transforms/LoopVectorize/AMDGPU/lit.local.cfg2
-rw-r--r--llvm/test/Transforms/LoopVectorize/AMDGPU/unroll-in-loop-vectorizer.ll28
3 files changed, 34 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index a780a76c86a..4a6d12bd883 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -155,6 +155,10 @@ bool AMDGPUTTIImpl::isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
}
unsigned AMDGPUTTIImpl::getMaxInterleaveFactor(unsigned VF) {
+ // Disable unrolling if the loop is not vectorized.
+ if (VF == 1)
+ return 1;
+
// Semi-arbitrary large amount.
return 64;
}
diff --git a/llvm/test/Transforms/LoopVectorize/AMDGPU/lit.local.cfg b/llvm/test/Transforms/LoopVectorize/AMDGPU/lit.local.cfg
new file mode 100644
index 00000000000..2a665f06be7
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/AMDGPU/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'AMDGPU' in config.root.targets:
+ config.unsupported = True
diff --git a/llvm/test/Transforms/LoopVectorize/AMDGPU/unroll-in-loop-vectorizer.ll b/llvm/test/Transforms/LoopVectorize/AMDGPU/unroll-in-loop-vectorizer.ll
new file mode 100644
index 00000000000..85ba95cab16
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/AMDGPU/unroll-in-loop-vectorizer.ll
@@ -0,0 +1,28 @@
+; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=fiji -loop-vectorize < %s | FileCheck %s
+
+
+; For AMDGPU, loop unroll in loop vectorizer is disabled when VF==1.
+;
+; CHECK-LABEL: @small_loop(
+; CHECK: store i32
+; CHECK-NOT: store i32
+; CHECK: ret
+define void @small_loop(i32* nocapture %inArray, i32 %size) nounwind {
+entry:
+ %0 = icmp sgt i32 %size, 0
+ br i1 %0, label %loop, label %exit
+
+loop: ; preds = %entry, %loop
+ %iv = phi i32 [ %iv1, %loop ], [ 0, %entry ]
+ %1 = getelementptr inbounds i32, i32* %inArray, i32 %iv
+ %2 = load i32, i32* %1, align 4
+ %3 = add nsw i32 %2, 6
+ store i32 %3, i32* %1, align 4
+ %iv1 = add i32 %iv, 1
+; %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+ %cond = icmp eq i32 %iv1, %size
+ br i1 %cond, label %exit, label %loop
+
+exit: ; preds = %loop, %entry
+ ret void
+}
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