diff options
Diffstat (limited to 'llvm')
22 files changed, 79 insertions, 3 deletions
diff --git a/llvm/include/llvm/Target/TargetSchedule.td b/llvm/include/llvm/Target/TargetSchedule.td index d08595fe147..5ad3aeadb77 100644 --- a/llvm/include/llvm/Target/TargetSchedule.td +++ b/llvm/include/llvm/Target/TargetSchedule.td @@ -104,6 +104,7 @@ class SchedMachineModel { def NoSchedModel : SchedMachineModel { let NoModel = 1; + let CompleteModel = 0; } // Define a kind of processor resource that may be common across diff --git a/llvm/lib/Target/AArch64/AArch64SchedA53.td b/llvm/lib/Target/AArch64/AArch64SchedA53.td index d709bee7b9e..ad5505b7818 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedA53.td +++ b/llvm/lib/Target/AArch64/AArch64SchedA53.td @@ -26,6 +26,7 @@ def CortexA53Model : SchedMachineModel { let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation // Specification - Instruction Timings" // v 1.0 Spreadsheet + let CompleteModel = 0; } diff --git a/llvm/lib/Target/AArch64/AArch64SchedA57.td b/llvm/lib/Target/AArch64/AArch64SchedA57.td index ca4457af852..4b3a9b0a9b2 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedA57.td +++ b/llvm/lib/Target/AArch64/AArch64SchedA57.td @@ -30,6 +30,7 @@ def CortexA57Model : SchedMachineModel { // Enable partial & runtime unrolling. The magic number is chosen based on // experiments and benchmarking data. let LoopMicroOpBufferSize = 16; + let CompleteModel = 0; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64SchedCyclone.td b/llvm/lib/Target/AArch64/AArch64SchedCyclone.td index 419169cf6ab..21e2bc2cb8b 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedCyclone.td +++ b/llvm/lib/Target/AArch64/AArch64SchedCyclone.td @@ -17,6 +17,7 @@ def CycloneModel : SchedMachineModel { let MicroOpBufferSize = 192; // Based on the reorder buffer. let LoadLatency = 4; // Optimistic load latency. let MispredictPenalty = 16; // 14-19 cycles are typical. + let CompleteModel = 0; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64SchedKryo.td b/llvm/lib/Target/AArch64/AArch64SchedKryo.td index 347104aa90f..dc01199b328 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedKryo.td +++ b/llvm/lib/Target/AArch64/AArch64SchedKryo.td @@ -26,6 +26,7 @@ def KryoModel : SchedMachineModel { // Enable partial & runtime unrolling. The magic number is chosen based on // experiments and benchmarking data. let LoopMicroOpBufferSize = 16; + let CompleteModel = 0; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/SISchedule.td b/llvm/lib/Target/AMDGPU/SISchedule.td index cd77e519abb..40b37c4593b 100644 --- a/llvm/lib/Target/AMDGPU/SISchedule.td +++ b/llvm/lib/Target/AMDGPU/SISchedule.td @@ -39,8 +39,12 @@ def Write64Bit : SchedWrite; // instructions and have VALU rates, but write to the SALU (i.e. VOPC // instructions) -def SIFullSpeedModel : SchedMachineModel; -def SIQuarterSpeedModel : SchedMachineModel; +def SIFullSpeedModel : SchedMachineModel { + let CompleteModel = 0; +} +def SIQuarterSpeedModel : SchedMachineModel { + let CompleteModel = 0; +} // BufferSize = 0 means the processors are in-order. let BufferSize = 0 in { diff --git a/llvm/lib/Target/ARM/ARMScheduleA8.td b/llvm/lib/Target/ARM/ARMScheduleA8.td index 2c6382542ab..154a889b41a 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA8.td +++ b/llvm/lib/Target/ARM/ARMScheduleA8.td @@ -1070,6 +1070,7 @@ def CortexA8Model : SchedMachineModel { // This is overriden by OperandCycles if the // Itineraries are queried instead. let MispredictPenalty = 13; // Based on estimate of pipeline depth. + let CompleteModel = 0; let Itineraries = CortexA8Itineraries; } diff --git a/llvm/lib/Target/Hexagon/HexagonScheduleV4.td b/llvm/lib/Target/Hexagon/HexagonScheduleV4.td index 67af147b25b..0f462c98913 100644 --- a/llvm/lib/Target/Hexagon/HexagonScheduleV4.td +++ b/llvm/lib/Target/Hexagon/HexagonScheduleV4.td @@ -199,6 +199,7 @@ def HexagonModelV4 : SchedMachineModel { let IssueWidth = 4; let Itineraries = HexagonItinerariesV4; let LoadLatency = 1; + let CompleteModel = 0; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Hexagon/HexagonScheduleV55.td b/llvm/lib/Target/Hexagon/HexagonScheduleV55.td index d9ad25d4cd5..2bc4a3db98b 100644 --- a/llvm/lib/Target/Hexagon/HexagonScheduleV55.td +++ b/llvm/lib/Target/Hexagon/HexagonScheduleV55.td @@ -163,6 +163,7 @@ def HexagonModelV55 : SchedMachineModel { let IssueWidth = 4; let Itineraries = HexagonItinerariesV55; let LoadLatency = 1; + let CompleteModel = 0; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Hexagon/HexagonScheduleV60.td b/llvm/lib/Target/Hexagon/HexagonScheduleV60.td index 2ccff8242a4..a92377f7178 100644 --- a/llvm/lib/Target/Hexagon/HexagonScheduleV60.td +++ b/llvm/lib/Target/Hexagon/HexagonScheduleV60.td @@ -303,6 +303,7 @@ def HexagonModelV60 : SchedMachineModel { let IssueWidth = 4; let Itineraries = HexagonItinerariesV60; let LoadLatency = 1; + let CompleteModel = 0; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Mips/MipsScheduleP5600.td b/llvm/lib/Target/Mips/MipsScheduleP5600.td index d32ae4f55ea..cee42873c6e 100644 --- a/llvm/lib/Target/Mips/MipsScheduleP5600.td +++ b/llvm/lib/Target/Mips/MipsScheduleP5600.td @@ -13,7 +13,7 @@ def MipsP5600Model : SchedMachineModel { int LoadLatency = 4; int MispredictPenalty = 8; // TODO: Estimated - let CompleteModel = 1; + let CompleteModel = 0; } let SchedModel = MipsP5600Model in { diff --git a/llvm/lib/Target/PowerPC/PPCSchedule440.td b/llvm/lib/Target/PowerPC/PPCSchedule440.td index 04a43bc0325..e4a2c3b474d 100644 --- a/llvm/lib/Target/PowerPC/PPCSchedule440.td +++ b/llvm/lib/Target/PowerPC/PPCSchedule440.td @@ -602,6 +602,8 @@ def PPC440Model : SchedMachineModel { // This is overriden by OperandCycles if the // Itineraries are queried instead. + let CompleteModel = 0; + let Itineraries = PPC440Itineraries; } diff --git a/llvm/lib/Target/PowerPC/PPCScheduleA2.td b/llvm/lib/Target/PowerPC/PPCScheduleA2.td index 21a357a2efc..9cdfd0b996d 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleA2.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleA2.td @@ -166,6 +166,8 @@ def PPCA2Model : SchedMachineModel { // Itineraries are queried instead. let MispredictPenalty = 13; + let CompleteModel = 0; + let Itineraries = PPCA2Itineraries; } diff --git a/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td b/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td index 36b8517dabf..262c7150800 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td @@ -316,5 +316,7 @@ def PPCE500mcModel : SchedMachineModel { // This is overriden by OperandCycles if the // Itineraries are queried instead. + let CompleteModel = 0; + let Itineraries = PPCE500mcItineraries; } diff --git a/llvm/lib/Target/PowerPC/PPCScheduleE5500.td b/llvm/lib/Target/PowerPC/PPCScheduleE5500.td index 7c2693ef0d4..642a5ae726e 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleE5500.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleE5500.td @@ -376,5 +376,7 @@ def PPCE5500Model : SchedMachineModel { // This is overriden by OperandCycles if the // Itineraries are queried instead. + let CompleteModel = 0; + let Itineraries = PPCE5500Itineraries; } diff --git a/llvm/lib/Target/PowerPC/PPCScheduleG5.td b/llvm/lib/Target/PowerPC/PPCScheduleG5.td index a3b73ab4454..a001b592312 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleG5.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleG5.td @@ -124,6 +124,8 @@ def G5Model : SchedMachineModel { // Itineraries are queried instead. let MispredictPenalty = 16; + let CompleteModel = 0; + let Itineraries = G5Itineraries; } diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP7.td b/llvm/lib/Target/PowerPC/PPCScheduleP7.td index 267f5672618..26c80c92c90 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleP7.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleP7.td @@ -391,6 +391,8 @@ def P7Model : SchedMachineModel { // Try to make sure we have at least 10 dispatch groups in a loop. let LoopMicroOpBufferSize = 40; + let CompleteModel = 0; + let Itineraries = P7Itineraries; } diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP8.td b/llvm/lib/Target/PowerPC/PPCScheduleP8.td index 69e6d05c660..b7083e6bafe 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleP8.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleP8.td @@ -400,6 +400,8 @@ def P8Model : SchedMachineModel { // Try to make sure we have at least 10 dispatch groups in a loop. let LoopMicroOpBufferSize = 60; + let CompleteModel = 0; + let Itineraries = P8Itineraries; } diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td index a261356afe6..46c88c4fcbb 100644 --- a/llvm/lib/Target/X86/X86Schedule.td +++ b/llvm/lib/Target/X86/X86Schedule.td @@ -640,6 +640,7 @@ def GenericModel : SchedMachineModel { let LoadLatency = 4; let HighLatency = 10; let PostRAScheduler = 0; + let CompleteModel = 0; } include "X86ScheduleAtom.td" diff --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td index 4c559c9c179..a5b440182aa 100644 --- a/llvm/lib/Target/X86/X86ScheduleAtom.td +++ b/llvm/lib/Target/X86/X86ScheduleAtom.td @@ -544,6 +544,7 @@ def AtomModel : SchedMachineModel { // simple loops, expand by a small factor to hide the backedge cost. let LoopMicroOpBufferSize = 10; let PostRAScheduler = 1; + let CompleteModel = 0; let Itineraries = AtomItineraries; } diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp index 0bce99636bc..e6e62d0e4ff 100644 --- a/llvm/utils/TableGen/CodeGenSchedule.cpp +++ b/llvm/utils/TableGen/CodeGenSchedule.cpp @@ -126,6 +126,8 @@ CodeGenSchedModels::CodeGenSchedModels(RecordKeeper &RK, // Populate each CodeGenProcModel's WriteResDefs, ReadAdvanceDefs, and // ProcResourceDefs. collectProcResources(); + + checkCompleteness(); } /// Gather all processor models. @@ -1523,6 +1525,49 @@ void CodeGenSchedModels::collectProcResources() { } } +void CodeGenSchedModels::checkCompleteness() { + bool Complete = true; + bool HadCompleteModel = false; + for (const CodeGenProcModel &ProcModel : procModels()) { + // Note that long-term we should check "CompleteModel", but for now most + // models that claim to be complete are actually not so we use a separate + // "CheckCompleteness" bit. + if (!ProcModel.ModelDef->getValueAsBit("CompleteModel")) + continue; + for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) { + if (Inst->hasNoSchedulingInfo) + continue; + unsigned SCIdx = getSchedClassIdx(*Inst); + if (!SCIdx) { + if (Inst->TheDef->isValueUnset("SchedRW") && !HadCompleteModel) { + PrintError("No schedule information for instruction '" + + Inst->TheDef->getName() + "'"); + Complete = false; + } + continue; + } + + const CodeGenSchedClass &SC = getSchedClass(SCIdx); + if (!SC.Writes.empty()) + continue; + + const RecVec &InstRWs = SC.InstRWs; + auto I = std::find_if(InstRWs.begin(), InstRWs.end(), + [&ProcModel] (const Record *R) { + return R->getValueAsDef("SchedModel") == ProcModel.ModelDef; + }); + if (I == InstRWs.end()) { + PrintError("'" + ProcModel.ModelName + "' lacks information for '" + + Inst->TheDef->getName() + "'"); + Complete = false; + } + } + HadCompleteModel = true; + } + if (!Complete) + PrintFatalError("Incomplete schedule model"); +} + // Collect itinerary class resources for each processor. void CodeGenSchedModels::collectItinProcResources(Record *ItinClassDef) { for (unsigned PIdx = 0, PEnd = ProcModels.size(); PIdx != PEnd; ++PIdx) { diff --git a/llvm/utils/TableGen/CodeGenSchedule.h b/llvm/utils/TableGen/CodeGenSchedule.h index 92c4e97b387..62601d941bc 100644 --- a/llvm/utils/TableGen/CodeGenSchedule.h +++ b/llvm/utils/TableGen/CodeGenSchedule.h @@ -401,6 +401,8 @@ private: void inferSchedClasses(); + void checkCompleteness(); + void inferFromRW(ArrayRef<unsigned> OperWrites, ArrayRef<unsigned> OperReads, unsigned FromClassIdx, ArrayRef<unsigned> ProcIndices); void inferFromItinClass(Record *ItinClassDef, unsigned FromClassIdx); |
