summaryrefslogtreecommitdiffstats
path: root/llvm
diff options
context:
space:
mode:
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/ARM/ARMParallelDSP.cpp9
1 files changed, 0 insertions, 9 deletions
diff --git a/llvm/lib/Target/ARM/ARMParallelDSP.cpp b/llvm/lib/Target/ARM/ARMParallelDSP.cpp
index 0e48ba4c7a4..7b357193f71 100644
--- a/llvm/lib/Target/ARM/ARMParallelDSP.cpp
+++ b/llvm/lib/Target/ARM/ARMParallelDSP.cpp
@@ -64,7 +64,6 @@ namespace {
struct BinOpChain {
Instruction *Root;
ValueList AllValues;
- MemInstList Loads;
MemInstList VecLd; // List of all load instructions.
ValueList LHS; // List of all (narrow) left hand operands.
ValueList RHS; // List of all (narrow) right hand operands.
@@ -79,13 +78,6 @@ namespace {
AllValues.push_back(V);
}
- void PopulateLoads() {
- for (auto *V : AllValues) {
- if (auto *Ld = dyn_cast<LoadInst>(V))
- Loads.push_back(Ld);
- }
- }
-
unsigned size() const { return AllValues.size(); }
bool AreSymmetrical(BinOpChain *Other);
@@ -563,7 +555,6 @@ bool ARMParallelDSP::CreateParallelPairs(Reduction &R) {
LLVM_DEBUG(dbgs() << "Operand list too short.\n");
return false;
}
- MulChain->PopulateLoads();
ValueList &LHS = static_cast<BinOpChain*>(MulChain.get())->LHS;
ValueList &RHS = static_cast<BinOpChain*>(MulChain.get())->RHS;
OpenPOWER on IntegriCloud