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-rw-r--r--llvm/utils/TableGen/CodeGenRegisters.cpp64
-rw-r--r--llvm/utils/TableGen/CodeGenRegisters.h15
-rw-r--r--llvm/utils/TableGen/RegisterInfoEmitter.cpp60
3 files changed, 73 insertions, 66 deletions
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index 6ce25fa6475..b137b3cc2e5 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -51,7 +51,7 @@ using namespace llvm;
//===----------------------------------------------------------------------===//
CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum)
- : TheDef(R), EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) {
+ : TheDef(R), EnumValue(Enum), AllSuperRegsCovered(true) {
Name = R->getName();
if (R->getValue("Namespace"))
Namespace = R->getValueAsString("Namespace");
@@ -62,7 +62,7 @@ CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum)
CodeGenSubRegIndex::CodeGenSubRegIndex(StringRef N, StringRef Nspace,
unsigned Enum)
: TheDef(nullptr), Name(N), Namespace(Nspace), Size(-1), Offset(-1),
- EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) {
+ EnumValue(Enum), AllSuperRegsCovered(true) {
}
std::string CodeGenSubRegIndex::getQualifiedName() const {
@@ -102,19 +102,19 @@ void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
}
}
-unsigned CodeGenSubRegIndex::computeLaneMask() const {
+LaneBitmask CodeGenSubRegIndex::computeLaneMask() const {
// Already computed?
- if (LaneMask)
+ if (!LaneMask.none())
return LaneMask;
// Recursion guard, shouldn't be required.
- LaneMask = ~0u;
+ LaneMask = LaneBitmask::getAll();
// The lane mask is simply the union of all sub-indices.
- unsigned M = 0;
+ LaneBitmask M;
for (const auto &C : Composed)
M |= C.second->computeLaneMask();
- assert(M && "Missing lane mask, sub-register cycle?");
+ assert(!M.none() && "Missing lane mask, sub-register cycle?");
LaneMask = M;
return LaneMask;
}
@@ -678,8 +678,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
: TheDef(R),
Name(R->getName()),
TopoSigs(RegBank.getNumTopoSigs()),
- EnumValue(-1),
- LaneMask(0) {
+ EnumValue(-1) {
// Rename anonymous register classes.
if (R->getName().size() > 9 && R->getName()[9] == '.') {
static unsigned AnonCounter = 0;
@@ -1193,7 +1192,7 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
// First assign individual bits to all the leaf indices.
unsigned Bit = 0;
// Determine mask of lanes that cover their registers.
- CoveringLanes = ~0u;
+ CoveringLanes = LaneBitmask::getAll();
for (auto &Idx : SubRegIndices) {
if (Idx.getComposites().empty()) {
if (Bit > 32) {
@@ -1201,10 +1200,10 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
Twine("Ran out of lanemask bits to represent subregister ")
+ Idx.getName());
}
- Idx.LaneMask = 1u << Bit;
+ Idx.LaneMask = LaneBitmask(1 << Bit);
++Bit;
} else {
- Idx.LaneMask = 0;
+ Idx.LaneMask = LaneBitmask::getNone();
}
}
@@ -1223,9 +1222,12 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
// Moving from a class with no subregisters we just had a single lane:
// The subregister must be a leaf subregister and only occupies 1 bit.
// Move the bit from the class without subregisters into that position.
- unsigned DstBit = Log2_32(Idx.LaneMask);
- assert(Idx.LaneMask == 1u << DstBit && "Must be a leaf subregister");
- MaskRolPair MaskRol = { 1, (uint8_t)DstBit };
+ static_assert(sizeof(Idx.LaneMask.getAsInteger()) == 4,
+ "Change Log2_32 to a proper one");
+ unsigned DstBit = Log2_32(Idx.LaneMask.getAsInteger());
+ assert(Idx.LaneMask == LaneBitmask(1 << DstBit) &&
+ "Must be a leaf subregister");
+ MaskRolPair MaskRol = { LaneBitmask(1), (uint8_t)DstBit };
LaneTransforms.push_back(MaskRol);
} else {
// Go through all leaf subregisters and find the ones that compose with
@@ -1239,8 +1241,8 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
continue;
// Replicate the behaviour from the lane mask generation loop above.
unsigned SrcBit = NextBit;
- unsigned SrcMask = 1u << SrcBit;
- if (NextBit < 31)
+ LaneBitmask SrcMask = LaneBitmask(1 << SrcBit);
+ if (NextBit < LaneBitmask::BitWidth-1)
++NextBit;
assert(Idx2.LaneMask == SrcMask);
@@ -1253,16 +1255,19 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
assert(Composite->getComposites().empty());
// Create Mask+Rotate operation and merge with existing ops if possible.
- unsigned DstBit = Log2_32(Composite->LaneMask);
+ static_assert(sizeof(Composite->LaneMask.getAsInteger()) == 4,
+ "Change Log2_32 to a proper one");
+ unsigned DstBit = Log2_32(Composite->LaneMask.getAsInteger());
int Shift = DstBit - SrcBit;
- uint8_t RotateLeft = Shift >= 0 ? (uint8_t)Shift : 32+Shift;
+ uint8_t RotateLeft = Shift >= 0 ? (uint8_t)Shift
+ : LaneBitmask::BitWidth + Shift;
for (auto &I : LaneTransforms) {
if (I.RotateLeft == RotateLeft) {
I.Mask |= SrcMask;
- SrcMask = 0;
+ SrcMask = LaneBitmask::getNone();
}
}
- if (SrcMask != 0) {
+ if (!SrcMask.none()) {
MaskRolPair MaskRol = { SrcMask, RotateLeft };
LaneTransforms.push_back(MaskRol);
}
@@ -1273,13 +1278,13 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
// 0xffffffff (including some irrelevant invalid bits) so that it should
// merge with more entries later while compressing the table.
if (LaneTransforms.size() == 1)
- LaneTransforms[0].Mask = ~0u;
+ LaneTransforms[0].Mask = LaneBitmask::getAll();
// Further compression optimization: For invalid compositions resulting
// in a sequence with 0 entries we can just pick any other. Choose
// Mask 0xffffffff with Rotation 0.
if (LaneTransforms.size() == 0) {
- MaskRolPair P = { ~0u, 0 };
+ MaskRolPair P = { LaneBitmask::getAll(), 0 };
LaneTransforms.push_back(P);
}
}
@@ -1289,7 +1294,7 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
// Inherit lanes from composites.
for (const auto &Idx : SubRegIndices) {
- unsigned Mask = Idx.computeLaneMask();
+ LaneBitmask Mask = Idx.computeLaneMask();
// If some super-registers without CoveredBySubRegs use this index, we can
// no longer assume that the lanes are covering their registers.
if (!Idx.AllSuperRegsCovered)
@@ -1298,7 +1303,7 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
// Compute lane mask combinations for register classes.
for (auto &RegClass : RegClasses) {
- unsigned LaneMask = 0;
+ LaneBitmask LaneMask;
for (const auto &SubRegIndex : SubRegIndices) {
if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr)
continue;
@@ -1307,8 +1312,8 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
// For classes without any subregisters set LaneMask to 1 instead of 0.
// This makes it easier for client code to handle classes uniformly.
- if (LaneMask == 0)
- LaneMask = 1;
+ if (LaneMask.none())
+ LaneMask = LaneBitmask(1);
RegClass.LaneMask = LaneMask;
}
@@ -1807,7 +1812,8 @@ void CodeGenRegBank::computeRegUnitLaneMasks() {
for (auto &Register : Registers) {
// Create an initial lane mask for all register units.
const auto &RegUnits = Register.getRegUnits();
- CodeGenRegister::RegUnitLaneMaskList RegUnitLaneMasks(RegUnits.count(), 0);
+ CodeGenRegister::RegUnitLaneMaskList
+ RegUnitLaneMasks(RegUnits.count(), LaneBitmask::getNone());
// Iterate through SubRegisters.
typedef CodeGenRegister::SubRegMap SubRegMap;
const SubRegMap &SubRegs = Register.getSubRegs();
@@ -1820,7 +1826,7 @@ void CodeGenRegBank::computeRegUnitLaneMasks() {
continue;
CodeGenSubRegIndex *SubRegIndex = S->first;
const CodeGenRegister *SubRegister = S->second;
- unsigned LaneMask = SubRegIndex->LaneMask;
+ LaneBitmask LaneMask = SubRegIndex->LaneMask;
// Distribute LaneMask to Register Units touched.
for (unsigned SUI : SubRegister->getRegUnits()) {
bool Found = false;
diff --git a/llvm/utils/TableGen/CodeGenRegisters.h b/llvm/utils/TableGen/CodeGenRegisters.h
index 7ef3d8b8413..3ed26fa401a 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/CodeGenRegisters.h
@@ -26,6 +26,7 @@
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/MC/LaneBitmask.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/SetTheory.h"
@@ -47,7 +48,7 @@ namespace llvm {
/// Mask the bits specified in Mask, then rotate them Rol bits to the left
/// assuming a wraparound at 32bits.
struct MaskRolPair {
- unsigned Mask;
+ LaneBitmask Mask;
uint8_t RotateLeft;
bool operator==(const MaskRolPair Other) const {
@@ -68,7 +69,7 @@ namespace llvm {
uint16_t Size;
uint16_t Offset;
const unsigned EnumValue;
- mutable unsigned LaneMask;
+ mutable LaneBitmask LaneMask;
mutable SmallVector<MaskRolPair,1> CompositionLaneMaskTransform;
// Are all super-registers containing this SubRegIndex covered by their
@@ -120,7 +121,7 @@ namespace llvm {
const CompMap &getComposites() const { return Composed; }
// Compute LaneMask from Composed. Return LaneMask.
- unsigned computeLaneMask() const;
+ LaneBitmask computeLaneMask() const;
private:
CompMap Composed;
@@ -206,7 +207,7 @@ namespace llvm {
// List of register units in ascending order.
typedef SparseBitVector<> RegUnitList;
- typedef SmallVector<unsigned, 16> RegUnitLaneMaskList;
+ typedef SmallVector<LaneBitmask, 16> RegUnitLaneMaskList;
// How many entries in RegUnitList are native?
RegUnitList NativeRegUnits;
@@ -215,7 +216,7 @@ namespace llvm {
// This is only valid after computeSubRegs() completes.
const RegUnitList &getRegUnits() const { return RegUnits; }
- ArrayRef<unsigned> getRegUnitLaneMasks() const {
+ ArrayRef<LaneBitmask> getRegUnitLaneMasks() const {
return makeArrayRef(RegUnitLaneMasks).slice(0, NativeRegUnits.count());
}
@@ -316,7 +317,7 @@ namespace llvm {
std::string AltOrderSelect;
uint8_t AllocationPriority;
/// Contains the combination of the lane masks of all subregisters.
- unsigned LaneMask;
+ LaneBitmask LaneMask;
/// True if there are at least 2 subregisters which do not interfere.
bool HasDisjunctSubRegs;
bool CoveredBySubRegs;
@@ -733,7 +734,7 @@ namespace llvm {
// Bit mask of lanes that cover their registers. A sub-register index whose
// LaneMask is contained in CoveringLanes will be completely covered by
// another sub-register with the same or larger lane mask.
- unsigned CoveringLanes;
+ LaneBitmask CoveringLanes;
};
} // end namespace llvm
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 6d9324a7e77..73ac332261d 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -578,7 +578,7 @@ static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
// 0 differential which means we can't encode repeated elements.
typedef SmallVector<uint16_t, 4> DiffVec;
-typedef SmallVector<unsigned, 4> MaskVec;
+typedef SmallVector<LaneBitmask, 4> MaskVec;
// Differentially encode a sequence of numbers into V. The starting value and
// terminating 0 are not added to V, so it will have the same size as List.
@@ -611,8 +611,8 @@ static void printDiff16(raw_ostream &OS, uint16_t Val) {
OS << Val;
}
-static void printMask(raw_ostream &OS, unsigned Val) {
- OS << format("0x%08X", Val);
+static void printMask(raw_ostream &OS, LaneBitmask Val) {
+ OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')';
}
// Try to combine Idx's compose map into Vec if it is compatible.
@@ -739,7 +739,7 @@ RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS,
}
OS << " struct MaskRolOp {\n"
- " unsigned Mask;\n"
+ " LaneBitmask Mask;\n"
" uint8_t RotateLeft;\n"
" };\n"
" static const MaskRolOp LaneMaskComposeSequences[] = {\n";
@@ -749,9 +749,10 @@ RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS,
const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s];
for (size_t p = 0, pe = Sequence.size(); p != pe; ++p) {
const MaskRolPair &P = Sequence[p];
- OS << format("{ 0x%08X, %2u }, ", P.Mask, P.RotateLeft);
+ printMask(OS << "{ ", P.Mask);
+ OS << format(", %2u }, ", P.RotateLeft);
}
- OS << "{ 0, 0 }";
+ OS << "{ LaneBitmask::getNone(), 0 }";
if (s+1 != se)
OS << ", ";
OS << " // Sequence " << Idx << "\n";
@@ -774,12 +775,11 @@ RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS,
" const {\n"
" --IdxA; assert(IdxA < " << SubRegIndices.size()
<< " && \"Subregister index out of bounds\");\n"
- " LaneBitmask Result = 0;\n"
- " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask != 0; ++Ops)"
- " {\n"
- " LaneBitmask Masked = LaneMask & Ops->Mask;\n"
- " Result |= (Masked << Ops->RotateLeft) & 0xFFFFFFFF;\n"
- " Result |= (Masked >> ((32 - Ops->RotateLeft) & 0x1F));\n"
+ " LaneBitmask Result;\n"
+ " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; !Ops->Mask.none(); ++Ops) {\n"
+ " LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();\n"
+ " unsigned S = Ops->RotateLeft;\n"
+ " Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));\n"
" }\n"
" return Result;\n"
"}\n\n";
@@ -790,12 +790,11 @@ RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS,
" LaneMask &= getSubRegIndexLaneMask(IdxA);\n"
" --IdxA; assert(IdxA < " << SubRegIndices.size()
<< " && \"Subregister index out of bounds\");\n"
- " LaneBitmask Result = 0;\n"
- " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask != 0; ++Ops)"
- " {\n"
- " LaneBitmask Rotated = (LaneMask >> Ops->RotateLeft) |\n"
- " ((LaneMask << ((32 - Ops->RotateLeft) & 0x1F)) & 0xFFFFFFFF);\n"
- " Result |= Rotated & Ops->Mask;\n"
+ " LaneBitmask Result;\n"
+ " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; !Ops->Mask.none(); ++Ops) {\n"
+ " LaneBitmask::Type M = LaneMask.getAsInteger();\n"
+ " unsigned S = Ops->RotateLeft;\n"
+ " Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));\n"
" }\n"
" return Result;\n"
"}\n\n";
@@ -894,8 +893,8 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
LaneMaskVec.insert(LaneMaskVec.begin(), RUMasks.begin(), RUMasks.end());
// Terminator mask should not be used inside of the list.
#ifndef NDEBUG
- for (unsigned M : LaneMaskVec) {
- assert(M != ~0u && "terminator mask should not be part of the list");
+ for (LaneBitmask M : LaneMaskVec) {
+ assert(!M.all() && "terminator mask should not be part of the list");
}
#endif
LaneMaskSeqs.add(LaneMaskVec);
@@ -916,8 +915,8 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << "};\n\n";
// Emit the shared table of regunit lane mask sequences.
- OS << "extern const unsigned " << TargetName << "LaneMaskLists[] = {\n";
- LaneMaskSeqs.emit(OS, printMask, "~0u");
+ OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n";
+ LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()");
OS << "};\n\n";
// Emit the table of sub-register indexes.
@@ -1197,9 +1196,10 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << "\" };\n\n";
// Emit SubRegIndex lane masks, including 0.
- OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n";
+ OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n LaneBitmask::getAll(),\n";
for (const auto &Idx : SubRegIndices) {
- OS << format(" 0x%08x, // ", Idx.LaneMask) << Idx.getName() << '\n';
+ printMask(OS << " ", Idx.LaneMask);
+ OS << ", // " << Idx.getName() << '\n';
}
OS << " };\n\n";
@@ -1317,9 +1317,9 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
<< "MCRegisterClasses[" << RC.getName() << "RegClassID],\n "
<< "VTLists + " << VTSeqs.get(RC.VTs) << ",\n " << RC.getName()
<< "SubClassMask,\n SuperRegIdxSeqs + "
- << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n "
- << format("0x%08x,\n ", RC.LaneMask)
- << (unsigned)RC.AllocationPriority << ",\n "
+ << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n ";
+ printMask(OS, RC.LaneMask);
+ OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n "
<< (RC.HasDisjunctSubRegs?"true":"false")
<< ", /* HasDisjunctSubRegs */\n "
<< (RC.CoveredBySubRegs?"true":"false")
@@ -1408,7 +1408,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Emit the constructor of the class...
OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";
- OS << "extern const unsigned " << TargetName << "LaneMaskLists[];\n";
+ OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n";
OS << "extern const char " << TargetName << "RegStrings[];\n";
OS << "extern const char " << TargetName << "RegClassStrings[];\n";
OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
@@ -1423,8 +1423,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
<< "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n"
<< " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
- << " SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0x";
- OS.write_hex(RegBank.CoveringLanes);
+ << " SubRegIndexNameTable, SubRegIndexLaneMaskTable, ";
+ printMask(OS, RegBank.CoveringLanes);
OS << ") {\n"
<< " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1
<< ", RA, PC,\n " << TargetName
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